[PATCH] D130769: [RISCV] Combine and remove redundant ADD/SUB instructions

[Elena Lepilkina via Phabricator via llvm-commits]

eklepilkina added a comment.

Sorry for delay. I checked using InstCombine, but unfortuantely it doesn't help in all cases. I updated adds-combinations.ll test (please, have a look), even if I call opt with instcombine pass, it doesn't change IR in this case. Moreover, I made experiment where I added InstCombinePass after LoopStrengthReduce and measure performance, I got several regressions on benchmarks.


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https://reviews.llvm.org/D130769