[PATCH] D130075: [InstCombine] Try not to demand low order bits for Add

[Jay Foad via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2754ff883d9e: [InstCombine] Try not to demand low order bits for Add (authored by foad).
Herald added a subscriber: zzheng.

Changed prior to commit:
  https://reviews.llvm.org/D130075?vs=454515&id=454588#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130075/new/

https://reviews.llvm.org/D130075

Files:
  llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
  llvm/test/Transforms/InstCombine/add2.ll
  llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
  llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll

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