[PATCH] D130075: [InstCombine] Try not to demand low order bits for Add
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 22 12:04:09 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2754ff883d9e: [InstCombine] Try not to demand low order bits for Add (authored by foad).
Herald added a subscriber: zzheng.
Changed prior to commit:
https://reviews.llvm.org/D130075?vs=454515&id=454588#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D130075/new/
https://reviews.llvm.org/D130075
Files:
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
llvm/test/Transforms/InstCombine/add2.ll
llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D130075.454588.patch
Type: text/x-patch
Size: 9969 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220822/28ad1419/attachment.bin>
More information about the llvm-commits
mailing list