[PATCH] D132080: RegisterClassInfo: Fix CSR cache invalidation

[Nigel Perks via Phabricator via llvm-commits]

nigelp-xmos added a comment.

A problem was revealed on XCore because in scavenging.ll CSR is different in the second function than the first: a different hard-coded list of registers, with the different register being the last entry. In the loop comparing CSR with LastCSR, the condition “CSR[I] == 0 || I >= LastSize” combines two cases. In the first case, you do indeed want to set change = (I != LastSize). But in the second case, the lists have different length, and the change flag should be true, even if I == LastSize. I guess I can't add a code comment because this is committed but my fix is:

  if (CSR[I] == 0) {
    CSRChanged = I != LastSize;
    break;
  }
  if (I >= LastSize) {
    CSRChanged = true;
    break;
  }

The XCore test now generates the same code it did before. I've done no other testing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132080/new/

https://reviews.llvm.org/D132080