[PATCH] D132392: [SVE] Extend getMemVTFromNode to cover the sret variants of sve.ld2/3/4.

[Paul Walker via Phabricator via llvm-commits]

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This enables the use of reg+imm addressing modes to match the
non-sret variants of these intrinsics.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D132392

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll

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