[llvm] b2542c4 - RegisterClassInfo: Fix CSR cache invalidation
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 22 09:29:19 PDT 2022
Author: Matthias Braun
Date: 2022-08-22T09:28:26-07:00
New Revision: b2542c40b924acba8bf9708e938c184b77918ae4
URL: https://github.com/llvm/llvm-project/commit/b2542c40b924acba8bf9708e938c184b77918ae4
DIFF: https://github.com/llvm/llvm-project/commit/b2542c40b924acba8bf9708e938c184b77918ae4.diff
LOG: RegisterClassInfo: Fix CSR cache invalidation
`RegisterClassInfo` caches information like allocation orders and reuses
it for multiple machine functions where possible. However the `MCPhysReg
*CalleeSavedRegs` field used to test whether the set of callee saved
registers changed did not work: After D28566
`MachineRegisterInfo::getCalleeSavedRegs()` can return dynamically
computed CSR sets that are only valid while the `MachineRegisterInfo`
object of the current function exists.
This changes the code to make a copy of the CSR list instead of keeping
a possibly invalid pointer around.
Differential Revision: https://reviews.llvm.org/D132080
Added:
Modified:
llvm/include/llvm/CodeGen/RegisterClassInfo.h
llvm/lib/CodeGen/RegisterClassInfo.cpp
llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll
llvm/test/CodeGen/XCore/scavenging.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/RegisterClassInfo.h b/llvm/include/llvm/CodeGen/RegisterClassInfo.h
index 39c72a42c4334..4ee8952f529e6 100644
--- a/llvm/include/llvm/CodeGen/RegisterClassInfo.h
+++ b/llvm/include/llvm/CodeGen/RegisterClassInfo.h
@@ -52,10 +52,9 @@ class RegisterClassInfo {
const MachineFunction *MF = nullptr;
const TargetRegisterInfo *TRI = nullptr;
- // Callee saved registers of last MF. Assumed to be valid until the next
- // runOnFunction() call.
- // Used only to determine if an update was made to CalleeSavedAliases.
- const MCPhysReg *CalleeSavedRegs = nullptr;
+ // Callee saved registers of last MF.
+ // Used only to determine if an update for CalleeSavedAliases is necessary.
+ SmallVector<MCPhysReg, 16> LastCalleeSavedRegs;
// Map register alias to the callee saved Register.
SmallVector<MCPhysReg, 4> CalleeSavedAliases;
diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index 374fcc9a6014d..faed78e0117f1 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -52,22 +52,39 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
Update = true;
}
- // Does this MF have
diff erent CSRs?
- assert(TRI && "no register info set");
+ // Test if CSRs have changed from the previous function.
+ const MachineRegisterInfo &MRI = MF->getRegInfo();
+ const MCPhysReg *CSR = MRI.getCalleeSavedRegs();
+ bool CSRChanged = true;
+ if (!Update) {
+ CSRChanged = false;
+ size_t LastSize = LastCalleeSavedRegs.size();
+ for (unsigned I = 0;; ++I) {
+ if (CSR[I] == 0 || I >= LastSize) {
+ CSRChanged = I != LastSize;
+ break;
+ }
+ if (CSR[I] != LastCalleeSavedRegs[I]) {
+ CSRChanged = true;
+ break;
+ }
+ }
+ }
// Get the callee saved registers.
- const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
- if (Update || CSR != CalleeSavedRegs) {
+ if (CSRChanged) {
+ LastCalleeSavedRegs.clear();
// Build a CSRAlias map. Every CSR alias saves the last
// overlapping CSR.
CalleeSavedAliases.assign(TRI->getNumRegs(), 0);
- for (const MCPhysReg *I = CSR; *I; ++I)
+ for (const MCPhysReg *I = CSR; *I; ++I) {
for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
CalleeSavedAliases[*AI] = *I;
+ LastCalleeSavedRegs.push_back(*I);
+ }
Update = true;
}
- CalleeSavedRegs = CSR;
// Even if CSR list is same, we could have had a
diff erent allocation order
// if ignoreCSRForAllocationOrder is evaluated
diff erently.
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll b/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll
index c65a202e21087..270de9a055900 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll
@@ -101,7 +101,6 @@ entry:
define dso_local signext i32 @X2IsCallerSaved(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e, i32 signext %f, i32 signext %g, i32 signext %h) local_unnamed_addr {
; CHECK-ALL-LABEL: X2IsCallerSaved:
; CHECK-S: .localentry X2IsCallerSaved, 1
-; CHECK-P9-NOT: .localentry
; CHECK-ALL: # %bb.0: # %entry
; CHECK-S-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-S-NEXT: std r30, -16(r1) # 8-byte Folded Spill
diff --git a/llvm/test/CodeGen/XCore/scavenging.ll b/llvm/test/CodeGen/XCore/scavenging.ll
index adf313e4a9890..1c9f78be7eb5b 100644
--- a/llvm/test/CodeGen/XCore/scavenging.ll
+++ b/llvm/test/CodeGen/XCore/scavenging.ll
@@ -55,51 +55,52 @@ declare void @g(i32*, i32*)
; CHECK: .section .cp.rodata.cst4,"aMc", at progbits,4
; CHECK: .p2align 2
; CHECK: [[ARG5:.LCPI[0-9_]+]]:
-; CHECK: .long 100003
+; CHECK: .long 100002
; CHECK: [[INDEX0:.LCPI[0-9_]+]]:
-; CHECK: .long 80002
+; CHECK: .long 100004
; CHECK: [[INDEX1:.LCPI[0-9_]+]]:
-; CHECK: .long 81002
+; CHECK: .long 80002
; CHECK: [[INDEX2:.LCPI[0-9_]+]]:
-; CHECK: .long 82002
+; CHECK: .long 81002
; CHECK: [[INDEX3:.LCPI[0-9_]+]]:
-; CHECK: .long 83002
+; CHECK: .long 82002
; CHECK: [[INDEX4:.LCPI[0-9_]+]]:
+; CHECK: .long 83002
+; CHECK: [[INDEX5:.LCPI[0-9_]+]]:
; CHECK: .long 84002
; CHECK: .text
; !FP + large frame: spill SR+SR = entsp 2 + 100000
; CHECK-LABEL: ScavengeSlots:
; CHECK: entsp 65535
-; CHECK: extsp 34467
+; CHECK: extsp 34468
; scavenge r11
; CHECK: ldaw r11, sp[0]
; scavenge r4 using SR spill slot
; CHECK: stw r4, sp[1]
; CHECK: ldw r4, cp[[[ARG5]]]
; r11 used to load 5th argument
-; CHECK: ldw r11, r11[r4]
-; CHECK: ldaw r4, sp[0]
-; scavenge r5 using SR spill slot
-; CHECK: stw r5, sp[0]
-; CHECK: ldw r5, cp[[[INDEX0]]]
-; r4 & r5 used by InsertSPConstInst() to emit STW_l3r instruction.
-; CHECK: stw r0, r4[r5]
-; CHECK: ldaw r0, sp[0]
-; CHECK: ldw r5, cp[[[INDEX1]]]
-; CHECK: stw r1, r0[r5]
+; CHECK: stw r10, r11[r4]
+; CHECK: ldaw r10, sp[0]
+; CHECK: ldw r11, cp[[[INDEX0]]]
+; CHECK: ldw r10, r10[r11]
+; CHECK: ldaw r11, sp[0]
+; CHECK: ldw r4, cp[[[INDEX1]]]
+; CHECK: stw r0, r11[r4]
; CHECK: ldaw r0, sp[0]
-; CHECK: ldw r1, cp[[[INDEX2]]]
-; CHECK: stw r2, r0[r1]
+; CHECK: ldw r11, cp[[[INDEX2]]]
+; CHECK: stw r1, r0[r11]
; CHECK: ldaw r0, sp[0]
; CHECK: ldw r1, cp[[[INDEX3]]]
; CHECK: stw r3, r0[r1]
; CHECK: ldaw r0, sp[0]
-; CHECK: ldw r1, cp[[[INDEX4]]]
-; CHECK: stw r11, r0[r1]
+; CHECK: ldw r1, cp[[[INDEX5]]]
+; CHECK: stw r10, r0[r1]
+; CHECK: ldaw r10, sp[0]
+; CHECK: ldw r0, cp[[[ARG5]]]
+; CHECK: ldw r10, r10[r0]
; CHECK: ldaw sp, sp[65535]
; CHECK: ldw r4, sp[1]
-; CHECK: ldw r5, sp[0]
-; CHECK: retsp 34467
+; CHECK: retsp 34468
define void @ScavengeSlots(i32 %r0, i32 %r1, i32 %r2, i32 %r3, i32 %r4) nounwind {
entry:
%Data = alloca [100000 x i32]
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