[PATCH] D130692: [AArch64][SVE] Expand gather index to 32 bits instead of 64 bits

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau added a comment.

@paulwalker-arm I've extended `isVectorShrinkable` to shrink sign extendeded and zero extended gathers/scatters, however i'm seeing the following change to a pair of gather/scatter tests in sve-fixed-length-masked-gather.ll:

  ; CHECK-LABEL: masked_gather_32b_scaled_sext_f64:
  ; CHECK:       // %bb.0:
  ; CHECK-NEXT:    ptrue p0.d, vl32
  ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
  ; CHECK-NEXT:    ld1sw { z1.d }, p0/z, [x1]
  ; CHECK-NEXT:    fcmeq p1.d, p0/z, z0.d, #0.0
  ; CHECK-NEXT:    ld1d { z0.d }, p1/z, [x2, z1.d, lsl #3]
  ; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
  ; CHECK-NEXT:    ret
    %cvals = load <32 x



  ; CHECK-LABEL: masked_gather_32b_scaled_sext_f64:
  ; CHECK:       // %bb.0:
  ; CHECK-NEXT:    ptrue p0.d, vl32
  ; CHECK-NEXT:    ptrue p1.s, vl32
  ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
  ; CHECK-NEXT:    ld1w { z1.s }, p1/z, [x1]
  ; CHECK-NEXT:    fcmeq p1.d, p0/z, z0.d, #0.0
  ; CHECK-NEXT:    sunpklo z0.d, z1.s
  ; CHECK-NEXT:    ld1d { z0.d }, p1/z, [x2, z0.d, lsl #3]
  ; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
  ; CHECK-NEXT:    ret

  define void @masked_gather_32b_scaled_sext_f64(<32 x double>* %a, <32 x i32>* %b, double* %base) vscale_range(16,0) #0 {
    %cvals = load <32 x double>, <32 x double>* %a
    %idxs = load <32 x i32>, <32 x i32>* %b
    %ext = sext <32 x i32> %idxs to <32 x i64>
    %ptrs = getelementptr double, double* %base, <32 x i64> %ext
    %mask = fcmp oeq <32 x double> %cvals, zeroinitializer
    %vals = call <32 x double> @llvm.masked.gather.v32f64(<32 x double*> %ptrs, i32 8, <32 x i1> %mask, <32 x double> undef)
    store <32 x double> %vals, <32 x double>* %a
    ret void

The test specifically wants the sign-extend which makes sense, but with my changes in we ignore the sign extend and then unpack it pointlessly. I'm assuming I need to check that the gather predicate doesn't come from a comparison with a wider vector before shrinking the vector?


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  https://reviews.llvm.org/D130692/new/

https://reviews.llvm.org/D130692