[PATCH] D132358: [RISCV][ISel] improved compressed instruction use
Dmitry via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 22 02:14:09 PDT 2022
dybv-sc updated this revision to Diff 454424.
dybv-sc added a comment.
Fixed missing commit
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D132358/new/
https://reviews.llvm.org/D132358
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/codemodel-lowering.ll
llvm/test/CodeGen/RISCV/isel-compressed-comp.ll
Index: llvm/test/CodeGen/RISCV/isel-compressed-comp.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/isel-compressed-comp.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s
+
+declare void @foo()
+
+define void @bar(i64 %a) {
+; CHECK: slti
+; CHECK-NEXT: bnez
+ %c = icmp slt i64 255, %a
+ br i1 %c, label %taken, label %return
+taken:
+ call void @foo()
+ br label %return
+return:
+ ret void
+}
Index: llvm/test/CodeGen/RISCV/codemodel-lowering.ll
===================================================================
--- llvm/test/CodeGen/RISCV/codemodel-lowering.ll
+++ llvm/test/CodeGen/RISCV/codemodel-lowering.ll
@@ -58,9 +58,9 @@
; RV32I-SMALL-NEXT: addi sp, sp, -16
; RV32I-SMALL-NEXT: lui a1, %hi(.Ltmp0)
; RV32I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0)
-; RV32I-SMALL-NEXT: li a2, 101
+; RV32I-SMALL-NEXT: slti a0, a0, 101
; RV32I-SMALL-NEXT: sw a1, 8(sp)
-; RV32I-SMALL-NEXT: blt a0, a2, .LBB2_3
+; RV32I-SMALL-NEXT: bnez a0, .LBB2_3
; RV32I-SMALL-NEXT: # %bb.1: # %if.then
; RV32I-SMALL-NEXT: lw a0, 8(sp)
; RV32I-SMALL-NEXT: jr a0
@@ -80,9 +80,9 @@
; RV32I-MEDIUM-NEXT: .Lpcrel_hi2:
; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0)
; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi2)
-; RV32I-MEDIUM-NEXT: li a2, 101
+; RV32I-MEDIUM-NEXT: slti a0, a0, 101
; RV32I-MEDIUM-NEXT: sw a1, 8(sp)
-; RV32I-MEDIUM-NEXT: blt a0, a2, .LBB2_3
+; RV32I-MEDIUM-NEXT: bnez a0, .LBB2_3
; RV32I-MEDIUM-NEXT: # %bb.1: # %if.then
; RV32I-MEDIUM-NEXT: lw a0, 8(sp)
; RV32I-MEDIUM-NEXT: jr a0
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1329,6 +1329,10 @@
defm : BccPat<SETULT, BLTU>;
defm : BccPat<SETUGE, BGEU>;
+// Try to produce compressed bnez instruction if possible
+def : Pat<(riscv_brcc GPR:$rs1, simm12:$c, SETLT, bb:$imm12),
+ (BNE (SLTI GPR:$rs1, simm12:$c), X0, simm13_lsb0:$imm12)>;
+
let isBarrier = 1, isBranch = 1, isTerminator = 1 in
def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>;
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