[PATCH] D132137: [InstCombine] For vector extract when extract vector and insert value type is the same

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/test/Transforms/InstCombine/opts-tuples-extract-intrinsic.ll:20
+; CHECK-LABEL: @test_extract_insert_dif_idx(
+; CHECK-NEXT:    [[VEC_EXT:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[V0:%.*]], i64 0)
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[VEC_EXT]]
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I am not sure this transform is correct.

My understanding of the documentation is that these are inserting *vectors* not single elements.  Given that, don't we need to prove that the vectors don't overlap?

In this example, if vscale = 6 on real hardware, isn't this transform unsound?

If it is sound, the semantics of the insert/extract intrinsics are non-obvious with regards to indexing, and the docs could be improved.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132137/new/

https://reviews.llvm.org/D132137