[llvm] 1492c88 - [PowerPC] Fix bugs in sign-/zero-extension elimination
Stefan Pintilie via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 19 05:05:50 PDT 2022
Author: Stefan Pintilie
Date: 2022-08-19T07:05:40-05:00
New Revision: 1492c88f494cb09de0ebc7fb77a84c41d0aa93ce
URL: https://github.com/llvm/llvm-project/commit/1492c88f494cb09de0ebc7fb77a84c41d0aa93ce
DIFF: https://github.com/llvm/llvm-project/commit/1492c88f494cb09de0ebc7fb77a84c41d0aa93ce.diff
LOG: [PowerPC] Fix bugs in sign-/zero-extension elimination
This patch fixes the following two bugs in `PPCInstrInfo::isSignOrZeroExtended` helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass.
- Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer).
- Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension).
To handle the first case, the parameter for the helpers is changed from `MachineInstr` to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D40554
Added:
llvm/test/CodeGen/PowerPC/sext_elimination.mir
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/lib/Target/PowerPC/PPCInstrFormats.td
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrP10.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
llvm/test/CodeGen/PowerPC/bcd-intrinsics.ll
llvm/test/CodeGen/PowerPC/csr-split.ll
llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
llvm/test/CodeGen/PowerPC/expand-isel.ll
llvm/test/CodeGen/PowerPC/f128-conv.ll
llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
llvm/test/CodeGen/PowerPC/fp-strict-conv.ll
llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
llvm/test/CodeGen/PowerPC/machine-pre.ll
llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
llvm/test/CodeGen/PowerPC/optcmp.ll
llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll
llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll
llvm/test/CodeGen/PowerPC/pr41088.ll
llvm/test/CodeGen/PowerPC/pr47660.ll
llvm/test/CodeGen/PowerPC/prefer-dqform.ll
llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll
llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll
llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll
llvm/test/CodeGen/PowerPC/select-constant-xor.ll
llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll
llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll
llvm/test/CodeGen/PowerPC/store-forward-be64.ll
llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index ad347855b38e..8843bd8cae8a 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11492,7 +11492,8 @@ static bool isSignExtended(MachineInstr &MI, const PPCInstrInfo *TII) {
default:
return false;
case PPC::COPY:
- return TII->isSignExtended(MI);
+ return TII->isSignExtended(MI.getOperand(1).getReg(),
+ &MI.getMF()->getRegInfo());
case PPC::LHA:
case PPC::LHA8:
case PPC::LHAU:
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 7d648b1429be..456461af190b 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -644,10 +644,10 @@ let isCodeGenOnly = 1 in {
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
"li $rD, $imm", IIC_IntSimple,
- [(set i64:$rD, imm64SExt16:$imm)]>;
+ [(set i64:$rD, imm64SExt16:$imm)]>, SExt32To64;
def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
"lis $rD, $imm", IIC_IntSimple,
- [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
+ [(set i64:$rD, imm16ShiftedSExt:$imm)]>, SExt32To64;
}
// Logical ops.
@@ -687,11 +687,11 @@ let Defs = [CR0] in {
def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
"andi. $dst, $src1, $src2", IIC_IntGeneral,
[(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
- isRecordForm;
+ isRecordForm, SExt32To64, ZExt32To64;
def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
"andis. $dst, $src1, $src2", IIC_IntGeneral,
[(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
- isRecordForm;
+ isRecordForm, ZExt32To64;
}
def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
"ori $dst, $src1, $src2", IIC_IntSimple,
@@ -898,39 +898,44 @@ defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS),
- "cntlzw", "$rA, $rS", IIC_IntGeneral, []>;
+ "cntlzw", "$rA, $rS", IIC_IntGeneral, []>,
+ ZExt32To64, SExt32To64;
defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS),
"cnttzw", "$rA, $rS", IIC_IntGeneral, []>,
- Requires<[IsISA3_0]>;
+ Requires<[IsISA3_0]>, ZExt32To64, SExt32To64;
defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
"extsb", "$rA, $rS", IIC_IntSimple,
- [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
+ [(set i64:$rA, (sext_inreg i64:$rS, i8))]>, SExt32To64;
defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
"extsh", "$rA, $rS", IIC_IntSimple,
- [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
+ [(set i64:$rA, (sext_inreg i64:$rS, i16))]>, SExt32To64;
defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
- "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
+ "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>, ZExt32To64;
defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
- "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
+ "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>, ZExt32To64;
} // Interpretation64Bit
// For fast-isel:
let isCodeGenOnly = 1 in {
def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
- "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
+ "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64,
+ SExt32To64;
def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
- "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
+ "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64,
+ SExt32To64;
} // isCodeGenOnly for fast-isel
defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
"extsw", "$rA, $rS", IIC_IntSimple,
- [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
+ [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64,
+ SExt32To64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
"extsw", "$rA, $rS", IIC_IntSimple,
- [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
+ [(set i64:$rA, (sext i32:$rS))]>, isPPC64,
+ SExt32To64;
let isCodeGenOnly = 1 in
def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS),
"extsw $rA, $rS", IIC_IntSimple,
@@ -959,13 +964,16 @@ def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH),
defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
"cntlzd", "$rA, $rS", IIC_IntGeneral,
- [(set i64:$rA, (ctlz i64:$rS))]>;
+ [(set i64:$rA, (ctlz i64:$rS))]>,
+ ZExt32To64, SExt32To64;
defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS),
"cnttzd", "$rA, $rS", IIC_IntGeneral,
- [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>;
+ [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>,
+ ZExt32To64, SExt32To64;
def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
"popcntd $rA, $rS", IIC_IntGeneral,
- [(set i64:$rA, (ctpop i64:$rS))]>;
+ [(set i64:$rA, (ctpop i64:$rS))]>,
+ ZExt32To64, SExt32To64;
def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"bpermd $rA, $rS, $rB", IIC_IntGeneral,
[(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>,
@@ -1016,7 +1024,7 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
[(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>,
isPPC64;
def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
- "setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
+ "setb $RT, $BFA", IIC_IntGeneral>, isPPC64, SExt32To64;
}
def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),
"addpcis $RT, $D", IIC_BrB, []>, isPPC64;
@@ -1238,29 +1246,29 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
"lha $rD, $src", IIC_LdStLHA,
[(set i64:$rD, (sextloadi16 DForm:$src))]>,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
"lwa $rD, $src", IIC_LdStLWA,
[(set i64:$rD,
(sextloadi32 DSForm:$src))]>, isPPC64,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src),
"lhax $rD, $src", IIC_LdStLHA,
[(set i64:$rD, (sextloadi16 XForm:$src))]>,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src),
"lwax $rD, $src", IIC_LdStLHA,
[(set i64:$rD, (sextloadi32 XForm:$src))]>, isPPC64,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
// For fast-isel:
let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in {
def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
"lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src),
"lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
} // end fast-isel isCodeGenOnly
// Update forms.
@@ -1292,23 +1300,29 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
let PPC970_Unit = 2 in {
def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
"lbz $rD, $src", IIC_LdStLoad,
- [(set i64:$rD, (zextloadi8 DForm:$src))]>;
+ [(set i64:$rD, (zextloadi8 DForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
"lhz $rD, $src", IIC_LdStLoad,
- [(set i64:$rD, (zextloadi16 DForm:$src))]>;
+ [(set i64:$rD, (zextloadi16 DForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
"lwz $rD, $src", IIC_LdStLoad,
- [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64;
+ [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64,
+ ZExt32To64;
def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src),
"lbzx $rD, $src", IIC_LdStLoad,
- [(set i64:$rD, (zextloadi8 XForm:$src))]>;
+ [(set i64:$rD, (zextloadi8 XForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src),
"lhzx $rD, $src", IIC_LdStLoad,
- [(set i64:$rD, (zextloadi16 XForm:$src))]>;
+ [(set i64:$rD, (zextloadi16 XForm:$src))]>,
+ ZExt32To64, SExt32To64;
def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src),
"lwzx $rD, $src", IIC_LdStLoad,
- [(set i64:$rD, (zextloadi32 XForm:$src))]>;
+ [(set i64:$rD, (zextloadi32 XForm:$src))]>,
+ ZExt32To64;
// Update forms.
@@ -1386,9 +1400,9 @@ def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src),
let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src),
- "lhbrx $rD, $src", IIC_LdStLoad, []>;
+ "lhbrx $rD, $src", IIC_LdStLoad, []>, ZExt32To64;
def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src),
- "lwbrx $rD, $src", IIC_LdStLoad, []>;
+ "lwbrx $rD, $src", IIC_LdStLoad, []>, ZExt32To64;
}
let mayLoad = 1, hasSideEffects = 0 in {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
index fe21a164dfab..86cb528a537f 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -1448,12 +1448,12 @@ def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>;
// Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
let hasSideEffects = 0 in {
-def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>;
-def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>;
-def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>;
-def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>;
-def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>;
-def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>;
+def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>, ZExt32To64;
+def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>, ZExt32To64;
+def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>, ZExt32To64;
+def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>, ZExt32To64;
+def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>, ZExt32To64;
+def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>, ZExt32To64;
}
// Vector Insert Element Instructions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index f7e4c0708d7d..d4d7f1107b03 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -44,6 +44,16 @@ class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
// Indicate that this instruction is prefixed.
bits<1> Prefixed = 0;
let TSFlags{7} = Prefixed;
+
+ // Indicate that this instruction produces a result that is sign extended from
+ // 32 bits to 64 bits.
+ bits<1> SExt32To64 = 0;
+ let TSFlags{8} = SExt32To64;
+
+ // Indicate that this instruction produces a result that is zero extended from
+ // 32 bits to 64 bits.
+ bits<1> ZExt32To64 = 0;
+ let TSFlags{9} = ZExt32To64;
// Fields used for relation models.
string BaseName = "";
@@ -70,6 +80,8 @@ class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
class XFormMemOp { bits<1> XFormMemOp = 1; }
+class SExt32To64 { bits<1> SExt32To64 = 1; }
+class ZExt32To64 { bits<1> ZExt32To64 = 1; }
// Two joined instructions; used to emit two adjacent instructions as one.
// The itinerary from the first instruction is used for scheduling and
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index de9cee0c31eb..eb875b0b63e0 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -17,6 +17,7 @@
#include "PPCInstrBuilder.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCTargetMachine.h"
+#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
@@ -2423,15 +2424,15 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
bool noSub = false;
if (isPPC64) {
if (is32BitSignedCompare) {
- // We can perform this optimization only if MI is sign-extending.
- if (isSignExtended(*MI))
+ // We can perform this optimization only if SrcReg is sign-extending.
+ if (isSignExtended(SrcReg, MRI))
noSub = true;
else
return false;
} else if (is32BitUnsignedCompare) {
- // We can perform this optimization, equality only, if MI is
+ // We can perform this optimization, equality only, if SrcReg is
// zero-extending.
- if (isZeroExtended(*MI)) {
+ if (isZeroExtended(SrcReg, MRI)) {
noSub = true;
equalityOnly = true;
} else
@@ -5128,51 +5129,87 @@ int PPCInstrInfo::getRecordFormOpcode(unsigned Opcode) {
return PPC::getRecordFormOpcode(Opcode);
}
-// This function returns true if the machine instruction
-// always outputs a value by sign-extending a 32 bit value,
-// i.e. 0 to 31-th bits are same as 32-th bit.
-static bool isSignExtendingOp(const MachineInstr &MI) {
- int Opcode = MI.getOpcode();
- if (Opcode == PPC::LI || Opcode == PPC::LI8 || Opcode == PPC::LIS ||
- Opcode == PPC::LIS8 || Opcode == PPC::SRAW || Opcode == PPC::SRAW_rec ||
- Opcode == PPC::SRAWI || Opcode == PPC::SRAWI_rec || Opcode == PPC::LWA ||
- Opcode == PPC::LWAX || Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
- Opcode == PPC::LHA || Opcode == PPC::LHAX || Opcode == PPC::LHA8 ||
- Opcode == PPC::LHAX8 || Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
- Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || Opcode == PPC::LBZU ||
- Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
- Opcode == PPC::LHZ || Opcode == PPC::LHZX || Opcode == PPC::LHZ8 ||
- Opcode == PPC::LHZX8 || Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
- Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 || Opcode == PPC::EXTSB ||
- Opcode == PPC::EXTSB_rec || Opcode == PPC::EXTSH ||
- Opcode == PPC::EXTSH_rec || Opcode == PPC::EXTSB8 ||
- Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSW ||
- Opcode == PPC::EXTSW_rec || Opcode == PPC::SETB || Opcode == PPC::SETB8 ||
- Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
- Opcode == PPC::EXTSB8_32_64)
+static bool isOpZeroOfSubwordPreincLoad(int Opcode) {
+ return (Opcode == PPC::LBZU || Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 ||
+ Opcode == PPC::LBZUX8 || Opcode == PPC::LHZU ||
+ Opcode == PPC::LHZUX || Opcode == PPC::LHZU8 ||
+ Opcode == PPC::LHZUX8);
+}
+
+// This function checks for sign extension from 32 bits to 64 bits.
+static bool definedBySignExtendingOp(const unsigned Reg,
+ const MachineRegisterInfo *MRI) {
+ if (!Register::isVirtualRegister(Reg))
+ return false;
+
+ MachineInstr *MI = MRI->getVRegDef(Reg);
+ if (!MI)
+ return false;
+
+ int Opcode = MI->getOpcode();
+ const PPCInstrInfo *TII =
+ MI->getMF()->getSubtarget<PPCSubtarget>().getInstrInfo();
+ if (TII->isSExt32To64(Opcode))
+ return true;
+
+ // The first def of LBZU/LHZU is sign extended.
+ if (isOpZeroOfSubwordPreincLoad(Opcode) && MI->getOperand(0).getReg() == Reg)
return true;
- if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
+ // RLDICL generates sign-extended output if it clears at least
+ // 33 bits from the left (MSB).
+ if (Opcode == PPC::RLDICL && MI->getOperand(3).getImm() >= 33)
return true;
+ // If at least one bit from left in a lower word is masked out,
+ // all of 0 to 32-th bits of the output are cleared.
+ // Hence the output is already sign extended.
if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec) &&
- MI.getOperand(3).getImm() > 0 &&
- MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
+ MI->getOperand(3).getImm() > 0 &&
+ MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
return true;
+ // If the most significant bit of immediate in ANDIS is zero,
+ // all of 0 to 32-th bits are cleared.
+ if (Opcode == PPC::ANDIS_rec || Opcode == PPC::ANDIS8_rec) {
+ uint16_t Imm = MI->getOperand(2).getImm();
+ if ((Imm & 0x8000) == 0)
+ return true;
+ }
+
return false;
}
-// This function returns true if the machine instruction
-// always outputs zeros in higher 32 bits.
-static bool isZeroExtendingOp(const MachineInstr &MI) {
- int Opcode = MI.getOpcode();
+// This function checks the machine instruction that defines the input register
+// Reg. If that machine instruction always outputs a value that has only zeros
+// in the higher 32 bits then this function will return true.
+static bool definedByZeroExtendingOp(const unsigned Reg,
+ const MachineRegisterInfo *MRI) {
+ if (!Register::isVirtualRegister(Reg))
+ return false;
+
+ MachineInstr *MI = MRI->getVRegDef(Reg);
+ if (!MI)
+ return false;
+
+ int Opcode = MI->getOpcode();
+ const PPCInstrInfo *TII =
+ MI->getMF()->getSubtarget<PPCSubtarget>().getInstrInfo();
+ if (TII->isZExt32To64(Opcode))
+ return true;
+
+ // The first def of LBZU/LHZU/LWZU are zero extended.
+ if ((isOpZeroOfSubwordPreincLoad(Opcode) || Opcode == PPC::LWZU ||
+ Opcode == PPC::LWZUX || Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8) &&
+ MI->getOperand(0).getReg() == Reg)
+ return true;
+
// The 16-bit immediate is sign-extended in li/lis.
// If the most significant bit is zero, all higher bits are zero.
if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
Opcode == PPC::LIS || Opcode == PPC::LIS8) {
- int64_t Imm = MI.getOperand(1).getImm();
+ int64_t Imm = MI->getOperand(1).getImm();
if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
return true;
}
@@ -5182,44 +5219,18 @@ static bool isZeroExtendingOp(const MachineInstr &MI) {
if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec ||
Opcode == PPC::RLDICL_32_64) &&
- MI.getOperand(3).getImm() >= 32)
+ MI->getOperand(3).getImm() >= 32)
return true;
if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) &&
- MI.getOperand(3).getImm() >= 32 &&
- MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
+ MI->getOperand(3).getImm() >= 32 &&
+ MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
return true;
if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec ||
Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
- MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
- return true;
-
- // There are other instructions that clear higher 32-bits.
- if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec ||
- Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec ||
- Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
- Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec ||
- Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec ||
- Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW || Opcode == PPC::SLW ||
- Opcode == PPC::SLW_rec || Opcode == PPC::SRW || Opcode == PPC::SRW_rec ||
- Opcode == PPC::SLW8 || Opcode == PPC::SRW8 || Opcode == PPC::SLWI ||
- Opcode == PPC::SLWI_rec || Opcode == PPC::SRWI ||
- Opcode == PPC::SRWI_rec || Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
- Opcode == PPC::LWZU || Opcode == PPC::LWZUX || Opcode == PPC::LWBRX ||
- Opcode == PPC::LHBRX || Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
- Opcode == PPC::LHZU || Opcode == PPC::LHZUX || Opcode == PPC::LBZ ||
- Opcode == PPC::LBZX || Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
- Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 || Opcode == PPC::LWZU8 ||
- Opcode == PPC::LWZUX8 || Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
- Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || Opcode == PPC::LHZU8 ||
- Opcode == PPC::LHZUX8 || Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
- Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
- Opcode == PPC::ANDI_rec || Opcode == PPC::ANDIS_rec ||
- Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWI_rec ||
- Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWI_rec ||
- Opcode == PPC::MFVSRWZ)
+ MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
return true;
return false;
@@ -5242,98 +5253,126 @@ bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
// We limit the max depth to track incoming values of PHIs or binary ops
// (e.g. AND) to avoid excessive cost.
-const unsigned MAX_DEPTH = 1;
-
-bool
-PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
- const unsigned Depth) const {
- const MachineFunction *MF = MI.getParent()->getParent();
- const MachineRegisterInfo *MRI = &MF->getRegInfo();
-
- // If we know this instruction returns sign- or zero-extended result,
- // return true.
- if (SignExt ? isSignExtendingOp(MI):
- isZeroExtendingOp(MI))
- return true;
-
- switch (MI.getOpcode()) {
+const unsigned MAX_BINOP_DEPTH = 1;
+// The isSignOrZeroExtended function is recursive. The parameter BinOpDepth
+// does not count all of the recursions. The parameter BinOpDepth is incremented
+// only when isSignOrZeroExtended calls itself more than once. This is done to
+// prevent expontential recursion. There is no parameter to track linear
+// recursion.
+std::pair<bool, bool>
+PPCInstrInfo::isSignOrZeroExtended(const unsigned Reg,
+ const unsigned BinOpDepth,
+ const MachineRegisterInfo *MRI) const {
+ if (!Register::isVirtualRegister(Reg))
+ return std::pair<bool, bool>(false, false);
+
+ MachineInstr *MI = MRI->getVRegDef(Reg);
+ if (!MI)
+ return std::pair<bool, bool>(false, false);
+
+ bool IsSExt = definedBySignExtendingOp(Reg, MRI);
+ bool IsZExt = definedByZeroExtendingOp(Reg, MRI);
+
+ // If we know the instruction always returns sign- and zero-extended result,
+ // return here.
+ if (IsSExt && IsZExt)
+ return std::pair<bool, bool>(IsSExt, IsZExt);
+
+ switch (MI->getOpcode()) {
case PPC::COPY: {
- Register SrcReg = MI.getOperand(1).getReg();
+ Register SrcReg = MI->getOperand(1).getReg();
// In both ELFv1 and v2 ABI, method parameters and the return value
// are sign- or zero-extended.
- if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
- const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
- // We check the ZExt/SExt flags for a method parameter.
- if (MI.getParent()->getBasicBlock() ==
- &MF->getFunction().getEntryBlock()) {
- Register VReg = MI.getOperand(0).getReg();
- if (MF->getRegInfo().isLiveIn(VReg))
- return SignExt ? FuncInfo->isLiveInSExt(VReg) :
- FuncInfo->isLiveInZExt(VReg);
- }
+ const MachineFunction *MF = MI->getMF();
- // For a method return value, we check the ZExt/SExt flags in attribute.
- // We assume the following code sequence for method call.
- // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
- // BL8_NOP @func,...
- // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
- // %5 = COPY %x3; G8RC:%5
- if (SrcReg == PPC::X3) {
- const MachineBasicBlock *MBB = MI.getParent();
- MachineBasicBlock::const_instr_iterator II =
- MachineBasicBlock::const_instr_iterator(&MI);
- if (II != MBB->instr_begin() &&
- (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
- const MachineInstr &CallMI = *(--II);
- if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
- const Function *CalleeFn =
- dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
- if (!CalleeFn)
- return false;
- const IntegerType *IntTy =
- dyn_cast<IntegerType>(CalleeFn->getReturnType());
- const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
- if (IntTy && IntTy->getBitWidth() <= 32)
- return Attrs.hasAttribute(SignExt ? Attribute::SExt :
- Attribute::ZExt);
- }
- }
+ if (!MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
+ // If this is a copy from another register, we recursively check source.
+ auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+ return std::pair<bool, bool>(SrcExt.first || IsSExt,
+ SrcExt.second || IsZExt);
+ }
+
+ // From here on everything is SVR4ABI
+ const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
+ // We check the ZExt/SExt flags for a method parameter.
+ if (MI->getParent()->getBasicBlock() ==
+ &MF->getFunction().getEntryBlock()) {
+ Register VReg = MI->getOperand(0).getReg();
+ if (MF->getRegInfo().isLiveIn(VReg)) {
+ IsSExt |= FuncInfo->isLiveInSExt(VReg);
+ IsZExt |= FuncInfo->isLiveInZExt(VReg);
+ return std::pair<bool, bool>(IsSExt, IsZExt);
}
}
- // If this is a copy from another register, we recursively check source.
- if (!Register::isVirtualRegister(SrcReg))
- return false;
- const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
- if (SrcMI != nullptr)
- return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
+ if (SrcReg != PPC::X3) {
+ // If this is a copy from another register, we recursively check source.
+ auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+ return std::pair<bool, bool>(SrcExt.first || IsSExt,
+ SrcExt.second || IsZExt);
+ }
- return false;
+ // For a method return value, we check the ZExt/SExt flags in attribute.
+ // We assume the following code sequence for method call.
+ // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
+ // BL8_NOP @func,...
+ // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
+ // %5 = COPY %x3; G8RC:%5
+ const MachineBasicBlock *MBB = MI->getParent();
+ std::pair<bool, bool> IsExtendPair = std::pair<bool, bool>(IsSExt, IsZExt);
+ MachineBasicBlock::const_instr_iterator II =
+ MachineBasicBlock::const_instr_iterator(MI);
+ if (II == MBB->instr_begin() || (--II)->getOpcode() != PPC::ADJCALLSTACKUP)
+ return IsExtendPair;
+
+ const MachineInstr &CallMI = *(--II);
+ if (!CallMI.isCall() || !CallMI.getOperand(0).isGlobal())
+ return IsExtendPair;
+
+ const Function *CalleeFn =
+ dyn_cast_if_present<Function>(CallMI.getOperand(0).getGlobal());
+ if (!CalleeFn)
+ return IsExtendPair;
+ const IntegerType *IntTy = dyn_cast<IntegerType>(CalleeFn->getReturnType());
+ if (IntTy && IntTy->getBitWidth() <= 32) {
+ const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
+ IsSExt |= Attrs.hasAttribute(Attribute::SExt);
+ IsZExt |= Attrs.hasAttribute(Attribute::ZExt);
+ return std::pair<bool, bool>(IsSExt, IsZExt);
+ }
+
+ return IsExtendPair;
}
- case PPC::ANDI_rec:
- case PPC::ANDIS_rec:
+ // OR, XOR with 16-bit immediate does not change the upper 48 bits.
+ // So, we track the operand register as we do for register copy.
case PPC::ORI:
- case PPC::ORIS:
case PPC::XORI:
- case PPC::XORIS:
- case PPC::ANDI8_rec:
- case PPC::ANDIS8_rec:
case PPC::ORI8:
+ case PPC::XORI8: {
+ unsigned SrcReg = MI->getOperand(1).getReg();
+ auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+ return std::pair<bool, bool>(SrcExt.first || IsSExt,
+ SrcExt.second || IsZExt);
+ }
+
+ // OR, XOR with shifted 16-bit immediate does not change the upper
+ // 32 bits. So, we track the operand register for zero extension.
+ // For sign extension when the MSB of the immediate is zero, we also
+ // track the operand register since the upper 33 bits are unchanged.
+ case PPC::ORIS:
+ case PPC::XORIS:
case PPC::ORIS8:
- case PPC::XORI8:
case PPC::XORIS8: {
- // logical operation with 16-bit immediate does not change the upper bits.
- // So, we track the operand register as we do for register copy.
- Register SrcReg = MI.getOperand(1).getReg();
- if (!Register::isVirtualRegister(SrcReg))
- return false;
- const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
- if (SrcMI != nullptr)
- return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
-
- return false;
+ unsigned SrcReg = MI->getOperand(1).getReg();
+ auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+ uint16_t Imm = MI->getOperand(2).getImm();
+ if (Imm & 0x8000)
+ return std::pair<bool, bool>(false, SrcExt.second || IsZExt);
+ else
+ return std::pair<bool, bool>(SrcExt.first || IsSExt,
+ SrcExt.second || IsZExt);
}
// If all incoming values are sign-/zero-extended,
@@ -5342,31 +5381,29 @@ PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
case PPC::OR8:
case PPC::ISEL:
case PPC::PHI: {
- if (Depth >= MAX_DEPTH)
- return false;
+ if (BinOpDepth >= MAX_BINOP_DEPTH)
+ return std::pair<bool, bool>(false, false);
// The input registers for PHI are operand 1, 3, ...
// The input registers for others are operand 1 and 2.
- unsigned E = 3, D = 1;
- if (MI.getOpcode() == PPC::PHI) {
- E = MI.getNumOperands();
- D = 2;
+ unsigned OperandEnd = 3, OperandStride = 1;
+ if (MI->getOpcode() == PPC::PHI) {
+ OperandEnd = MI->getNumOperands();
+ OperandStride = 2;
}
- for (unsigned I = 1; I != E; I += D) {
- if (MI.getOperand(I).isReg()) {
- Register SrcReg = MI.getOperand(I).getReg();
- if (!Register::isVirtualRegister(SrcReg))
- return false;
- const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
- if (SrcMI == nullptr ||
- !isSignOrZeroExtended(*SrcMI, SignExt, Depth + 1))
- return false;
- }
- else
- return false;
+ IsSExt = true;
+ IsZExt = true;
+ for (unsigned I = 1; I != OperandEnd; I += OperandStride) {
+ if (!MI->getOperand(I).isReg())
+ return std::pair<bool, bool>(false, false);
+
+ unsigned SrcReg = MI->getOperand(I).getReg();
+ auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth + 1, MRI);
+ IsSExt &= SrcExt.first;
+ IsZExt &= SrcExt.second;
}
- return true;
+ return std::pair<bool, bool>(IsSExt, IsZExt);
}
// If at least one of the incoming values of an AND is zero extended
@@ -5374,35 +5411,21 @@ PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
// are sign-extended then the output is also sign extended.
case PPC::AND:
case PPC::AND8: {
- if (Depth >= MAX_DEPTH)
- return false;
-
- assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
-
- Register SrcReg1 = MI.getOperand(1).getReg();
- Register SrcReg2 = MI.getOperand(2).getReg();
-
- if (!Register::isVirtualRegister(SrcReg1) ||
- !Register::isVirtualRegister(SrcReg2))
- return false;
-
- const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
- const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
- if (!MISrc1 || !MISrc2)
- return false;
-
- if(SignExt)
- return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
- isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
- else
- return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
- isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
+ if (BinOpDepth >= MAX_BINOP_DEPTH)
+ return std::pair<bool, bool>(false, false);
+
+ unsigned SrcReg1 = MI->getOperand(1).getReg();
+ unsigned SrcReg2 = MI->getOperand(2).getReg();
+ auto Src1Ext = isSignOrZeroExtended(SrcReg1, BinOpDepth + 1, MRI);
+ auto Src2Ext = isSignOrZeroExtended(SrcReg2, BinOpDepth + 1, MRI);
+ return std::pair<bool, bool>(Src1Ext.first && Src2Ext.first,
+ Src1Ext.second || Src2Ext.second);
}
default:
break;
}
- return false;
+ return std::pair<bool, bool>(IsSExt, IsZExt);
}
bool PPCInstrInfo::isBDNZ(unsigned Opcode) const {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 980bb3107a8b..26e9d0e52d57 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -67,7 +67,11 @@ enum {
/// This instruction is an X-Form memory operation.
XFormMemOp = 0x1 << NewDef_Shift,
/// This instruction is prefixed.
- Prefixed = 0x1 << (NewDef_Shift+1)
+ Prefixed = 0x1 << (NewDef_Shift + 1),
+ /// This instruction produced a sign extended result.
+ SExt32To64 = 0x1 << (NewDef_Shift + 2),
+ /// This instruction produced a zero extended result.
+ ZExt32To64 = 0x1 << (NewDef_Shift + 3)
};
} // end namespace PPCII
@@ -294,6 +298,12 @@ class PPCInstrInfo : public PPCGenInstrInfo {
bool isPrefixed(unsigned Opcode) const {
return get(Opcode).TSFlags & PPCII::Prefixed;
}
+ bool isSExt32To64(unsigned Opcode) const {
+ return get(Opcode).TSFlags & PPCII::SExt32To64;
+ }
+ bool isZExt32To64(unsigned Opcode) const {
+ return get(Opcode).TSFlags & PPCII::ZExt32To64;
+ }
/// Check if Opcode corresponds to a call instruction that should be marked
/// with the NOTOC relocation.
@@ -687,19 +697,20 @@ class PPCInstrInfo : public PPCGenInstrInfo {
bool isTOCSaveMI(const MachineInstr &MI) const;
- bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
- const unsigned PhiDepth) const;
+ std::pair<bool, bool>
+ isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth,
+ const MachineRegisterInfo *MRI) const;
- /// Return true if the output of the instruction is always a sign-extended,
- /// i.e. 0 to 31-th bits are same as 32-th bit.
- bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
- return isSignOrZeroExtended(MI, true, depth);
+ // Return true if the register is sign-extended from 32 to 64 bits.
+ bool isSignExtended(const unsigned Reg,
+ const MachineRegisterInfo *MRI) const {
+ return isSignOrZeroExtended(Reg, 0, MRI).first;
}
- /// Return true if the output of the instruction is always zero-extended,
- /// i.e. 0 to 31-th bits are all zeros
- bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
- return isSignOrZeroExtended(MI, false, depth);
+ // Return true if the register is zero-extended from 32 to 64 bits.
+ bool isZeroExtended(const unsigned Reg,
+ const MachineRegisterInfo *MRI) const {
+ return isSignOrZeroExtended(Reg, 0, MRI).second;
}
bool convertToImmediateForm(MachineInstr &MI,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 212a0e08f545..b390bf059abe 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1791,17 +1791,19 @@ def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS),
let PPC970_Unit = 2 in {
def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
"lbz $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (zextloadi8 DForm:$src))]>;
+ [(set i32:$rD, (zextloadi8 DForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
"lha $rD, $src", IIC_LdStLHA,
[(set i32:$rD, (sextloadi16 DForm:$src))]>,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
"lhz $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (zextloadi16 DForm:$src))]>;
+ [(set i32:$rD, (zextloadi16 DForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
"lwz $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (load DForm:$src))]>;
+ [(set i32:$rD, (load DForm:$src))]>, ZExt32To64;
let Predicates = [HasFPU] in {
def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
@@ -1894,23 +1896,25 @@ def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in {
def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src),
"lbzx $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (zextloadi8 XForm:$src))]>;
+ [(set i32:$rD, (zextloadi8 XForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src),
"lhax $rD, $src", IIC_LdStLHA,
[(set i32:$rD, (sextloadi16 XForm:$src))]>,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src),
"lhzx $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (zextloadi16 XForm:$src))]>;
+ [(set i32:$rD, (zextloadi16 XForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src),
"lwzx $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (load XForm:$src))]>;
+ [(set i32:$rD, (load XForm:$src))]>, ZExt32To64;
def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src),
"lhbrx $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (PPClbrx ForceXForm:$src, i16))]>;
+ [(set i32:$rD, (PPClbrx ForceXForm:$src, i16))]>, ZExt32To64;
def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src),
"lwbrx $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (PPClbrx ForceXForm:$src, i32))]>;
+ [(set i32:$rD, (PPClbrx ForceXForm:$src, i32))]>, ZExt32To64;
let Predicates = [HasFPU] in {
def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src),
@@ -2155,10 +2159,10 @@ def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
"li $rD, $imm", IIC_IntSimple,
- [(set i32:$rD, imm32SExt16:$imm)]>;
+ [(set i32:$rD, imm32SExt16:$imm)]>, SExt32To64;
def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
"lis $rD, $imm", IIC_IntSimple,
- [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
+ [(set i32:$rD, imm16ShiftedSExt:$imm)]>, SExt32To64;
}
}
@@ -2170,11 +2174,11 @@ let Defs = [CR0] in {
def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
"andi. $dst, $src1, $src2", IIC_IntGeneral,
[(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
- isRecordForm;
+ isRecordForm, ZExt32To64, SExt32To64;
def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
"andis. $dst, $src1, $src2", IIC_IntGeneral,
[(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
- isRecordForm;
+ isRecordForm, ZExt32To64;
}
def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
"ori $dst, $src1, $src2", IIC_IntSimple,
@@ -2244,13 +2248,13 @@ defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
} // isCommutable
defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
"slw", "$rA, $rS, $rB", IIC_IntGeneral,
- [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
+ [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>, ZExt32To64;
defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
"srw", "$rA, $rS, $rB", IIC_IntGeneral,
- [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
+ [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>, ZExt32To64;
defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
"sraw", "$rA, $rS, $rB", IIC_IntShift,
- [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
+ [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>, SExt32To64;
}
def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>;
@@ -2265,19 +2269,21 @@ let PPC970_Unit = 1 in { // FXU Operations.
let hasSideEffects = 0 in {
defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
"srawi", "$rA, $rS, $SH", IIC_IntShift,
- [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
+ [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>,
+ SExt32To64;
defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
"cntlzw", "$rA, $rS", IIC_IntGeneral,
- [(set i32:$rA, (ctlz i32:$rS))]>;
+ [(set i32:$rA, (ctlz i32:$rS))]>, ZExt32To64;
defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS),
"cnttzw", "$rA, $rS", IIC_IntGeneral,
- [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>;
+ [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>,
+ ZExt32To64;
defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
"extsb", "$rA, $rS", IIC_IntSimple,
- [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
+ [(set i32:$rA, (sext_inreg i32:$rS, i8))]>, SExt32To64;
defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
"extsh", "$rA, $rS", IIC_IntSimple,
- [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
+ [(set i32:$rA, (sext_inreg i32:$rS, i16))]>, SExt32To64;
let isCommutable = 1 in
def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
@@ -4520,9 +4526,11 @@ def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm",
(ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
- (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>,
+ ZExt32To64;
def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
- (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>,
+ ZExt32To64;
def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
@@ -4536,17 +4544,17 @@ def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
- (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
- (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
- (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n",
- (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
- (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n",
- (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
@@ -4872,7 +4880,7 @@ def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>;
def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;
def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA),
- "setb $RT, $BFA", IIC_IntGeneral>;
+ "setb $RT, $BFA", IIC_IntGeneral>, SExt32To64;
} // IsISA3_0
let Predicates = [IsISA3_0] in {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index c127f5487552..a40b59423e8d 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -1319,23 +1319,31 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [P
let Predicates = [IsISA3_1] in {
def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RT), (ins crbitrc:$BI),
- "setbc $RT, $BI", IIC_IntCompare, []>;
+ "setbc $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64, ZExt32To64;
def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RT), (ins crbitrc:$BI),
- "setbcr $RT, $BI", IIC_IntCompare, []>;
+ "setbcr $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64, ZExt32To64;
def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RT), (ins crbitrc:$BI),
- "setnbc $RT, $BI", IIC_IntCompare, []>;
+ "setnbc $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64;
def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RT), (ins crbitrc:$BI),
- "setnbcr $RT, $BI", IIC_IntCompare, []>;
+ "setnbcr $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RT), (ins crbitrc:$BI),
- "setbc $RT, $BI", IIC_IntCompare, []>;
+ "setbc $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64, ZExt32To64;
def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RT), (ins crbitrc:$BI),
- "setbcr $RT, $BI", IIC_IntCompare, []>;
+ "setbcr $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64, ZExt32To64;
def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RT), (ins crbitrc:$BI),
- "setnbc $RT, $BI", IIC_IntCompare, []>;
+ "setnbc $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64;
def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RT), (ins crbitrc:$BI),
- "setnbcr $RT, $BI", IIC_IntCompare, []>;
+ "setnbcr $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64;
}
def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
@@ -1457,19 +1465,23 @@ let Predicates = [IsISA3_1] in {
def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$rD), (ins vrrc:$vB),
"vextractbm $rD, $vB", IIC_VecGeneral,
[(set i32:$rD,
- (int_ppc_altivec_vextractbm v16i8:$vB))]>;
+ (int_ppc_altivec_vextractbm v16i8:$vB))]>,
+ ZExt32To64;
def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$rD), (ins vrrc:$vB),
"vextracthm $rD, $vB", IIC_VecGeneral,
[(set i32:$rD,
- (int_ppc_altivec_vextracthm v8i16:$vB))]>;
+ (int_ppc_altivec_vextracthm v8i16:$vB))]>,
+ ZExt32To64;
def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB),
"vextractwm $rD, $vB", IIC_VecGeneral,
[(set i32:$rD,
- (int_ppc_altivec_vextractwm v4i32:$vB))]>;
+ (int_ppc_altivec_vextractwm v4i32:$vB))]>,
+ ZExt32To64;
def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB),
"vextractdm $rD, $vB", IIC_VecGeneral,
[(set i32:$rD,
- (int_ppc_altivec_vextractdm v2i64:$vB))]>;
+ (int_ppc_altivec_vextractdm v2i64:$vB))]>,
+ ZExt32To64;
def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB),
"vextractqm $rD, $vB", IIC_VecGeneral,
[(set i32:$rD,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 6e562498dcf9..605157576a51 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -1300,7 +1300,7 @@ let Predicates = [HasVSX, HasP8Vector] in {
Requires<[In64BitMode]>;
def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
"mfvsrwz $rA, $XT", IIC_VecGeneral,
- [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
+ [(set i32:$rA, (PPCmfvsr f64:$XT))]>, ZExt32To64;
// FIXME: Setting the hasSideEffects flag here to match current behaviour.
let isCodeGenOnly = 1, hasSideEffects = 1 in
def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT),
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index c9d064548763..6788bd852e16 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -73,12 +73,12 @@ ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true),
static cl::opt<bool>
EnableSExtElimination("ppc-eliminate-signext",
cl::desc("enable elimination of sign-extensions"),
- cl::init(false), cl::Hidden);
+ cl::init(true), cl::Hidden);
static cl::opt<bool>
EnableZExtElimination("ppc-eliminate-zeroext",
cl::desc("enable elimination of zero-extensions"),
- cl::init(false), cl::Hidden);
+ cl::init(true), cl::Hidden);
static cl::opt<bool>
EnableTrapOptimization("ppc-opt-conditional-trap",
@@ -172,8 +172,10 @@ static MachineInstr *getVRegDefOrNull(MachineOperand *Op,
// This function returns number of known zero bits in output of MI
// starting from the most significant bit.
-static unsigned
-getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) {
+static unsigned getKnownLeadingZeroCount(const unsigned Reg,
+ const PPCInstrInfo *TII,
+ const MachineRegisterInfo *MRI) {
+ MachineInstr *MI = MRI->getVRegDef(Reg);
unsigned Opcode = MI->getOpcode();
if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec)
@@ -217,7 +219,7 @@ getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) {
Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
return 56;
- if (TII->isZeroExtended(*MI))
+ if (TII->isZeroExtended(Reg, MRI))
return 32;
return 0;
@@ -782,8 +784,8 @@ bool PPCMIPeephole::simplifyCode() {
SrcMI->getOpcode() == PPC::LHZX) {
if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
break;
- auto is64Bit = [] (unsigned Opcode) {
- return Opcode == PPC::EXTSH8;
+ auto is64Bit = [](unsigned Opcode) {
+ return Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSH8_32_64;
};
auto isXForm = [] (unsigned Opcode) {
return Opcode == PPC::LHZX;
@@ -798,6 +800,7 @@ bool PPCMIPeephole::simplifyCode() {
};
unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
isXForm(SrcMI->getOpcode()));
+
LLVM_DEBUG(dbgs() << "Zero-extending load\n");
LLVM_DEBUG(SrcMI->dump());
LLVM_DEBUG(dbgs() << "and sign-extension\n");
@@ -840,8 +843,29 @@ bool PPCMIPeephole::simplifyCode() {
if (isXForm) return PPC::LWAX_32;
else return PPC::LWA_32;
};
+
+ // The transformation from a zero-extending load to a sign-extending
+ // load is only legal when the displacement is a multiple of 4.
+ // If the displacement is not at least 4 byte aligned, don't perform
+ // the transformation.
+ bool IsWordAligned = false;
+ if (SrcMI->getOperand(1).isGlobal()) {
+ const GlobalObject *GO =
+ dyn_cast<GlobalObject>(SrcMI->getOperand(1).getGlobal());
+ if (GO && GO->getAlignment() >= 4)
+ IsWordAligned = true;
+ } else if (SrcMI->getOperand(1).isImm()) {
+ int64_t Value = SrcMI->getOperand(1).getImm();
+ if (Value % 4 == 0)
+ IsWordAligned = true;
+ }
+
unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
isXForm(SrcMI->getOpcode()));
+
+ if (!IsWordAligned && (Opc == PPC::LWA || Opc == PPC::LWA_32))
+ break;
+
LLVM_DEBUG(dbgs() << "Zero-extending load\n");
LLVM_DEBUG(SrcMI->dump());
LLVM_DEBUG(dbgs() << "and sign-extension\n");
@@ -853,7 +877,7 @@ bool PPCMIPeephole::simplifyCode() {
Simplified = true;
NumEliminatedSExt++;
} else if (MI.getOpcode() == PPC::EXTSW_32_64 &&
- TII->isSignExtended(*SrcMI)) {
+ TII->isSignExtended(NarrowReg, MRI)) {
// We can eliminate EXTSW if the input is known to be already
// sign-extended.
LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
@@ -904,8 +928,11 @@ bool PPCMIPeephole::simplifyCode() {
if (Register::isVirtualRegister(CopyReg))
SrcMI = MRI->getVRegDef(CopyReg);
}
+ if (!SrcMI->getOperand(0).isReg())
+ break;
- unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII);
+ unsigned KnownZeroCount =
+ getKnownLeadingZeroCount(SrcMI->getOperand(0).getReg(), TII, MRI);
if (MI.getOperand(3).getImm() <= KnownZeroCount) {
LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n");
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
index 6dea9ba934ec..c1bf81f5610e 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
@@ -1441,7 +1441,7 @@ entry:
; ASM32PWR4-DAG: lwz [[REG10:[0-9]+]], 92(1)
; ASM64PWR4-DAG: ld [[REG1:[0-9]+]], 112(1)
-; ASM64PWR4-DAG: lwz [[REG2:[0-9]+]], 124(1)
+; ASM64PWR4-DAG: lwa [[REG2:[0-9]+]], 124(1)
; ASM64PWR4-DAG: lwz [[REG3:[0-9]+]], 132(1)
; ASM64PWR4-DAG: lwz [[REG4:[0-9]+]], 140(1)
; ASM64PWR4-DAG: lwa [[REG5:[0-9]+]], 148(1)
diff --git a/llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
index e2f9451632b4..d48c80d08307 100644
--- a/llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
@@ -23,7 +23,6 @@ define dso_local signext i16 @ld_0_int16_t_uint8_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
@@ -37,7 +36,6 @@ define dso_local signext i16 @ld_align16_int16_t_uint8_t(i8* nocapture readonly
; CHECK-LABEL: ld_align16_int16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -59,7 +57,6 @@ define dso_local signext i16 @ld_align32_int16_t_uint8_t(i8* nocapture readonly
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -75,7 +72,6 @@ define dso_local signext i16 @ld_align64_int16_t_uint8_t(i8* nocapture readonly
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int16_t_uint8_t:
@@ -84,7 +80,6 @@ define dso_local signext i16 @ld_align64_int16_t_uint8_t(i8* nocapture readonly
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -98,7 +93,6 @@ define dso_local signext i16 @ld_reg_int16_t_uint8_t(i8* nocapture readonly %ptr
; CHECK-LABEL: ld_reg_int16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -113,7 +107,6 @@ define dso_local signext i16 @ld_or_int16_t_uint8_t(i64 %ptr, i8 zeroext %off) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -130,7 +123,6 @@ define dso_local signext i16 @ld_not_disjoint16_int16_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -146,7 +138,6 @@ define dso_local signext i16 @ld_disjoint_align16_int16_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -164,7 +155,6 @@ define dso_local signext i16 @ld_not_disjoint32_int16_t_uint8_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -191,7 +181,6 @@ define dso_local signext i16 @ld_disjoint_align32_int16_t_uint8_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int16_t_uint8_t:
@@ -201,7 +190,6 @@ define dso_local signext i16 @ld_disjoint_align32_int16_t_uint8_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -221,7 +209,6 @@ define dso_local signext i16 @ld_not_disjoint64_int16_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int16_t_uint8_t:
@@ -232,7 +219,6 @@ define dso_local signext i16 @ld_not_disjoint64_int16_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -250,7 +236,6 @@ define dso_local signext i16 @ld_disjoint_align64_int16_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int16_t_uint8_t:
@@ -260,7 +245,6 @@ define dso_local signext i16 @ld_disjoint_align64_int16_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -276,7 +260,6 @@ define dso_local signext i16 @ld_cst_align16_int16_t_uint8_t() {
; CHECK-LABEL: ld_cst_align16_int16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -290,7 +273,6 @@ define dso_local signext i16 @ld_cst_align32_int16_t_uint8_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -305,7 +287,6 @@ define dso_local signext i16 @ld_cst_align64_int16_t_uint8_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int16_t_uint8_t:
@@ -314,7 +295,6 @@ define dso_local signext i16 @ld_cst_align64_int16_t_uint8_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
@@ -1540,7 +1520,6 @@ define dso_local zeroext i16 @ld_0_uint16_t_uint8_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
@@ -1554,7 +1533,6 @@ define dso_local zeroext i16 @ld_align16_uint16_t_uint8_t(i8* nocapture readonly
; CHECK-LABEL: ld_align16_uint16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -1576,7 +1554,6 @@ define dso_local zeroext i16 @ld_align32_uint16_t_uint8_t(i8* nocapture readonly
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -1592,7 +1569,6 @@ define dso_local zeroext i16 @ld_align64_uint16_t_uint8_t(i8* nocapture readonly
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint16_t_uint8_t:
@@ -1601,7 +1577,6 @@ define dso_local zeroext i16 @ld_align64_uint16_t_uint8_t(i8* nocapture readonly
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -1615,7 +1590,6 @@ define dso_local zeroext i16 @ld_reg_uint16_t_uint8_t(i8* nocapture readonly %pt
; CHECK-LABEL: ld_reg_uint16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -1630,7 +1604,6 @@ define dso_local zeroext i16 @ld_or_uint16_t_uint8_t(i64 %ptr, i8 zeroext %off)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -1647,7 +1620,6 @@ define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -1663,7 +1635,6 @@ define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -1681,7 +1652,6 @@ define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_uint8_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -1708,7 +1678,6 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_uint8_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint8_t:
@@ -1718,7 +1687,6 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_uint8_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -1738,7 +1706,6 @@ define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_uint8_t:
@@ -1749,7 +1716,6 @@ define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -1767,7 +1733,6 @@ define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_uint8_t:
@@ -1777,7 +1742,6 @@ define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -1793,7 +1757,6 @@ define dso_local zeroext i16 @ld_cst_align16_uint16_t_uint8_t() {
; CHECK-LABEL: ld_cst_align16_uint16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -1807,7 +1770,6 @@ define dso_local zeroext i16 @ld_cst_align32_uint16_t_uint8_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -1822,7 +1784,6 @@ define dso_local zeroext i16 @ld_cst_align64_uint16_t_uint8_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_uint8_t:
@@ -1831,7 +1792,6 @@ define dso_local zeroext i16 @ld_cst_align64_uint16_t_uint8_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
@@ -2170,7 +2130,6 @@ define dso_local zeroext i16 @ld_0_uint16_t_uint16_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint16_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i16*
@@ -2183,7 +2142,6 @@ define dso_local zeroext i16 @ld_align16_uint16_t_uint16_t(i8* nocapture readonl
; CHECK-LABEL: ld_align16_uint16_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -2205,7 +2163,6 @@ define dso_local zeroext i16 @ld_align32_uint16_t_uint16_t(i8* nocapture readonl
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -2221,7 +2178,6 @@ define dso_local zeroext i16 @ld_align64_uint16_t_uint16_t(i8* nocapture readonl
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint16_t_uint16_t:
@@ -2230,7 +2186,6 @@ define dso_local zeroext i16 @ld_align64_uint16_t_uint16_t(i8* nocapture readonl
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -2244,7 +2199,6 @@ define dso_local zeroext i16 @ld_reg_uint16_t_uint16_t(i8* nocapture readonly %p
; CHECK-LABEL: ld_reg_uint16_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -2259,7 +2213,6 @@ define dso_local zeroext i16 @ld_or_uint16_t_uint16_t(i64 %ptr, i8 zeroext %off)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -2275,7 +2228,6 @@ define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_uint16_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -2290,7 +2242,6 @@ define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_uint16_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lhz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -2307,7 +2258,6 @@ define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_uint16_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -2333,7 +2283,6 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_uint16_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint16_t:
@@ -2343,7 +2292,6 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_uint16_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -2362,7 +2310,6 @@ define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_uint16_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_uint16_t:
@@ -2373,7 +2320,6 @@ define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_uint16_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -2390,7 +2336,6 @@ define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_uint16_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_uint16_t:
@@ -2400,7 +2345,6 @@ define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_uint16_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -2415,7 +2359,6 @@ define dso_local zeroext i16 @ld_cst_align16_uint16_t_uint16_t() {
; CHECK-LABEL: ld_cst_align16_uint16_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
@@ -2428,7 +2371,6 @@ define dso_local zeroext i16 @ld_cst_align32_uint16_t_uint16_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lhz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
@@ -2442,7 +2384,6 @@ define dso_local zeroext i16 @ld_cst_align64_uint16_t_uint16_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_uint16_t:
@@ -2451,7 +2392,6 @@ define dso_local zeroext i16 @ld_cst_align64_uint16_t_uint16_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
diff --git a/llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
index 2774dc389568..9a78f91dee89 100644
--- a/llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
@@ -23,7 +23,6 @@ define dso_local signext i32 @ld_0_int32_t_uint8_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
@@ -37,7 +36,6 @@ define dso_local signext i32 @ld_align16_int32_t_uint8_t(i8* nocapture readonly
; CHECK-LABEL: ld_align16_int32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -59,7 +57,6 @@ define dso_local signext i32 @ld_align32_int32_t_uint8_t(i8* nocapture readonly
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -75,7 +72,6 @@ define dso_local signext i32 @ld_align64_int32_t_uint8_t(i8* nocapture readonly
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int32_t_uint8_t:
@@ -84,7 +80,6 @@ define dso_local signext i32 @ld_align64_int32_t_uint8_t(i8* nocapture readonly
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -98,7 +93,6 @@ define dso_local signext i32 @ld_reg_int32_t_uint8_t(i8* nocapture readonly %ptr
; CHECK-LABEL: ld_reg_int32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -113,7 +107,6 @@ define dso_local signext i32 @ld_or_int32_t_uint8_t(i64 %ptr, i8 zeroext %off) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -130,7 +123,6 @@ define dso_local signext i32 @ld_not_disjoint16_int32_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -146,7 +138,6 @@ define dso_local signext i32 @ld_disjoint_align16_int32_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -164,7 +155,6 @@ define dso_local signext i32 @ld_not_disjoint32_int32_t_uint8_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -191,7 +181,6 @@ define dso_local signext i32 @ld_disjoint_align32_int32_t_uint8_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint8_t:
@@ -201,7 +190,6 @@ define dso_local signext i32 @ld_disjoint_align32_int32_t_uint8_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -221,7 +209,6 @@ define dso_local signext i32 @ld_not_disjoint64_int32_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint8_t:
@@ -232,7 +219,6 @@ define dso_local signext i32 @ld_not_disjoint64_int32_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -250,7 +236,6 @@ define dso_local signext i32 @ld_disjoint_align64_int32_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint8_t:
@@ -260,7 +245,6 @@ define dso_local signext i32 @ld_disjoint_align64_int32_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -276,7 +260,6 @@ define dso_local signext i32 @ld_cst_align16_int32_t_uint8_t() {
; CHECK-LABEL: ld_cst_align16_int32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -290,7 +273,6 @@ define dso_local signext i32 @ld_cst_align32_int32_t_uint8_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -305,7 +287,6 @@ define dso_local signext i32 @ld_cst_align64_int32_t_uint8_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint8_t:
@@ -314,7 +295,6 @@ define dso_local signext i32 @ld_cst_align64_int32_t_uint8_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
@@ -631,7 +611,6 @@ define dso_local signext i32 @ld_0_int32_t_uint16_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i16*
@@ -645,7 +624,6 @@ define dso_local signext i32 @ld_align16_int32_t_uint16_t(i8* nocapture readonly
; CHECK-LABEL: ld_align16_int32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -668,7 +646,6 @@ define dso_local signext i32 @ld_align32_int32_t_uint16_t(i8* nocapture readonly
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -685,7 +662,6 @@ define dso_local signext i32 @ld_align64_int32_t_uint16_t(i8* nocapture readonly
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int32_t_uint16_t:
@@ -694,7 +670,6 @@ define dso_local signext i32 @ld_align64_int32_t_uint16_t(i8* nocapture readonly
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -709,7 +684,6 @@ define dso_local signext i32 @ld_reg_int32_t_uint16_t(i8* nocapture readonly %pt
; CHECK-LABEL: ld_reg_int32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -725,7 +699,6 @@ define dso_local signext i32 @ld_or_int32_t_uint16_t(i64 %ptr, i8 zeroext %off)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -742,7 +715,6 @@ define dso_local signext i32 @ld_not_disjoint16_int32_t_uint16_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -758,7 +730,6 @@ define dso_local signext i32 @ld_disjoint_align16_int32_t_uint16_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lhz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -776,7 +747,6 @@ define dso_local signext i32 @ld_not_disjoint32_int32_t_uint16_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -803,7 +773,6 @@ define dso_local signext i32 @ld_disjoint_align32_int32_t_uint16_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint16_t:
@@ -813,7 +782,6 @@ define dso_local signext i32 @ld_disjoint_align32_int32_t_uint16_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -833,7 +801,6 @@ define dso_local signext i32 @ld_not_disjoint64_int32_t_uint16_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint16_t:
@@ -844,7 +811,6 @@ define dso_local signext i32 @ld_not_disjoint64_int32_t_uint16_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -862,7 +828,6 @@ define dso_local signext i32 @ld_disjoint_align64_int32_t_uint16_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint16_t:
@@ -872,7 +837,6 @@ define dso_local signext i32 @ld_disjoint_align64_int32_t_uint16_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -888,7 +852,6 @@ define dso_local signext i32 @ld_cst_align16_int32_t_uint16_t() {
; CHECK-LABEL: ld_cst_align16_int32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
@@ -902,7 +865,6 @@ define dso_local signext i32 @ld_cst_align32_int32_t_uint16_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lhz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
@@ -917,7 +879,6 @@ define dso_local signext i32 @ld_cst_align64_int32_t_uint16_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint16_t:
@@ -926,7 +887,6 @@ define dso_local signext i32 @ld_cst_align64_int32_t_uint16_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
@@ -1246,8 +1206,7 @@ entry:
define dso_local signext i32 @ld_0_int32_t_uint32_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i32*
@@ -1259,8 +1218,7 @@ entry:
define dso_local signext i32 @ld_align16_int32_t_uint32_t(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 8(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 8(r3)
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -1281,8 +1239,7 @@ define dso_local signext i32 @ld_align32_int32_t_uint32_t(i8* nocapture readonly
; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -1297,8 +1254,7 @@ define dso_local signext i32 @ld_align64_int32_t_uint32_t(i8* nocapture readonly
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwax r3, r3, r4
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int32_t_uint32_t:
@@ -1306,8 +1262,7 @@ define dso_local signext i32 @ld_align64_int32_t_uint32_t(i8* nocapture readonly
; CHECK-PREP10-NEXT: lis r4, 3725
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -1320,8 +1275,7 @@ entry:
define dso_local signext i32 @ld_reg_int32_t_uint32_t(i8* nocapture readonly %ptr, i64 %off) {
; CHECK-LABEL: ld_reg_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwzx r3, r3, r4
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwax r3, r3, r4
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -1335,8 +1289,7 @@ define dso_local signext i32 @ld_or_int32_t_uint32_t(i64 %ptr, i8 zeroext %off)
; CHECK-LABEL: ld_or_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -1351,8 +1304,7 @@ define dso_local signext i32 @ld_not_disjoint16_int32_t_uint32_t(i64 %ptr) {
; CHECK-LABEL: ld_not_disjoint16_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -1366,8 +1318,7 @@ define dso_local signext i32 @ld_disjoint_align16_int32_t_uint32_t(i64 %ptr) {
; CHECK-LABEL: ld_disjoint_align16_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
-; CHECK-NEXT: lwz r3, 24(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 24(r3)
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -1383,8 +1334,7 @@ define dso_local signext i32 @ld_not_disjoint32_int32_t_uint32_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -1409,8 +1359,7 @@ define dso_local signext i32 @ld_disjoint_align32_int32_t_uint32_t(i64 %ptr) {
; CHECK-P9-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
-; CHECK-P9-NEXT: lwzx r3, r3, r4
-; CHECK-P9-NEXT: extsw r3, r3
+; CHECK-P9-NEXT: lwax r3, r3, r4
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint32_t:
@@ -1419,8 +1368,7 @@ define dso_local signext i32 @ld_disjoint_align32_int32_t_uint32_t(i64 %ptr) {
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
-; CHECK-P8-NEXT: lwzx r3, r3, r4
-; CHECK-P8-NEXT: extsw r3, r3
+; CHECK-P8-NEXT: lwax r3, r3, r4
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -1438,8 +1386,7 @@ define dso_local signext i32 @ld_not_disjoint64_int32_t_uint32_t(i64 %ptr) {
; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
-; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwa r3, 0(r3)
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint32_t:
@@ -1449,8 +1396,7 @@ define dso_local signext i32 @ld_not_disjoint64_int32_t_uint32_t(i64 %ptr) {
; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
-; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwa r3, 0(r3)
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -1466,8 +1412,7 @@ define dso_local signext i32 @ld_disjoint_align64_int32_t_uint32_t(i64 %ptr) {
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwax r3, r3, r4
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint32_t:
@@ -1476,8 +1421,7 @@ define dso_local signext i32 @ld_disjoint_align64_int32_t_uint32_t(i64 %ptr) {
; CHECK-PREP10-NEXT: rldicr r3, r3, 0, 23
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -1491,8 +1435,7 @@ entry:
define dso_local signext i32 @ld_cst_align16_int32_t_uint32_t() {
; CHECK-LABEL: ld_cst_align16_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 4080(0)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 4080(0)
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
@@ -1504,8 +1447,7 @@ define dso_local signext i32 @ld_cst_align32_int32_t_uint32_t() {
; CHECK-LABEL: ld_cst_align32_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
-; CHECK-NEXT: lwz r3, -27108(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, -27108(r3)
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
@@ -1518,8 +1460,7 @@ define dso_local signext i32 @ld_cst_align64_int32_t_uint32_t() {
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
-; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwa r3, 0(r3)
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint32_t:
@@ -1527,8 +1468,7 @@ define dso_local signext i32 @ld_cst_align64_int32_t_uint32_t() {
; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwa r3, 0(r3)
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
@@ -1848,7 +1788,6 @@ define dso_local zeroext i32 @ld_0_uint32_t_uint8_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
@@ -1862,7 +1801,6 @@ define dso_local zeroext i32 @ld_align16_uint32_t_uint8_t(i8* nocapture readonly
; CHECK-LABEL: ld_align16_uint32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -1884,7 +1822,6 @@ define dso_local zeroext i32 @ld_align32_uint32_t_uint8_t(i8* nocapture readonly
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -1900,7 +1837,6 @@ define dso_local zeroext i32 @ld_align64_uint32_t_uint8_t(i8* nocapture readonly
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint8_t:
@@ -1909,7 +1845,6 @@ define dso_local zeroext i32 @ld_align64_uint32_t_uint8_t(i8* nocapture readonly
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -1923,7 +1858,6 @@ define dso_local zeroext i32 @ld_reg_uint32_t_uint8_t(i8* nocapture readonly %pt
; CHECK-LABEL: ld_reg_uint32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -1938,7 +1872,6 @@ define dso_local zeroext i32 @ld_or_uint32_t_uint8_t(i64 %ptr, i8 zeroext %off)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -1955,7 +1888,6 @@ define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -1971,7 +1903,6 @@ define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -1989,7 +1920,6 @@ define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_uint8_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -2016,7 +1946,6 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint8_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint8_t:
@@ -2026,7 +1955,6 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint8_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -2046,7 +1974,6 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint8_t:
@@ -2057,7 +1984,6 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -2075,7 +2001,6 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint8_t:
@@ -2085,7 +2010,6 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -2101,7 +2025,6 @@ define dso_local zeroext i32 @ld_cst_align16_uint32_t_uint8_t() {
; CHECK-LABEL: ld_cst_align16_uint32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -2115,7 +2038,6 @@ define dso_local zeroext i32 @ld_cst_align32_uint32_t_uint8_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -2130,7 +2052,6 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint8_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint8_t:
@@ -2139,7 +2060,6 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint8_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
@@ -2478,7 +2398,6 @@ define dso_local zeroext i32 @ld_0_uint32_t_uint16_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i16*
@@ -2492,7 +2411,6 @@ define dso_local zeroext i32 @ld_align16_uint32_t_uint16_t(i8* nocapture readonl
; CHECK-LABEL: ld_align16_uint32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -2515,7 +2433,6 @@ define dso_local zeroext i32 @ld_align32_uint32_t_uint16_t(i8* nocapture readonl
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -2532,7 +2449,6 @@ define dso_local zeroext i32 @ld_align64_uint32_t_uint16_t(i8* nocapture readonl
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint16_t:
@@ -2541,7 +2457,6 @@ define dso_local zeroext i32 @ld_align64_uint32_t_uint16_t(i8* nocapture readonl
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -2556,7 +2471,6 @@ define dso_local zeroext i32 @ld_reg_uint32_t_uint16_t(i8* nocapture readonly %p
; CHECK-LABEL: ld_reg_uint32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -2572,7 +2486,6 @@ define dso_local zeroext i32 @ld_or_uint32_t_uint16_t(i64 %ptr, i8 zeroext %off)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -2589,7 +2502,6 @@ define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_uint16_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -2605,7 +2517,6 @@ define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_uint16_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lhz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -2623,7 +2534,6 @@ define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_uint16_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -2650,7 +2560,6 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint16_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint16_t:
@@ -2660,7 +2569,6 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint16_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -2680,7 +2588,6 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint16_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint16_t:
@@ -2691,7 +2598,6 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint16_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -2709,7 +2615,6 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint16_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint16_t:
@@ -2719,7 +2624,6 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint16_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -2735,7 +2639,6 @@ define dso_local zeroext i32 @ld_cst_align16_uint32_t_uint16_t() {
; CHECK-LABEL: ld_cst_align16_uint32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
@@ -2749,7 +2652,6 @@ define dso_local zeroext i32 @ld_cst_align32_uint32_t_uint16_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lhz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
@@ -2764,7 +2666,6 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint16_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint16_t:
@@ -2773,7 +2674,6 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint16_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
@@ -2785,8 +2685,7 @@ entry:
define dso_local zeroext i32 @ld_0_uint32_t_int16_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 0(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@@ -2800,8 +2699,7 @@ entry:
define dso_local zeroext i32 @ld_align16_uint32_t_int16_t(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lhz r3, 8(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 8(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@@ -2825,8 +2723,7 @@ define dso_local zeroext i32 @ld_align32_uint32_t_int16_t(i8* nocapture readonly
; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
-; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsh r3, r3
+; CHECK-PREP10-NEXT: lhax r3, r3, r4
; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
@@ -2843,8 +2740,7 @@ define dso_local zeroext i32 @ld_align64_uint32_t_int16_t(i8* nocapture readonly
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: extsh r3, r3
+; CHECK-P10-NEXT: lhax r3, r3, r4
; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
@@ -2853,8 +2749,7 @@ define dso_local zeroext i32 @ld_align64_uint32_t_int16_t(i8* nocapture readonly
; CHECK-PREP10-NEXT: lis r4, 3725
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsh r3, r3
+; CHECK-PREP10-NEXT: lhax r3, r3, r4
; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
@@ -2869,8 +2764,7 @@ entry:
define dso_local zeroext i32 @ld_reg_uint32_t_int16_t(i8* nocapture readonly %ptr, i64 %off) {
; CHECK-LABEL: ld_reg_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lhzx r3, r3, r4
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lhax r3, r3, r4
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@@ -2886,8 +2780,7 @@ define dso_local zeroext i32 @ld_or_uint32_t_int16_t(i64 %ptr, i8 zeroext %off)
; CHECK-LABEL: ld_or_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
-; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 0(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@@ -2904,8 +2797,7 @@ define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_int16_t(i64 %ptr) {
; CHECK-LABEL: ld_not_disjoint16_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
-; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 0(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@@ -2921,8 +2813,7 @@ define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_int16_t(i64 %ptr) {
; CHECK-LABEL: ld_disjoint_align16_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
-; CHECK-NEXT: lhz r3, 24(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 24(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@@ -2940,8 +2831,7 @@ define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_int16_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
-; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 0(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@@ -2969,8 +2859,7 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_int16_t(i64 %ptr) {
; CHECK-P9-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
-; CHECK-P9-NEXT: lhzx r3, r3, r4
-; CHECK-P9-NEXT: extsh r3, r3
+; CHECK-P9-NEXT: lhax r3, r3, r4
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
@@ -2980,8 +2869,7 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_int16_t(i64 %ptr) {
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
-; CHECK-P8-NEXT: lhzx r3, r3, r4
-; CHECK-P8-NEXT: extsh r3, r3
+; CHECK-P8-NEXT: lhax r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
@@ -3001,8 +2889,7 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_int16_t(i64 %ptr) {
; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
-; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: extsh r3, r3
+; CHECK-P10-NEXT: lha r3, 0(r3)
; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
@@ -3013,8 +2900,7 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_int16_t(i64 %ptr) {
; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
-; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsh r3, r3
+; CHECK-PREP10-NEXT: lha r3, 0(r3)
; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
@@ -3032,8 +2918,7 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_int16_t(i64 %ptr) {
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: extsh r3, r3
+; CHECK-P10-NEXT: lhax r3, r3, r4
; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
@@ -3043,8 +2928,7 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_int16_t(i64 %ptr) {
; CHECK-PREP10-NEXT: rldicr r3, r3, 0, 23
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsh r3, r3
+; CHECK-PREP10-NEXT: lhax r3, r3, r4
; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
@@ -3060,8 +2944,7 @@ entry:
define dso_local zeroext i32 @ld_cst_align16_uint32_t_int16_t() {
; CHECK-LABEL: ld_cst_align16_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lhz r3, 4080(0)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 4080(0)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@@ -3075,8 +2958,7 @@ define dso_local zeroext i32 @ld_cst_align32_uint32_t_int16_t() {
; CHECK-LABEL: ld_cst_align32_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
-; CHECK-NEXT: lhz r3, -27108(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, -27108(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@@ -3091,8 +2973,7 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_int16_t() {
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
-; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: extsh r3, r3
+; CHECK-P10-NEXT: lha r3, 0(r3)
; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
@@ -3101,8 +2982,7 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_int16_t() {
; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsh r3, r3
+; CHECK-PREP10-NEXT: lha r3, 0(r3)
; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
@@ -3116,7 +2996,6 @@ define dso_local zeroext i32 @ld_0_uint32_t_uint32_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i32*
@@ -3129,7 +3008,6 @@ define dso_local zeroext i32 @ld_align16_uint32_t_uint32_t(i8* nocapture readonl
; CHECK-LABEL: ld_align16_uint32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -3151,7 +3029,6 @@ define dso_local zeroext i32 @ld_align32_uint32_t_uint32_t(i8* nocapture readonl
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -3167,7 +3044,6 @@ define dso_local zeroext i32 @ld_align64_uint32_t_uint32_t(i8* nocapture readonl
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint32_t:
@@ -3176,7 +3052,6 @@ define dso_local zeroext i32 @ld_align64_uint32_t_uint32_t(i8* nocapture readonl
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -3190,7 +3065,6 @@ define dso_local zeroext i32 @ld_reg_uint32_t_uint32_t(i8* nocapture readonly %p
; CHECK-LABEL: ld_reg_uint32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -3205,7 +3079,6 @@ define dso_local zeroext i32 @ld_or_uint32_t_uint32_t(i64 %ptr, i8 zeroext %off)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -3221,7 +3094,6 @@ define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_uint32_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -3236,7 +3108,6 @@ define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_uint32_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lwz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -3253,7 +3124,6 @@ define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_uint32_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -3279,7 +3149,6 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint32_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lwzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint32_t:
@@ -3289,7 +3158,6 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint32_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lwzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -3308,7 +3176,6 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint32_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint32_t:
@@ -3319,7 +3186,6 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint32_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -3336,7 +3202,6 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint32_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint32_t:
@@ -3346,7 +3211,6 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint32_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -3361,7 +3225,6 @@ define dso_local zeroext i32 @ld_cst_align16_uint32_t_uint32_t() {
; CHECK-LABEL: ld_cst_align16_uint32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
@@ -3374,7 +3237,6 @@ define dso_local zeroext i32 @ld_cst_align32_uint32_t_uint32_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lwz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
@@ -3388,7 +3250,6 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint32_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint32_t:
@@ -3397,7 +3258,6 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint32_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
diff --git a/llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
index 55ba3c057740..57ca3213bd0a 100644
--- a/llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
@@ -23,7 +23,6 @@ define dso_local i64 @ld_0_int64_t_uint8_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
@@ -37,7 +36,6 @@ define dso_local i64 @ld_align16_int64_t_uint8_t(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_int64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -59,7 +57,6 @@ define dso_local i64 @ld_align32_int64_t_uint8_t(i8* nocapture readonly %ptr) {
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -75,7 +72,6 @@ define dso_local i64 @ld_align64_int64_t_uint8_t(i8* nocapture readonly %ptr) {
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int64_t_uint8_t:
@@ -84,7 +80,6 @@ define dso_local i64 @ld_align64_int64_t_uint8_t(i8* nocapture readonly %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -98,7 +93,6 @@ define dso_local i64 @ld_reg_int64_t_uint8_t(i8* nocapture readonly %ptr, i64 %o
; CHECK-LABEL: ld_reg_int64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -113,7 +107,6 @@ define dso_local i64 @ld_or_int64_t_uint8_t(i64 %ptr, i8 zeroext %off) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -130,7 +123,6 @@ define dso_local i64 @ld_not_disjoint16_int64_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -146,7 +138,6 @@ define dso_local i64 @ld_disjoint_align16_int64_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -164,7 +155,6 @@ define dso_local i64 @ld_not_disjoint32_int64_t_uint8_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -191,7 +181,6 @@ define dso_local i64 @ld_disjoint_align32_int64_t_uint8_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint8_t:
@@ -201,7 +190,6 @@ define dso_local i64 @ld_disjoint_align32_int64_t_uint8_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -221,7 +209,6 @@ define dso_local i64 @ld_not_disjoint64_int64_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint8_t:
@@ -232,7 +219,6 @@ define dso_local i64 @ld_not_disjoint64_int64_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -250,7 +236,6 @@ define dso_local i64 @ld_disjoint_align64_int64_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint8_t:
@@ -260,7 +245,6 @@ define dso_local i64 @ld_disjoint_align64_int64_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -276,7 +260,6 @@ define dso_local i64 @ld_cst_align16_int64_t_uint8_t() {
; CHECK-LABEL: ld_cst_align16_int64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -290,7 +273,6 @@ define dso_local i64 @ld_cst_align32_int64_t_uint8_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -305,7 +287,6 @@ define dso_local i64 @ld_cst_align64_int64_t_uint8_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint8_t:
@@ -314,7 +295,6 @@ define dso_local i64 @ld_cst_align64_int64_t_uint8_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
@@ -631,7 +611,6 @@ define dso_local i64 @ld_0_int64_t_uint16_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i16*
@@ -645,7 +624,6 @@ define dso_local i64 @ld_align16_int64_t_uint16_t(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_int64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -668,7 +646,6 @@ define dso_local i64 @ld_align32_int64_t_uint16_t(i8* nocapture readonly %ptr) {
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -685,7 +662,6 @@ define dso_local i64 @ld_align64_int64_t_uint16_t(i8* nocapture readonly %ptr) {
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int64_t_uint16_t:
@@ -694,7 +670,6 @@ define dso_local i64 @ld_align64_int64_t_uint16_t(i8* nocapture readonly %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -709,7 +684,6 @@ define dso_local i64 @ld_reg_int64_t_uint16_t(i8* nocapture readonly %ptr, i64 %
; CHECK-LABEL: ld_reg_int64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -725,7 +699,6 @@ define dso_local i64 @ld_or_int64_t_uint16_t(i64 %ptr, i8 zeroext %off) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -742,7 +715,6 @@ define dso_local i64 @ld_not_disjoint16_int64_t_uint16_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -758,7 +730,6 @@ define dso_local i64 @ld_disjoint_align16_int64_t_uint16_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lhz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -776,7 +747,6 @@ define dso_local i64 @ld_not_disjoint32_int64_t_uint16_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -803,7 +773,6 @@ define dso_local i64 @ld_disjoint_align32_int64_t_uint16_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint16_t:
@@ -813,7 +782,6 @@ define dso_local i64 @ld_disjoint_align32_int64_t_uint16_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -833,7 +801,6 @@ define dso_local i64 @ld_not_disjoint64_int64_t_uint16_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint16_t:
@@ -844,7 +811,6 @@ define dso_local i64 @ld_not_disjoint64_int64_t_uint16_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -862,7 +828,6 @@ define dso_local i64 @ld_disjoint_align64_int64_t_uint16_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint16_t:
@@ -872,7 +837,6 @@ define dso_local i64 @ld_disjoint_align64_int64_t_uint16_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -888,7 +852,6 @@ define dso_local i64 @ld_cst_align16_int64_t_uint16_t() {
; CHECK-LABEL: ld_cst_align16_int64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
@@ -902,7 +865,6 @@ define dso_local i64 @ld_cst_align32_int64_t_uint16_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lhz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
@@ -917,7 +879,6 @@ define dso_local i64 @ld_cst_align64_int64_t_uint16_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint16_t:
@@ -926,7 +887,6 @@ define dso_local i64 @ld_cst_align64_int64_t_uint16_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
@@ -1247,7 +1207,6 @@ define dso_local i64 @ld_0_int64_t_uint32_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i32*
@@ -1261,7 +1220,6 @@ define dso_local i64 @ld_align16_int64_t_uint32_t(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_int64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -1284,7 +1242,6 @@ define dso_local i64 @ld_align32_int64_t_uint32_t(i8* nocapture readonly %ptr) {
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -1301,7 +1258,6 @@ define dso_local i64 @ld_align64_int64_t_uint32_t(i8* nocapture readonly %ptr) {
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int64_t_uint32_t:
@@ -1310,7 +1266,6 @@ define dso_local i64 @ld_align64_int64_t_uint32_t(i8* nocapture readonly %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -1325,7 +1280,6 @@ define dso_local i64 @ld_reg_int64_t_uint32_t(i8* nocapture readonly %ptr, i64 %
; CHECK-LABEL: ld_reg_int64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -1341,7 +1295,6 @@ define dso_local i64 @ld_or_int64_t_uint32_t(i64 %ptr, i8 zeroext %off) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -1358,7 +1311,6 @@ define dso_local i64 @ld_not_disjoint16_int64_t_uint32_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -1374,7 +1326,6 @@ define dso_local i64 @ld_disjoint_align16_int64_t_uint32_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lwz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -1392,7 +1343,6 @@ define dso_local i64 @ld_not_disjoint32_int64_t_uint32_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -1419,7 +1369,6 @@ define dso_local i64 @ld_disjoint_align32_int64_t_uint32_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lwzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint32_t:
@@ -1429,7 +1378,6 @@ define dso_local i64 @ld_disjoint_align32_int64_t_uint32_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lwzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -1449,7 +1397,6 @@ define dso_local i64 @ld_not_disjoint64_int64_t_uint32_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint32_t:
@@ -1460,7 +1407,6 @@ define dso_local i64 @ld_not_disjoint64_int64_t_uint32_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -1478,7 +1424,6 @@ define dso_local i64 @ld_disjoint_align64_int64_t_uint32_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint32_t:
@@ -1488,7 +1433,6 @@ define dso_local i64 @ld_disjoint_align64_int64_t_uint32_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -1504,7 +1448,6 @@ define dso_local i64 @ld_cst_align16_int64_t_uint32_t() {
; CHECK-LABEL: ld_cst_align16_int64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
@@ -1518,7 +1461,6 @@ define dso_local i64 @ld_cst_align32_int64_t_uint32_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lwz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
@@ -1533,7 +1475,6 @@ define dso_local i64 @ld_cst_align64_int64_t_uint32_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint32_t:
@@ -1542,7 +1483,6 @@ define dso_local i64 @ld_cst_align64_int64_t_uint32_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
@@ -1554,8 +1494,7 @@ entry:
define dso_local i64 @ld_0_int64_t_int32_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i32*
@@ -1568,8 +1507,7 @@ entry:
define dso_local i64 @ld_align16_int64_t_int32_t(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 8(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 8(r3)
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -1591,8 +1529,7 @@ define dso_local i64 @ld_align32_int64_t_int32_t(i8* nocapture readonly %ptr) {
; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -1608,8 +1545,7 @@ define dso_local i64 @ld_align64_int64_t_int32_t(i8* nocapture readonly %ptr) {
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwax r3, r3, r4
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int64_t_int32_t:
@@ -1617,8 +1553,7 @@ define dso_local i64 @ld_align64_int64_t_int32_t(i8* nocapture readonly %ptr) {
; CHECK-PREP10-NEXT: lis r4, 3725
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -1632,8 +1567,7 @@ entry:
define dso_local i64 @ld_reg_int64_t_int32_t(i8* nocapture readonly %ptr, i64 %off) {
; CHECK-LABEL: ld_reg_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwzx r3, r3, r4
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwax r3, r3, r4
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -1648,8 +1582,7 @@ define dso_local i64 @ld_or_int64_t_int32_t(i64 %ptr, i8 zeroext %off) {
; CHECK-LABEL: ld_or_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -1665,8 +1598,7 @@ define dso_local i64 @ld_not_disjoint16_int64_t_int32_t(i64 %ptr) {
; CHECK-LABEL: ld_not_disjoint16_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -1681,8 +1613,7 @@ define dso_local i64 @ld_disjoint_align16_int64_t_int32_t(i64 %ptr) {
; CHECK-LABEL: ld_disjoint_align16_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
-; CHECK-NEXT: lwz r3, 24(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 24(r3)
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -1699,8 +1630,7 @@ define dso_local i64 @ld_not_disjoint32_int64_t_int32_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -1726,8 +1656,7 @@ define dso_local i64 @ld_disjoint_align32_int64_t_int32_t(i64 %ptr) {
; CHECK-P9-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
-; CHECK-P9-NEXT: lwzx r3, r3, r4
-; CHECK-P9-NEXT: extsw r3, r3
+; CHECK-P9-NEXT: lwax r3, r3, r4
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_int32_t:
@@ -1736,8 +1665,7 @@ define dso_local i64 @ld_disjoint_align32_int64_t_int32_t(i64 %ptr) {
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
-; CHECK-P8-NEXT: lwzx r3, r3, r4
-; CHECK-P8-NEXT: extsw r3, r3
+; CHECK-P8-NEXT: lwax r3, r3, r4
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -1756,8 +1684,7 @@ define dso_local i64 @ld_not_disjoint64_int64_t_int32_t(i64 %ptr) {
; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
-; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwa r3, 0(r3)
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_int32_t:
@@ -1767,8 +1694,7 @@ define dso_local i64 @ld_not_disjoint64_int64_t_int32_t(i64 %ptr) {
; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
-; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwa r3, 0(r3)
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -1785,8 +1711,7 @@ define dso_local i64 @ld_disjoint_align64_int64_t_int32_t(i64 %ptr) {
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwax r3, r3, r4
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_int32_t:
@@ -1795,8 +1720,7 @@ define dso_local i64 @ld_disjoint_align64_int64_t_int32_t(i64 %ptr) {
; CHECK-PREP10-NEXT: rldicr r3, r3, 0, 23
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -1811,8 +1735,7 @@ entry:
define dso_local i64 @ld_cst_align16_int64_t_int32_t() {
; CHECK-LABEL: ld_cst_align16_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 4080(0)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 4080(0)
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
@@ -1825,8 +1748,7 @@ define dso_local i64 @ld_cst_align32_int64_t_int32_t() {
; CHECK-LABEL: ld_cst_align32_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
-; CHECK-NEXT: lwz r3, -27108(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, -27108(r3)
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
@@ -1840,8 +1762,7 @@ define dso_local i64 @ld_cst_align64_int64_t_int32_t() {
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
-; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwa r3, 0(r3)
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_int32_t:
@@ -1849,8 +1770,7 @@ define dso_local i64 @ld_cst_align64_int64_t_int32_t() {
; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwa r3, 0(r3)
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
@@ -2134,7 +2054,6 @@ define dso_local i64 @ld_0_uint64_t_uint8_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
@@ -2148,7 +2067,6 @@ define dso_local i64 @ld_align16_uint64_t_uint8_t(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_uint64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -2170,7 +2088,6 @@ define dso_local i64 @ld_align32_uint64_t_uint8_t(i8* nocapture readonly %ptr) {
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -2186,7 +2103,6 @@ define dso_local i64 @ld_align64_uint64_t_uint8_t(i8* nocapture readonly %ptr) {
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint8_t:
@@ -2195,7 +2111,6 @@ define dso_local i64 @ld_align64_uint64_t_uint8_t(i8* nocapture readonly %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -2209,7 +2124,6 @@ define dso_local i64 @ld_reg_uint64_t_uint8_t(i8* nocapture readonly %ptr, i64 %
; CHECK-LABEL: ld_reg_uint64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -2224,7 +2138,6 @@ define dso_local i64 @ld_or_uint64_t_uint8_t(i64 %ptr, i8 zeroext %off) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -2241,7 +2154,6 @@ define dso_local i64 @ld_not_disjoint16_uint64_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -2257,7 +2169,6 @@ define dso_local i64 @ld_disjoint_align16_uint64_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -2275,7 +2186,6 @@ define dso_local i64 @ld_not_disjoint32_uint64_t_uint8_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -2302,7 +2212,6 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_uint8_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint8_t:
@@ -2312,7 +2221,6 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_uint8_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -2332,7 +2240,6 @@ define dso_local i64 @ld_not_disjoint64_uint64_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint8_t:
@@ -2343,7 +2250,6 @@ define dso_local i64 @ld_not_disjoint64_uint64_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -2361,7 +2267,6 @@ define dso_local i64 @ld_disjoint_align64_uint64_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint8_t:
@@ -2371,7 +2276,6 @@ define dso_local i64 @ld_disjoint_align64_uint64_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -2387,7 +2291,6 @@ define dso_local i64 @ld_cst_align16_uint64_t_uint8_t() {
; CHECK-LABEL: ld_cst_align16_uint64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -2401,7 +2304,6 @@ define dso_local i64 @ld_cst_align32_uint64_t_uint8_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -2416,7 +2318,6 @@ define dso_local i64 @ld_cst_align64_uint64_t_uint8_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint8_t:
@@ -2425,7 +2326,6 @@ define dso_local i64 @ld_cst_align64_uint64_t_uint8_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
@@ -2742,7 +2642,6 @@ define dso_local i64 @ld_0_uint64_t_uint16_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i16*
@@ -2756,7 +2655,6 @@ define dso_local i64 @ld_align16_uint64_t_uint16_t(i8* nocapture readonly %ptr)
; CHECK-LABEL: ld_align16_uint64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -2779,7 +2677,6 @@ define dso_local i64 @ld_align32_uint64_t_uint16_t(i8* nocapture readonly %ptr)
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -2796,7 +2693,6 @@ define dso_local i64 @ld_align64_uint64_t_uint16_t(i8* nocapture readonly %ptr)
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint16_t:
@@ -2805,7 +2701,6 @@ define dso_local i64 @ld_align64_uint64_t_uint16_t(i8* nocapture readonly %ptr)
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -2820,7 +2715,6 @@ define dso_local i64 @ld_reg_uint64_t_uint16_t(i8* nocapture readonly %ptr, i64
; CHECK-LABEL: ld_reg_uint64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -2836,7 +2730,6 @@ define dso_local i64 @ld_or_uint64_t_uint16_t(i64 %ptr, i8 zeroext %off) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -2853,7 +2746,6 @@ define dso_local i64 @ld_not_disjoint16_uint64_t_uint16_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -2869,7 +2761,6 @@ define dso_local i64 @ld_disjoint_align16_uint64_t_uint16_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lhz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -2887,7 +2778,6 @@ define dso_local i64 @ld_not_disjoint32_uint64_t_uint16_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -2914,7 +2804,6 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_uint16_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint16_t:
@@ -2924,7 +2813,6 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_uint16_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -2944,7 +2832,6 @@ define dso_local i64 @ld_not_disjoint64_uint64_t_uint16_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint16_t:
@@ -2955,7 +2842,6 @@ define dso_local i64 @ld_not_disjoint64_uint64_t_uint16_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -2973,7 +2859,6 @@ define dso_local i64 @ld_disjoint_align64_uint64_t_uint16_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint16_t:
@@ -2983,7 +2868,6 @@ define dso_local i64 @ld_disjoint_align64_uint64_t_uint16_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -2999,7 +2883,6 @@ define dso_local i64 @ld_cst_align16_uint64_t_uint16_t() {
; CHECK-LABEL: ld_cst_align16_uint64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
@@ -3013,7 +2896,6 @@ define dso_local i64 @ld_cst_align32_uint64_t_uint16_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lhz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
@@ -3028,7 +2910,6 @@ define dso_local i64 @ld_cst_align64_uint64_t_uint16_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint16_t:
@@ -3037,7 +2918,6 @@ define dso_local i64 @ld_cst_align64_uint64_t_uint16_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
@@ -3358,7 +3238,6 @@ define dso_local i64 @ld_0_uint64_t_uint32_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i32*
@@ -3372,7 +3251,6 @@ define dso_local i64 @ld_align16_uint64_t_uint32_t(i8* nocapture readonly %ptr)
; CHECK-LABEL: ld_align16_uint64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -3395,7 +3273,6 @@ define dso_local i64 @ld_align32_uint64_t_uint32_t(i8* nocapture readonly %ptr)
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -3412,7 +3289,6 @@ define dso_local i64 @ld_align64_uint64_t_uint32_t(i8* nocapture readonly %ptr)
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint32_t:
@@ -3421,7 +3297,6 @@ define dso_local i64 @ld_align64_uint64_t_uint32_t(i8* nocapture readonly %ptr)
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -3436,7 +3311,6 @@ define dso_local i64 @ld_reg_uint64_t_uint32_t(i8* nocapture readonly %ptr, i64
; CHECK-LABEL: ld_reg_uint64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -3452,7 +3326,6 @@ define dso_local i64 @ld_or_uint64_t_uint32_t(i64 %ptr, i8 zeroext %off) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -3469,7 +3342,6 @@ define dso_local i64 @ld_not_disjoint16_uint64_t_uint32_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -3485,7 +3357,6 @@ define dso_local i64 @ld_disjoint_align16_uint64_t_uint32_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lwz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -3503,7 +3374,6 @@ define dso_local i64 @ld_not_disjoint32_uint64_t_uint32_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -3530,7 +3400,6 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_uint32_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lwzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint32_t:
@@ -3540,7 +3409,6 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_uint32_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lwzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -3560,7 +3428,6 @@ define dso_local i64 @ld_not_disjoint64_uint64_t_uint32_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint32_t:
@@ -3571,7 +3438,6 @@ define dso_local i64 @ld_not_disjoint64_uint64_t_uint32_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -3589,7 +3455,6 @@ define dso_local i64 @ld_disjoint_align64_uint64_t_uint32_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint32_t:
@@ -3599,7 +3464,6 @@ define dso_local i64 @ld_disjoint_align64_uint64_t_uint32_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -3615,7 +3479,6 @@ define dso_local i64 @ld_cst_align16_uint64_t_uint32_t() {
; CHECK-LABEL: ld_cst_align16_uint64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
@@ -3629,7 +3492,6 @@ define dso_local i64 @ld_cst_align32_uint64_t_uint32_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lwz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
@@ -3644,7 +3506,6 @@ define dso_local i64 @ld_cst_align64_uint64_t_uint32_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint32_t:
@@ -3653,7 +3514,6 @@ define dso_local i64 @ld_cst_align64_uint64_t_uint32_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
@@ -3665,8 +3525,7 @@ entry:
define dso_local i64 @ld_0_uint64_t_int32_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i32*
@@ -3679,8 +3538,7 @@ entry:
define dso_local i64 @ld_align16_uint64_t_int32_t(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 8(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 8(r3)
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -3702,8 +3560,7 @@ define dso_local i64 @ld_align32_uint64_t_int32_t(i8* nocapture readonly %ptr) {
; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -3719,8 +3576,7 @@ define dso_local i64 @ld_align64_uint64_t_int32_t(i8* nocapture readonly %ptr) {
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwax r3, r3, r4
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint64_t_int32_t:
@@ -3728,8 +3584,7 @@ define dso_local i64 @ld_align64_uint64_t_int32_t(i8* nocapture readonly %ptr) {
; CHECK-PREP10-NEXT: lis r4, 3725
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -3743,8 +3598,7 @@ entry:
define dso_local i64 @ld_reg_uint64_t_int32_t(i8* nocapture readonly %ptr, i64 %off) {
; CHECK-LABEL: ld_reg_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwzx r3, r3, r4
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwax r3, r3, r4
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -3759,8 +3613,7 @@ define dso_local i64 @ld_or_uint64_t_int32_t(i64 %ptr, i8 zeroext %off) {
; CHECK-LABEL: ld_or_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -3776,8 +3629,7 @@ define dso_local i64 @ld_not_disjoint16_uint64_t_int32_t(i64 %ptr) {
; CHECK-LABEL: ld_not_disjoint16_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -3792,8 +3644,7 @@ define dso_local i64 @ld_disjoint_align16_uint64_t_int32_t(i64 %ptr) {
; CHECK-LABEL: ld_disjoint_align16_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
-; CHECK-NEXT: lwz r3, 24(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 24(r3)
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -3810,8 +3661,7 @@ define dso_local i64 @ld_not_disjoint32_uint64_t_int32_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -3837,8 +3687,7 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_int32_t(i64 %ptr) {
; CHECK-P9-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
-; CHECK-P9-NEXT: lwzx r3, r3, r4
-; CHECK-P9-NEXT: extsw r3, r3
+; CHECK-P9-NEXT: lwax r3, r3, r4
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_int32_t:
@@ -3847,8 +3696,7 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_int32_t(i64 %ptr) {
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
-; CHECK-P8-NEXT: lwzx r3, r3, r4
-; CHECK-P8-NEXT: extsw r3, r3
+; CHECK-P8-NEXT: lwax r3, r3, r4
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -3867,8 +3715,7 @@ define dso_local i64 @ld_not_disjoint64_uint64_t_int32_t(i64 %ptr) {
; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
-; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwa r3, 0(r3)
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_int32_t:
@@ -3878,8 +3725,7 @@ define dso_local i64 @ld_not_disjoint64_uint64_t_int32_t(i64 %ptr) {
; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
-; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwa r3, 0(r3)
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -3896,8 +3742,7 @@ define dso_local i64 @ld_disjoint_align64_uint64_t_int32_t(i64 %ptr) {
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwax r3, r3, r4
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_int32_t:
@@ -3906,8 +3751,7 @@ define dso_local i64 @ld_disjoint_align64_uint64_t_int32_t(i64 %ptr) {
; CHECK-PREP10-NEXT: rldicr r3, r3, 0, 23
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -3922,8 +3766,7 @@ entry:
define dso_local i64 @ld_cst_align16_uint64_t_int32_t() {
; CHECK-LABEL: ld_cst_align16_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 4080(0)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 4080(0)
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
@@ -3936,8 +3779,7 @@ define dso_local i64 @ld_cst_align32_uint64_t_int32_t() {
; CHECK-LABEL: ld_cst_align32_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
-; CHECK-NEXT: lwz r3, -27108(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, -27108(r3)
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
@@ -3951,8 +3793,7 @@ define dso_local i64 @ld_cst_align64_uint64_t_int32_t() {
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
-; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwa r3, 0(r3)
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_int32_t:
@@ -3960,8 +3801,7 @@ define dso_local i64 @ld_cst_align64_uint64_t_int32_t() {
; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwa r3, 0(r3)
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
diff --git a/llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
index d04487af90ff..57e2399bd959 100644
--- a/llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
@@ -1236,7 +1236,6 @@ define dso_local zeroext i8 @ld_0_uint8_t_uint8_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint8_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
@@ -1249,7 +1248,6 @@ define dso_local zeroext i8 @ld_align16_uint8_t_uint8_t(i8* nocapture readonly %
; CHECK-LABEL: ld_align16_uint8_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -1270,7 +1268,6 @@ define dso_local zeroext i8 @ld_align32_uint8_t_uint8_t(i8* nocapture readonly %
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -1285,7 +1282,6 @@ define dso_local zeroext i8 @ld_align64_uint8_t_uint8_t(i8* nocapture readonly %
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint8_t_uint8_t:
@@ -1294,7 +1290,6 @@ define dso_local zeroext i8 @ld_align64_uint8_t_uint8_t(i8* nocapture readonly %
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -1307,7 +1302,6 @@ define dso_local zeroext i8 @ld_reg_uint8_t_uint8_t(i8* nocapture readonly %ptr,
; CHECK-LABEL: ld_reg_uint8_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -1321,7 +1315,6 @@ define dso_local zeroext i8 @ld_or_uint8_t_uint8_t(i64 %ptr, i8 zeroext %off) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -1337,7 +1330,6 @@ define dso_local zeroext i8 @ld_not_disjoint16_uint8_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -1352,7 +1344,6 @@ define dso_local zeroext i8 @ld_disjoint_align16_uint8_t_uint8_t(i64 %ptr) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -1369,7 +1360,6 @@ define dso_local zeroext i8 @ld_not_disjoint32_uint8_t_uint8_t(i64 %ptr) {
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -1395,7 +1385,6 @@ define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_uint8_t(i64 %ptr) {
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_uint8_t:
@@ -1405,7 +1394,6 @@ define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_uint8_t(i64 %ptr) {
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -1424,7 +1412,6 @@ define dso_local zeroext i8 @ld_not_disjoint64_uint8_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_uint8_t:
@@ -1435,7 +1422,6 @@ define dso_local zeroext i8 @ld_not_disjoint64_uint8_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -1452,7 +1438,6 @@ define dso_local zeroext i8 @ld_disjoint_align64_uint8_t_uint8_t(i64 %ptr) {
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_uint8_t:
@@ -1462,7 +1447,6 @@ define dso_local zeroext i8 @ld_disjoint_align64_uint8_t_uint8_t(i64 %ptr) {
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -1477,7 +1461,6 @@ define dso_local zeroext i8 @ld_cst_align16_uint8_t_uint8_t() {
; CHECK-LABEL: ld_cst_align16_uint8_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -1490,7 +1473,6 @@ define dso_local zeroext i8 @ld_cst_align32_uint8_t_uint8_t() {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -1504,7 +1486,6 @@ define dso_local zeroext i8 @ld_cst_align64_uint8_t_uint8_t() {
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_uint8_t:
@@ -1513,7 +1494,6 @@ define dso_local zeroext i8 @ld_cst_align64_uint8_t_uint8_t() {
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
diff --git a/llvm/test/CodeGen/PowerPC/bcd-intrinsics.ll b/llvm/test/CodeGen/PowerPC/bcd-intrinsics.ll
index fa9f656c4b20..6f494f32e0bc 100644
--- a/llvm/test/CodeGen/PowerPC/bcd-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/bcd-intrinsics.ll
@@ -11,7 +11,6 @@ define dso_local i64 @test_invalid(<16 x i8> %a) local_unnamed_addr #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v2, 0
; CHECK-NEXT: setbc r3, 4*cr6+un
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_invalid:
@@ -19,7 +18,6 @@ define dso_local i64 @test_invalid(<16 x i8> %a) local_unnamed_addr #0 {
; CHECK-P9-NEXT: bcdsub. v2, v2, v2, 0
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 28, 31, 31
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 6, <16 x i8> %a, <16 x i8> %a) #2
@@ -47,7 +45,6 @@ define dso_local i64 @test_add_ofl(<16 x i8> %a, <16 x i8> %b, i64 %ps) local_un
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdadd. v2, v2, v3, 0
; CHECK-NEXT: setbc r3, 4*cr6+un
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_add_ofl:
@@ -55,7 +52,6 @@ define dso_local i64 @test_add_ofl(<16 x i8> %a, <16 x i8> %b, i64 %ps) local_un
; CHECK-P9-NEXT: bcdadd. v2, v2, v3, 0
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 28, 31, 31
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdadd.p(i32 6, <16 x i8> %a, <16 x i8> %b) #2
@@ -83,7 +79,6 @@ define dso_local i64 @test_sub_ofl(<16 x i8> %a, <16 x i8> %b, i64 %ps) local_un
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-NEXT: setbc r3, 4*cr6+un
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_sub_ofl:
@@ -91,7 +86,6 @@ define dso_local i64 @test_sub_ofl(<16 x i8> %a, <16 x i8> %b, i64 %ps) local_un
; CHECK-P9-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 28, 31, 31
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 6, <16 x i8> %a, <16 x i8> %b) #2
@@ -104,7 +98,6 @@ define dso_local i64 @test_cmplt(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-NEXT: setbc r3, 4*cr6+lt
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_cmplt:
@@ -112,7 +105,6 @@ define dso_local i64 @test_cmplt(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr
; CHECK-P9-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 25, 31, 31
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 2, <16 x i8> %a, <16 x i8> %b) #2
@@ -125,7 +117,6 @@ define dso_local i64 @test_cmpgt(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-NEXT: setbc r3, 4*cr6+gt
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_cmpgt:
@@ -133,7 +124,6 @@ define dso_local i64 @test_cmpgt(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr
; CHECK-P9-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 26, 31, 31
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 4, <16 x i8> %a, <16 x i8> %b) #2
@@ -146,7 +136,6 @@ define dso_local i64 @test_cmpeq(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-NEXT: setbc r3, 4*cr6+eq
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_cmpeq:
@@ -154,7 +143,6 @@ define dso_local i64 @test_cmpeq(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr
; CHECK-P9-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 27, 31, 31
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 0, <16 x i8> %a, <16 x i8> %b) #2
@@ -167,7 +155,6 @@ define dso_local i64 @test_cmpge(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-NEXT: setbcr r3, 4*cr6+lt
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_cmpge:
@@ -176,7 +163,6 @@ define dso_local i64 @test_cmpge(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 25, 31, 31
; CHECK-P9-NEXT: xori r3, r3, 1
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 3, <16 x i8> %a, <16 x i8> %b) #2
@@ -189,7 +175,6 @@ define dso_local i64 @test_cmple(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-NEXT: setbcr r3, 4*cr6+gt
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_cmple:
@@ -198,7 +183,6 @@ define dso_local i64 @test_cmple(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 26, 31, 31
; CHECK-P9-NEXT: xori r3, r3, 1
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 5, <16 x i8> %a, <16 x i8> %b) #2
diff --git a/llvm/test/CodeGen/PowerPC/csr-split.ll b/llvm/test/CodeGen/PowerPC/csr-split.ll
index 0e2cf306e99b..fe5b4278f775 100644
--- a/llvm/test/CodeGen/PowerPC/csr-split.ll
+++ b/llvm/test/CodeGen/PowerPC/csr-split.ll
@@ -113,7 +113,6 @@ define dso_local signext i32 @test2(i32* %p1) local_unnamed_addr {
; CHECK-PWR9-NEXT: bl callNonVoid
; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: .LBB1_3: # %return
-; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: addi r1, r1, 48
; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
@@ -146,7 +145,6 @@ define dso_local signext i32 @test2(i32* %p1) local_unnamed_addr {
; CHECK-NEXT: nop
; CHECK-NEXT: .LBB1_3: # %return
; CHECK-NEXT: ld r30, 112(r1) # 8-byte Folded Reload
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: addi r1, r1, 128
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
@@ -190,7 +188,6 @@ define dso_local i8* @test3(i8** nocapture %p1, i8 zeroext %p2) local_unnamed_ad
; CHECK-PWR9-NEXT: beq cr0, .LBB2_2
; CHECK-PWR9-NEXT: # %bb.1: # %land.rhs
; CHECK-PWR9-NEXT: mr r29, r3
-; CHECK-PWR9-NEXT: clrldi r4, r4, 32
; CHECK-PWR9-NEXT: mr r3, r30
; CHECK-PWR9-NEXT: bl bar
; CHECK-PWR9-NEXT: nop
@@ -220,7 +217,6 @@ define dso_local i8* @test3(i8** nocapture %p1, i8 zeroext %p2) local_unnamed_ad
; CHECK-NEXT: beq cr0, .LBB2_2
; CHECK-NEXT: # %bb.1: # %land.rhs
; CHECK-NEXT: mr r29, r3
-; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: mr r3, r30
; CHECK-NEXT: bl bar
; CHECK-NEXT: nop
diff --git a/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll b/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
index 78f6ec0204be..299f219c028b 100644
--- a/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
+++ b/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
@@ -16,23 +16,22 @@ define void @foo(i32 zeroext %n, <256 x i1>* %ptr, <256 x i1>* %ptr2) {
; CHECK-NEXT: cmplwi r3, 0
; CHECK-NEXT: beqlr cr0
; CHECK-NEXT: # %bb.1: # %for.body.lr.ph
-; CHECK-NEXT: clrldi r6, r3, 32
-; CHECK-NEXT: addi r3, r4, 64
-; CHECK-NEXT: addi r4, r5, 64
-; CHECK-NEXT: mtctr r6
+; CHECK-NEXT: addi r4, r4, 64
+; CHECK-NEXT: addi r5, r5, 64
+; CHECK-NEXT: mtctr r3
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_2: # %for.body
; CHECK-NEXT: #
-; CHECK-NEXT: lxvp vsp34, -64(r3)
-; CHECK-NEXT: lxvp vsp36, -32(r3)
-; CHECK-NEXT: lxvp vsp32, 0(r3)
-; CHECK-NEXT: lxvp vsp38, 32(r3)
-; CHECK-NEXT: addi r3, r3, 1
-; CHECK-NEXT: stxvp vsp34, -64(r4)
-; CHECK-NEXT: stxvp vsp36, -32(r4)
-; CHECK-NEXT: stxvp vsp32, 0(r4)
-; CHECK-NEXT: stxvp vsp38, 32(r4)
+; CHECK-NEXT: lxvp vsp34, -64(r4)
+; CHECK-NEXT: lxvp vsp36, -32(r4)
+; CHECK-NEXT: lxvp vsp32, 0(r4)
+; CHECK-NEXT: lxvp vsp38, 32(r4)
; CHECK-NEXT: addi r4, r4, 1
+; CHECK-NEXT: stxvp vsp34, -64(r5)
+; CHECK-NEXT: stxvp vsp36, -32(r5)
+; CHECK-NEXT: stxvp vsp32, 0(r5)
+; CHECK-NEXT: stxvp vsp38, 32(r5)
+; CHECK-NEXT: addi r5, r5, 1
; CHECK-NEXT: bdnz .LBB0_2
; CHECK-NEXT: # %bb.3: # %for.cond.cleanup
; CHECK-NEXT: blr
@@ -42,23 +41,22 @@ define void @foo(i32 zeroext %n, <256 x i1>* %ptr, <256 x i1>* %ptr2) {
; CHECK-BE-NEXT: cmplwi r3, 0
; CHECK-BE-NEXT: beqlr cr0
; CHECK-BE-NEXT: # %bb.1: # %for.body.lr.ph
-; CHECK-BE-NEXT: clrldi r6, r3, 32
-; CHECK-BE-NEXT: addi r3, r4, 64
-; CHECK-BE-NEXT: addi r4, r5, 64
-; CHECK-BE-NEXT: mtctr r6
+; CHECK-BE-NEXT: addi r4, r4, 64
+; CHECK-BE-NEXT: addi r5, r5, 64
+; CHECK-BE-NEXT: mtctr r3
; CHECK-BE-NEXT: .p2align 4
; CHECK-BE-NEXT: .LBB0_2: # %for.body
; CHECK-BE-NEXT: #
-; CHECK-BE-NEXT: lxvp vsp34, -64(r3)
-; CHECK-BE-NEXT: lxvp vsp36, -32(r3)
-; CHECK-BE-NEXT: lxvp vsp32, 0(r3)
-; CHECK-BE-NEXT: lxvp vsp38, 32(r3)
-; CHECK-BE-NEXT: addi r3, r3, 1
-; CHECK-BE-NEXT: stxvp vsp34, -64(r4)
-; CHECK-BE-NEXT: stxvp vsp36, -32(r4)
-; CHECK-BE-NEXT: stxvp vsp32, 0(r4)
-; CHECK-BE-NEXT: stxvp vsp38, 32(r4)
+; CHECK-BE-NEXT: lxvp vsp34, -64(r4)
+; CHECK-BE-NEXT: lxvp vsp36, -32(r4)
+; CHECK-BE-NEXT: lxvp vsp32, 0(r4)
+; CHECK-BE-NEXT: lxvp vsp38, 32(r4)
; CHECK-BE-NEXT: addi r4, r4, 1
+; CHECK-BE-NEXT: stxvp vsp34, -64(r5)
+; CHECK-BE-NEXT: stxvp vsp36, -32(r5)
+; CHECK-BE-NEXT: stxvp vsp32, 0(r5)
+; CHECK-BE-NEXT: stxvp vsp38, 32(r5)
+; CHECK-BE-NEXT: addi r5, r5, 1
; CHECK-BE-NEXT: bdnz .LBB0_2
; CHECK-BE-NEXT: # %bb.3: # %for.cond.cleanup
; CHECK-BE-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel.ll b/llvm/test/CodeGen/PowerPC/expand-isel.ll
index 773658f6f338..8a7fb75a8726 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-isel.ll
@@ -193,10 +193,7 @@ cleanup:
; CHECK-LABEL: @testComplexISEL
; CHECK: cmplwi r3, 0
; CHECK: li r3, 1
-; CHECK: beq cr0, [[TGT:.LBB[0-9_]+]]
-; CHECK: clrldi r3, r3, 32
-; CHECK: blr
-; CHECK: [[TGT]]
+; CHECK: bnelr cr0
; CHECK: xor [[XOR:r[0-9]+]]
; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63
diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll b/llvm/test/CodeGen/PowerPC/f128-conv.ll
index fff30a11917a..b419c41806e4 100644
--- a/llvm/test/CodeGen/PowerPC/f128-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll
@@ -1999,7 +1999,6 @@ define void @cvdp2uw2qp(double %val, fp128* nocapture %res) {
; CHECK-P8-NEXT: xscvdpuxws f0, f1
; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
@@ -2075,7 +2074,6 @@ define void @cvsp2uw2qp(float %val, fp128* nocapture %res) {
; CHECK-P8-NEXT: xscvdpuxws f0, f1
; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
diff --git a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
index 04ea185e0b4c..84cb9c597bde 100644
--- a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
@@ -627,7 +627,6 @@ define zeroext i32 @qpConv2uw(fp128* nocapture readonly %a) {
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2uw:
@@ -707,7 +706,6 @@ define zeroext i32 @qpConv2uw_03(fp128* nocapture readonly %a) {
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2uw_03:
@@ -964,7 +962,6 @@ define zeroext i16 @qpConv2uhw(fp128* nocapture readonly %a) {
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2uhw:
@@ -1042,7 +1039,6 @@ define zeroext i16 @qpConv2uhw_03(fp128* nocapture readonly %a) {
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2uhw_03:
@@ -1296,7 +1292,6 @@ define zeroext i8 @qpConv2ub(fp128* nocapture readonly %a) {
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2ub:
@@ -1374,7 +1369,6 @@ define zeroext i8 @qpConv2ub_03(fp128* nocapture readonly %a) {
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2ub_03:
diff --git a/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll b/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
index 268d89174216..9fd3a653efb0 100644
--- a/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
@@ -11,7 +11,6 @@ define zeroext i8 @_Z6testcff(float %arg) {
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca float, align 4
@@ -44,7 +43,6 @@ define zeroext i8 @_Z6testcdd(double %arg) {
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca double, align 8
@@ -77,7 +75,6 @@ define zeroext i8 @_Z7testucff(float %arg) {
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca float, align 4
@@ -110,7 +107,6 @@ define zeroext i8 @_Z7testucdd(double %arg) {
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca double, align 8
@@ -209,7 +205,6 @@ define zeroext i16 @_Z7testusff(float %arg) {
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca float, align 4
@@ -242,7 +237,6 @@ define zeroext i16 @_Z7testusdd(double %arg) {
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca double, align 8
@@ -341,7 +335,6 @@ define zeroext i32 @_Z7testuiff(float %arg) {
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca float, align 4
@@ -374,7 +367,6 @@ define zeroext i32 @_Z7testuidd(double %arg) {
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca double, align 8
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
index dcc077ef0d70..6e02d1ed4e14 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
@@ -447,7 +447,6 @@ define zeroext i32 @q_to_u32(fp128 %m) #0 {
; P9: # %bb.0: # %entry
; P9-NEXT: xscvqpuwz v2, v2
; P9-NEXT: mfvsrwz r3, v2
-; P9-NEXT: clrldi r3, r3, 32
; P9-NEXT: blr
;
; NOVSX-LABEL: q_to_u32:
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll b/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll
index 3e26f417ceab..abdf3d133781 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll
@@ -89,7 +89,6 @@ define zeroext i32 @d_to_u32(double %m) #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; NOVSX-LABEL: d_to_u32:
@@ -165,7 +164,6 @@ define zeroext i32 @f_to_u32(float %m) #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; NOVSX-LABEL: f_to_u32:
diff --git a/llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll b/llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
index 1d4e865d2c06..f5d106404754 100644
--- a/llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
+++ b/llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
@@ -13,7 +13,6 @@ define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) loc
; CHECK-NEXT: vcmpgtsw. 2, 4, 3
; CHECK-NEXT: mfocrf 3, 2
; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31
-; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: blr
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: li 3, 0
@@ -27,7 +26,6 @@ define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) loc
; CHECK-AIX-64-NEXT: vcmpgtsw. 2, 4, 3
; CHECK-AIX-64-NEXT: mfocrf 3, 2
; CHECK-AIX-64-NEXT: rlwinm 3, 3, 25, 31, 31
-; CHECK-AIX-64-NEXT: clrldi 3, 3, 32
; CHECK-AIX-64-NEXT: blr
; CHECK-AIX-64-NEXT: L..BB0_2:
; CHECK-AIX-64-NEXT: li 3, 0
diff --git a/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll b/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
index d1b9554abdf5..fad8548dc675 100644
--- a/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
+++ b/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
@@ -22,7 +22,6 @@ define i64 @foo(i8* %p, i32 signext %n, i32 signext %count) {
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: addi r6, r3, 5
; CHECK-NEXT: addi r3, r4, -1
-; CHECK-NEXT: extsw r5, r5
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: mtctr r3
@@ -88,7 +87,6 @@ define zeroext i8 @foo1(i8* %p, i32 signext %n, i32 signext %count) {
; CHECK-NEXT: cmpwi r4, 1
; CHECK-NEXT: blt cr0, .LBB1_4
; CHECK-NEXT: # %bb.1: # %for.body.preheader
-; CHECK-NEXT: extsw r5, r5
; CHECK-NEXT: sub r3, r3, r5
; CHECK-NEXT: addi r6, r3, 1000
; CHECK-NEXT: addi r3, r4, -1
diff --git a/llvm/test/CodeGen/PowerPC/machine-pre.ll b/llvm/test/CodeGen/PowerPC/machine-pre.ll
index 98ed27db965b..facf56222b02 100644
--- a/llvm/test/CodeGen/PowerPC/machine-pre.ll
+++ b/llvm/test/CodeGen/PowerPC/machine-pre.ll
@@ -83,11 +83,11 @@ define dso_local signext i32 @foo(i32 signext %x, i32 signext %y) nounwind {
; CHECK-P9-NEXT: bge cr0, .LBB1_7
; CHECK-P9-NEXT: .LBB1_4: # %while.cond
; CHECK-P9-NEXT: #
-; CHECK-P9-NEXT: extsw r3, r29
+; CHECK-P9-NEXT: mr r3, r29
; CHECK-P9-NEXT: bl bar
; CHECK-P9-NEXT: nop
; CHECK-P9-NEXT: mr r29, r3
-; CHECK-P9-NEXT: extsw r3, r30
+; CHECK-P9-NEXT: mr r3, r30
; CHECK-P9-NEXT: bl bar
; CHECK-P9-NEXT: nop
; CHECK-P9-NEXT: mr r30, r3
diff --git a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
index aaf6a9e4cb35..72df22e69427 100644
--- a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
+++ b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
@@ -44,11 +44,9 @@ define signext i32 @zeroEqualityTest01(i8* %x, i8* %y) {
; CHECK-NEXT: ld 4, 8(4)
; CHECK-NEXT: cmpld 3, 4
; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: beq 0, .LBB1_3
+; CHECK-NEXT: beqlr 0
; CHECK-NEXT: .LBB1_2: # %res_block
; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: .LBB1_3: # %endblock
-; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: blr
%call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 16)
%not.tobool = icmp ne i32 %call, 0
@@ -74,11 +72,9 @@ define signext i32 @zeroEqualityTest03(i8* %x, i8* %y) {
; CHECK-NEXT: lbz 4, 6(4)
; CHECK-NEXT: cmplw 3, 4
; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: beq 0, .LBB2_4
+; CHECK-NEXT: beqlr 0
; CHECK-NEXT: .LBB2_3: # %res_block
; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: .LBB2_4: # %endblock
-; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: blr
%call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 7)
%not.lnot = icmp ne i32 %call, 0
diff --git a/llvm/test/CodeGen/PowerPC/optcmp.ll b/llvm/test/CodeGen/PowerPC/optcmp.ll
index 2e09d76c6976..51ebbbd4fc66 100644
--- a/llvm/test/CodeGen/PowerPC/optcmp.ll
+++ b/llvm/test/CodeGen/PowerPC/optcmp.ll
@@ -9,25 +9,21 @@ define signext i32 @foo(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpw 3, 4
-; CHECK-NEXT: iselgt 6, 3, 4
-; CHECK-NEXT: sub 4, 3, 4
-; CHECK-NEXT: extsw 3, 6
-; CHECK-NEXT: stw 4, 0(5)
+; CHECK-NEXT: sub 6, 3, 4
+; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: stw 6, 0(5)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: foo:
; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: cmpw 3, 4
+; CHECK-NO-ISEL-NEXT: sub 6, 3, 4
; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB0_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT: ori 6, 4, 0
-; CHECK-NO-ISEL-NEXT: b .LBB0_3
+; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
+; CHECK-NO-ISEL-NEXT: b .LBB0_2
; CHECK-NO-ISEL-NEXT: .LBB0_2: # %entry
-; CHECK-NO-ISEL-NEXT: addi 6, 3, 0
-; CHECK-NO-ISEL-NEXT: .LBB0_3: # %entry
-; CHECK-NO-ISEL-NEXT: sub 4, 3, 4
-; CHECK-NO-ISEL-NEXT: extsw 3, 6
-; CHECK-NO-ISEL-NEXT: stw 4, 0(5)
+; CHECK-NO-ISEL-NEXT: stw 6, 0(5)
; CHECK-NO-ISEL-NEXT: blr
entry:
%sub = sub nsw i32 %a, %b
diff --git a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
index c8d4b4bda1c0..edacc81287ae 100644
--- a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
+++ b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
@@ -676,7 +676,6 @@ define zeroext i8 @getuc0(<16 x i8> %vuc) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 8, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc0:
@@ -684,14 +683,12 @@ define zeroext i8 @getuc0(<16 x i8> %vuc) {
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: clrldi r3, r3, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc0:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 8, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 0
@@ -706,7 +703,6 @@ define zeroext i8 @getuc1(<16 x i8> %vuc) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 16, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc1:
@@ -714,14 +710,12 @@ define zeroext i8 @getuc1(<16 x i8> %vuc) {
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 56, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc1:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 16, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 1
@@ -736,7 +730,6 @@ define zeroext i8 @getuc2(<16 x i8> %vuc) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 24, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc2:
@@ -744,14 +737,12 @@ define zeroext i8 @getuc2(<16 x i8> %vuc) {
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 48, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc2:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 24, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 2
@@ -764,7 +755,6 @@ define zeroext i8 @getuc3(<16 x i8> %vuc) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 32, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc3:
@@ -772,14 +762,12 @@ define zeroext i8 @getuc3(<16 x i8> %vuc) {
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 40, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc3:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 32, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 3
@@ -794,7 +782,6 @@ define zeroext i8 @getuc4(<16 x i8> %vuc) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 40, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc4:
@@ -802,14 +789,12 @@ define zeroext i8 @getuc4(<16 x i8> %vuc) {
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 32, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc4:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 40, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 4
@@ -824,7 +809,6 @@ define zeroext i8 @getuc5(<16 x i8> %vuc) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 48, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc5:
@@ -832,14 +816,12 @@ define zeroext i8 @getuc5(<16 x i8> %vuc) {
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 24, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc5:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 48, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 5
@@ -854,7 +836,6 @@ define zeroext i8 @getuc6(<16 x i8> %vuc) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 56, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc6:
@@ -862,14 +843,12 @@ define zeroext i8 @getuc6(<16 x i8> %vuc) {
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 16, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc6:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 56, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 6
@@ -884,7 +863,6 @@ define zeroext i8 @getuc7(<16 x i8> %vuc) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: clrldi r3, r3, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc7:
@@ -892,14 +870,12 @@ define zeroext i8 @getuc7(<16 x i8> %vuc) {
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 8, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc7:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: clrldi 3, 3, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 7
@@ -915,14 +891,12 @@ define zeroext i8 @getuc8(<16 x i8> %vuc) {
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 8, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc8:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: clrldi r3, r3, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc8:
@@ -930,7 +904,6 @@ define zeroext i8 @getuc8(<16 x i8> %vuc) {
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 8, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 8
@@ -946,14 +919,12 @@ define zeroext i8 @getuc9(<16 x i8> %vuc) {
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 16, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc9:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 56, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc9:
@@ -961,7 +932,6 @@ define zeroext i8 @getuc9(<16 x i8> %vuc) {
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 16, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 9
@@ -977,14 +947,12 @@ define zeroext i8 @getuc10(<16 x i8> %vuc) {
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 24, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc10:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 48, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc10:
@@ -992,7 +960,6 @@ define zeroext i8 @getuc10(<16 x i8> %vuc) {
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 24, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 10
@@ -1008,14 +975,12 @@ define zeroext i8 @getuc11(<16 x i8> %vuc) {
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 32, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc11:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 40, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc11:
@@ -1023,7 +988,6 @@ define zeroext i8 @getuc11(<16 x i8> %vuc) {
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 32, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 11
@@ -1039,14 +1003,12 @@ define zeroext i8 @getuc12(<16 x i8> %vuc) {
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 40, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc12:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 32, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc12:
@@ -1054,7 +1016,6 @@ define zeroext i8 @getuc12(<16 x i8> %vuc) {
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 40, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 12
@@ -1070,14 +1031,12 @@ define zeroext i8 @getuc13(<16 x i8> %vuc) {
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 48, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc13:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 24, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc13:
@@ -1085,7 +1044,6 @@ define zeroext i8 @getuc13(<16 x i8> %vuc) {
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 48, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 13
@@ -1101,14 +1059,12 @@ define zeroext i8 @getuc14(<16 x i8> %vuc) {
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 56, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc14:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 16, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc14:
@@ -1116,7 +1072,6 @@ define zeroext i8 @getuc14(<16 x i8> %vuc) {
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 56, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 14
@@ -1132,14 +1087,12 @@ define zeroext i8 @getuc15(<16 x i8> %vuc) {
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: clrldi r3, r3, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc15:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 8, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc15:
@@ -1147,7 +1100,6 @@ define zeroext i8 @getuc15(<16 x i8> %vuc) {
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: clrldi 3, 3, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 15
@@ -1502,7 +1454,6 @@ define zeroext i16 @getus0(<8 x i16> %vus) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 16, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus0:
@@ -1510,14 +1461,12 @@ define zeroext i16 @getus0(<8 x i16> %vus) {
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: clrldi r3, r3, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus0:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 16, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 0
@@ -1532,7 +1481,6 @@ define zeroext i16 @getus1(<8 x i16> %vus) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 32, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus1:
@@ -1540,14 +1488,12 @@ define zeroext i16 @getus1(<8 x i16> %vus) {
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 48, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus1:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 32, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 1
@@ -1562,7 +1508,6 @@ define zeroext i16 @getus2(<8 x i16> %vus) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 48, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus2:
@@ -1570,14 +1515,12 @@ define zeroext i16 @getus2(<8 x i16> %vus) {
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 32, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus2:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 48, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 2
@@ -1592,7 +1535,6 @@ define zeroext i16 @getus3(<8 x i16> %vus) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: clrldi r3, r3, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus3:
@@ -1600,14 +1542,12 @@ define zeroext i16 @getus3(<8 x i16> %vus) {
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 16, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus3:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: clrldi 3, 3, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 3
@@ -1623,14 +1563,12 @@ define zeroext i16 @getus4(<8 x i16> %vus) {
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 16, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus4:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: clrldi r3, r3, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus4:
@@ -1638,7 +1576,6 @@ define zeroext i16 @getus4(<8 x i16> %vus) {
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 16, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 4
@@ -1654,14 +1591,12 @@ define zeroext i16 @getus5(<8 x i16> %vus) {
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 32, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus5:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 48, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus5:
@@ -1669,7 +1604,6 @@ define zeroext i16 @getus5(<8 x i16> %vus) {
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 32, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 5
@@ -1685,14 +1619,12 @@ define zeroext i16 @getus6(<8 x i16> %vus) {
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 48, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus6:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 32, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus6:
@@ -1700,7 +1632,6 @@ define zeroext i16 @getus6(<8 x i16> %vus) {
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 48, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 6
@@ -1716,14 +1647,12 @@ define zeroext i16 @getus7(<8 x i16> %vus) {
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: clrldi r3, r3, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus7:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 16, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus7:
@@ -1731,7 +1660,6 @@ define zeroext i16 @getus7(<8 x i16> %vus) {
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: clrldi 3, 3, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 7
@@ -1961,21 +1889,18 @@ define zeroext i32 @getui0(<4 x i32> %vui) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getui0:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprwz r3, f0
-; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getui0:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: xxsldwi 0, 34, 34, 3
; CHECK-AIX-NEXT: mffprwz 3, 0
-; CHECK-AIX-NEXT: clrldi 3, 3, 32
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %vui, i32 0
@@ -1989,20 +1914,17 @@ define zeroext i32 @getui1(<4 x i32> %vui) {
; CHECK-LABEL: getui1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getui1:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-LE-NEXT: mffprwz r3, f0
-; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getui1:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrwz 3, 34
-; CHECK-AIX-NEXT: clrldi 3, 3, 32
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %vui, i32 1
@@ -2017,20 +1939,17 @@ define zeroext i32 @getui2(<4 x i32> %vui) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getui2:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrwz r3, v2
-; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getui2:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: xxsldwi 0, 34, 34, 1
; CHECK-AIX-NEXT: mffprwz 3, 0
-; CHECK-AIX-NEXT: clrldi 3, 3, 32
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %vui, i32 2
@@ -2045,21 +1964,18 @@ define zeroext i32 @getui3(<4 x i32> %vui) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getui3:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-LE-NEXT: mffprwz r3, f0
-; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getui3:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprwz 3, 0
-; CHECK-AIX-NEXT: clrldi 3, 3, 32
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %vui, i32 3
diff --git a/llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll b/llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll
index 71755f722cb2..2cfbb2d00df7 100644
--- a/llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll
@@ -31,7 +31,7 @@ cleanup: ; preds = %for.body, %for.cond
; CHECK-LABEL: limit_loop
; CHECK: mtctr
; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, 1
-; CHECK: bdnz
+; CHECK: bdzlr
; CHECK: blr
}
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
index 6749d5f948df..98856d097ea5 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
@@ -663,7 +663,6 @@ define i64 @setb27(i64 %a, i64 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: cmpd r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-PWR8-LABEL: setb27:
@@ -690,7 +689,6 @@ define i64 @setb28(i64 %a, i64 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: cmpd r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-PWR8-LABEL: setb28:
@@ -882,8 +880,6 @@ define i64 @setbsc1(i8 %a, i8 %b) {
; CHECK-PWR8-NEXT: extsb r4, r4
; CHECK-PWR8-NEXT: extsb r3, r3
; CHECK-PWR8-NEXT: li r5, -1
-; CHECK-PWR8-NEXT: extsw r4, r4
-; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: sub r6, r4, r3
; CHECK-PWR8-NEXT: cmpw r3, r4
; CHECK-PWR8-NEXT: rldicl r3, r6, 1, 63
@@ -911,8 +907,6 @@ define i64 @setbsc2(i8 %a, i8 %b) {
; CHECK-PWR8-NEXT: extsb r4, r4
; CHECK-PWR8-NEXT: extsb r3, r3
; CHECK-PWR8-NEXT: li r5, -1
-; CHECK-PWR8-NEXT: extsw r4, r4
-; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: sub r6, r4, r3
; CHECK-PWR8-NEXT: cmpw r4, r3
; CHECK-PWR8-NEXT: rldicl r3, r6, 1, 63
@@ -944,8 +938,6 @@ define i64 @setbsc3(i4 %a, i4 %b) {
; CHECK-PWR8-NEXT: li r5, -1
; CHECK-PWR8-NEXT: srawi r4, r4, 28
; CHECK-PWR8-NEXT: srawi r3, r3, 28
-; CHECK-PWR8-NEXT: extsw r4, r4
-; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: sub r6, r4, r3
; CHECK-PWR8-NEXT: cmpw r3, r4
; CHECK-PWR8-NEXT: rldicl r3, r6, 1, 63
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll b/llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll
index 604a39ec8367..1eddb24ad514 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll
@@ -82,7 +82,6 @@ define dso_local signext i32 @ClobberLR_BR(i32 signext %in) #0 {
; PPC64LE-NEXT: nop
; PPC64LE-NEXT: #NO_APP
; PPC64LE-NEXT: .LBB3_1: # %return
-; PPC64LE-NEXT: extsw r3, r3
; PPC64LE-NEXT: addi r1, r1, 32
; PPC64LE-NEXT: ld r0, 16(r1)
; PPC64LE-NEXT: mtlr r0
@@ -102,7 +101,6 @@ define dso_local signext i32 @ClobberLR_BR(i32 signext %in) #0 {
; PPC64BE-NEXT: nop
; PPC64BE-NEXT: #NO_APP
; PPC64BE-NEXT: .LBB3_1: # %return
-; PPC64BE-NEXT: extsw r3, r3
; PPC64BE-NEXT: addi r1, r1, 48
; PPC64BE-NEXT: ld r0, 16(r1)
; PPC64BE-NEXT: mtlr r0
@@ -131,13 +129,11 @@ define dso_local signext i32 @ClobberR5_BR(i32 signext %in) #0 {
; PPC64LE-NEXT: nop
; PPC64LE-NEXT: #NO_APP
; PPC64LE-NEXT: # %bb.1: # %return
-; PPC64LE-NEXT: extsw r3, r3
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB4_2: # Block address taken
; PPC64LE-NEXT: # %return_early
; PPC64LE-NEXT: # Label of block must be emitted
; PPC64LE-NEXT: li r3, 0
-; PPC64LE-NEXT: extsw r3, r3
; PPC64LE-NEXT: blr
;
; PPC64BE-LABEL: ClobberR5_BR:
@@ -146,13 +142,11 @@ define dso_local signext i32 @ClobberR5_BR(i32 signext %in) #0 {
; PPC64BE-NEXT: nop
; PPC64BE-NEXT: #NO_APP
; PPC64BE-NEXT: # %bb.1: # %return
-; PPC64BE-NEXT: extsw r3, r3
; PPC64BE-NEXT: blr
; PPC64BE-NEXT: .LBB4_2: # Block address taken
; PPC64BE-NEXT: # %return_early
; PPC64BE-NEXT: # Label of block must be emitted
; PPC64BE-NEXT: li r3, 0
-; PPC64BE-NEXT: extsw r3, r3
; PPC64BE-NEXT: blr
entry:
callbr void asm sideeffect "nop", "!i,~{r5}"()
diff --git a/llvm/test/CodeGen/PowerPC/pr41088.ll b/llvm/test/CodeGen/PowerPC/pr41088.ll
index f3899bb15381..bcaf07f98efc 100644
--- a/llvm/test/CodeGen/PowerPC/pr41088.ll
+++ b/llvm/test/CodeGen/PowerPC/pr41088.ll
@@ -46,13 +46,12 @@ define void @test(%6* %arg, %7* %arg1, %12* %arg2) unnamed_addr personality i32
; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16
-; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: li r4, 0
; CHECK-NEXT: # %bb.1: # %bb9
; CHECK-NEXT: bl test5
; CHECK-NEXT: nop
-; CHECK-NEXT: rlwinm r3, r3, 8, 16, 23
+; CHECK-NEXT: rlwinm r4, r3, 8, 16, 23
; CHECK-NEXT: # %bb.2: # %bb12
-; CHECK-NEXT: clrldi r4, r3, 32
; CHECK-NEXT: bl test3
; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32
diff --git a/llvm/test/CodeGen/PowerPC/pr47660.ll b/llvm/test/CodeGen/PowerPC/pr47660.ll
index 64feb2735806..79f185d1f7b5 100644
--- a/llvm/test/CodeGen/PowerPC/pr47660.ll
+++ b/llvm/test/CodeGen/PowerPC/pr47660.ll
@@ -16,7 +16,6 @@ define dso_local i24 @_Z1f1c(i24 %g.coerce) local_unnamed_addr #0 {
; CHECK-LE-NEXT: xsmuldp f0, f0, f1
; CHECK-LE-NEXT: xscvdpsxws f0, f0
; CHECK-LE-NEXT: mffprwz r3, f0
-; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: _Z1f1c:
@@ -31,7 +30,6 @@ define dso_local i24 @_Z1f1c(i24 %g.coerce) local_unnamed_addr #0 {
; CHECK-BE-NEXT: fctiwz f0, f0
; CHECK-BE-NEXT: stfd f0, -8(r1)
; CHECK-BE-NEXT: lwz r3, -4(r1)
-; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: blr
entry:
%0 = and i24 %g.coerce, 255
diff --git a/llvm/test/CodeGen/PowerPC/prefer-dqform.ll b/llvm/test/CodeGen/PowerPC/prefer-dqform.ll
index fabdabc620f8..5c5979e65b21 100644
--- a/llvm/test/CodeGen/PowerPC/prefer-dqform.ll
+++ b/llvm/test/CodeGen/PowerPC/prefer-dqform.ll
@@ -34,34 +34,33 @@ define void @test(i32* dereferenceable(4) %.ial, i32* noalias dereferenceable(4)
; CHECK-P9-NEXT: # %bb.1: # %_loop_2_do_.lr.ph
; CHECK-P9-NEXT: extswsli r5, r5, 3
; CHECK-P9-NEXT: extsw r10, r4
+; CHECK-P9-NEXT: lwa r4, 0(r7)
; CHECK-P9-NEXT: add r5, r8, r5
-; CHECK-P9-NEXT: clrldi r8, r3, 32
-; CHECK-P9-NEXT: lwa r3, 0(r7)
-; CHECK-P9-NEXT: addi r4, r8, 1
-; CHECK-P9-NEXT: addi r5, r5, -8
-; CHECK-P9-NEXT: lxvdsx vs0, 0, r5
-; CHECK-P9-NEXT: sub r3, r4, r3
+; CHECK-P9-NEXT: addi r8, r5, -8
+; CHECK-P9-NEXT: addi r5, r3, 1
+; CHECK-P9-NEXT: sub r3, r10, r3
+; CHECK-P9-NEXT: rldicl r3, r3, 60, 4
+; CHECK-P9-NEXT: lxvdsx vs0, 0, r8
+; CHECK-P9-NEXT: sub r4, r5, r4
+; CHECK-P9-NEXT: sldi r5, r5, 3
+; CHECK-P9-NEXT: addi r3, r3, 1
; CHECK-P9-NEXT: sldi r4, r4, 3
-; CHECK-P9-NEXT: sldi r3, r3, 3
-; CHECK-P9-NEXT: add r4, r9, r4
-; CHECK-P9-NEXT: add r3, r6, r3
-; CHECK-P9-NEXT: sub r6, r10, r8
-; CHECK-P9-NEXT: rldicl r6, r6, 60, 4
-; CHECK-P9-NEXT: addi r6, r6, 1
-; CHECK-P9-NEXT: mtctr r6
+; CHECK-P9-NEXT: add r5, r9, r5
+; CHECK-P9-NEXT: mtctr r3
+; CHECK-P9-NEXT: add r4, r6, r4
; CHECK-P9-NEXT: .p2align 4
; CHECK-P9-NEXT: .LBB0_2: # %_loop_2_do_
; CHECK-P9-NEXT: #
-; CHECK-P9-NEXT: lxv vs1, -16(r4)
-; CHECK-P9-NEXT: lxv vs2, 0(r4)
-; CHECK-P9-NEXT: lxv vs3, -16(r3)
-; CHECK-P9-NEXT: lxv vs4, 0(r3)
-; CHECK-P9-NEXT: addi r3, r3, 128
+; CHECK-P9-NEXT: lxv vs1, -16(r5)
+; CHECK-P9-NEXT: lxv vs2, 0(r5)
+; CHECK-P9-NEXT: lxv vs3, -16(r4)
+; CHECK-P9-NEXT: lxv vs4, 0(r4)
+; CHECK-P9-NEXT: addi r4, r4, 128
; CHECK-P9-NEXT: xvmaddadp vs1, vs3, vs1
-; CHECK-P9-NEXT: stxv vs1, -16(r4)
+; CHECK-P9-NEXT: stxv vs1, -16(r5)
; CHECK-P9-NEXT: xvmaddadp vs2, vs4, vs0
-; CHECK-P9-NEXT: stxv vs2, 0(r4)
-; CHECK-P9-NEXT: addi r4, r4, 128
+; CHECK-P9-NEXT: stxv vs2, 0(r5)
+; CHECK-P9-NEXT: addi r5, r5, 128
; CHECK-P9-NEXT: bdnz .LBB0_2
; CHECK-P9-NEXT: # %bb.3: # %_return_bb
; CHECK-P9-NEXT: blr
@@ -88,34 +87,33 @@ define void @test(i32* dereferenceable(4) %.ial, i32* noalias dereferenceable(4)
; CHECK-P10-NEXT: # %bb.1: # %_loop_2_do_.lr.ph
; CHECK-P10-NEXT: extswsli r5, r5, 3
; CHECK-P10-NEXT: extsw r10, r4
+; CHECK-P10-NEXT: lwa r4, 0(r7)
; CHECK-P10-NEXT: add r5, r8, r5
-; CHECK-P10-NEXT: clrldi r8, r3, 32
-; CHECK-P10-NEXT: lwa r3, 0(r7)
-; CHECK-P10-NEXT: addi r4, r8, 1
-; CHECK-P10-NEXT: addi r5, r5, -8
-; CHECK-P10-NEXT: lxvdsx vs0, 0, r5
-; CHECK-P10-NEXT: sub r3, r4, r3
+; CHECK-P10-NEXT: addi r8, r5, -8
+; CHECK-P10-NEXT: addi r5, r3, 1
+; CHECK-P10-NEXT: sub r3, r10, r3
+; CHECK-P10-NEXT: sub r4, r5, r4
+; CHECK-P10-NEXT: rldicl r3, r3, 60, 4
+; CHECK-P10-NEXT: sldi r5, r5, 3
+; CHECK-P10-NEXT: add r5, r9, r5
+; CHECK-P10-NEXT: lxvdsx vs0, 0, r8
+; CHECK-P10-NEXT: addi r3, r3, 1
; CHECK-P10-NEXT: sldi r4, r4, 3
-; CHECK-P10-NEXT: add r4, r9, r4
-; CHECK-P10-NEXT: sldi r3, r3, 3
-; CHECK-P10-NEXT: add r3, r6, r3
-; CHECK-P10-NEXT: sub r6, r10, r8
-; CHECK-P10-NEXT: rldicl r6, r6, 60, 4
-; CHECK-P10-NEXT: addi r6, r6, 1
-; CHECK-P10-NEXT: mtctr r6
+; CHECK-P10-NEXT: add r4, r6, r4
+; CHECK-P10-NEXT: mtctr r3
; CHECK-P10-NEXT: .p2align 4
; CHECK-P10-NEXT: .LBB0_2: # %_loop_2_do_
; CHECK-P10-NEXT: #
-; CHECK-P10-NEXT: lxv vs1, -16(r4)
-; CHECK-P10-NEXT: lxv vs2, 0(r4)
-; CHECK-P10-NEXT: lxv vs3, -16(r3)
+; CHECK-P10-NEXT: lxv vs1, -16(r5)
+; CHECK-P10-NEXT: lxv vs2, 0(r5)
+; CHECK-P10-NEXT: lxv vs3, -16(r4)
; CHECK-P10-NEXT: xvmaddadp vs1, vs3, vs1
-; CHECK-P10-NEXT: lxv vs4, 0(r3)
+; CHECK-P10-NEXT: lxv vs4, 0(r4)
; CHECK-P10-NEXT: xvmaddadp vs2, vs4, vs0
-; CHECK-P10-NEXT: addi r3, r3, 128
-; CHECK-P10-NEXT: stxv vs1, -16(r4)
-; CHECK-P10-NEXT: stxv vs2, 0(r4)
; CHECK-P10-NEXT: addi r4, r4, 128
+; CHECK-P10-NEXT: stxv vs1, -16(r5)
+; CHECK-P10-NEXT: stxv vs2, 0(r5)
+; CHECK-P10-NEXT: addi r5, r5, 128
; CHECK-P10-NEXT: bdnz .LBB0_2
; CHECK-P10-NEXT: # %bb.3: # %_return_bb
; CHECK-P10-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll b/llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll
index 03b7219f7458..f45611f18346 100644
--- a/llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll
@@ -4320,7 +4320,6 @@ define dso_local zeroext i16 @ld_align16_uint16_t_float(i8* nocapture readonly %
; CHECK-NEXT: lfs f0, 8(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -4337,7 +4336,6 @@ define dso_local zeroext i16 @ld_align32_uint16_t_float(i8* nocapture readonly %
; CHECK-P10-NEXT: plfs f0, 99999000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align32_uint16_t_float:
@@ -4347,7 +4345,6 @@ define dso_local zeroext i16 @ld_align32_uint16_t_float(i8* nocapture readonly %
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -4366,7 +4363,6 @@ define dso_local zeroext i16 @ld_align64_uint16_t_float(i8* nocapture readonly %
; CHECK-P10-NEXT: lfsx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint16_t_float:
@@ -4377,7 +4373,6 @@ define dso_local zeroext i16 @ld_align64_uint16_t_float(i8* nocapture readonly %
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -4394,7 +4389,6 @@ define dso_local zeroext i16 @ld_reg_uint16_t_float(i8* nocapture readonly %ptr,
; CHECK-NEXT: lfsx f0, r3, r4
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -4412,7 +4406,6 @@ define dso_local zeroext i16 @ld_or_uint16_t_float(i64 %ptr, i8 zeroext %off) {
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -4431,7 +4424,6 @@ define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_float(i64 %ptr) {
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -4449,7 +4441,6 @@ define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_float(i64 %ptr) {
; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -4469,7 +4460,6 @@ define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_float(i64 %ptr) {
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -4488,7 +4478,6 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_float(i64 %ptr) {
; CHECK-P10-NEXT: plfs f0, 999990000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_float:
@@ -4500,7 +4489,6 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_float(i64 %ptr) {
; CHECK-P9-NEXT: lfsx f0, r3, r4
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_float:
@@ -4512,7 +4500,6 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_float(i64 %ptr) {
; CHECK-P8-NEXT: lfsx f0, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -4534,7 +4521,6 @@ define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_float(i64 %ptr) {
; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_float:
@@ -4547,7 +4533,6 @@ define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_float(i64 %ptr) {
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -4567,7 +4552,6 @@ define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_float(i64 %ptr) {
; CHECK-P10-NEXT: lfsx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_float:
@@ -4579,7 +4563,6 @@ define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_float(i64 %ptr) {
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -4597,7 +4580,6 @@ define dso_local zeroext i16 @ld_cst_align16_uint16_t_float() {
; CHECK-NEXT: lfs f0, 4080(0)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16
@@ -4613,7 +4595,6 @@ define dso_local zeroext i16 @ld_cst_align32_uint16_t_float() {
; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4
@@ -4630,7 +4611,6 @@ define dso_local zeroext i16 @ld_cst_align64_uint16_t_float() {
; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_float:
@@ -4641,7 +4621,6 @@ define dso_local zeroext i16 @ld_cst_align64_uint16_t_float() {
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
@@ -4656,7 +4635,6 @@ define dso_local zeroext i16 @ld_0_uint16_t_double(i64 %ptr) {
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to double*
@@ -4672,7 +4650,6 @@ define dso_local zeroext i16 @ld_align16_uint16_t_double(i8* nocapture readonly
; CHECK-NEXT: lfd f0, 8(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -4689,7 +4666,6 @@ define dso_local zeroext i16 @ld_align32_uint16_t_double(i8* nocapture readonly
; CHECK-P10-NEXT: plfd f0, 99999000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align32_uint16_t_double:
@@ -4699,7 +4675,6 @@ define dso_local zeroext i16 @ld_align32_uint16_t_double(i8* nocapture readonly
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -4718,7 +4693,6 @@ define dso_local zeroext i16 @ld_align64_uint16_t_double(i8* nocapture readonly
; CHECK-P10-NEXT: lfdx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint16_t_double:
@@ -4729,7 +4703,6 @@ define dso_local zeroext i16 @ld_align64_uint16_t_double(i8* nocapture readonly
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -4746,7 +4719,6 @@ define dso_local zeroext i16 @ld_reg_uint16_t_double(i8* nocapture readonly %ptr
; CHECK-NEXT: lfdx f0, r3, r4
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -4764,7 +4736,6 @@ define dso_local zeroext i16 @ld_or_uint16_t_double(i64 %ptr, i8 zeroext %off) {
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -4783,7 +4754,6 @@ define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_double(i64 %ptr) {
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -4801,7 +4771,6 @@ define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_double(i64 %ptr) {
; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -4821,7 +4790,6 @@ define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_double(i64 %ptr) {
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -4840,7 +4808,6 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_double(i64 %ptr) {
; CHECK-P10-NEXT: plfd f0, 999990000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_double:
@@ -4852,7 +4819,6 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_double(i64 %ptr) {
; CHECK-P9-NEXT: lfdx f0, r3, r4
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_double:
@@ -4864,7 +4830,6 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_double(i64 %ptr) {
; CHECK-P8-NEXT: lfdx f0, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -4886,7 +4851,6 @@ define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_double(i64 %ptr) {
; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_double:
@@ -4899,7 +4863,6 @@ define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_double(i64 %ptr) {
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -4919,7 +4882,6 @@ define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_double(i64 %ptr) {
; CHECK-P10-NEXT: lfdx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_double:
@@ -4931,7 +4893,6 @@ define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_double(i64 %ptr) {
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -4949,7 +4910,6 @@ define dso_local zeroext i16 @ld_cst_align16_uint16_t_double() {
; CHECK-NEXT: lfd f0, 4080(0)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16
@@ -4965,7 +4925,6 @@ define dso_local zeroext i16 @ld_cst_align32_uint16_t_double() {
; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8
@@ -4982,7 +4941,6 @@ define dso_local zeroext i16 @ld_cst_align64_uint16_t_double() {
; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_double:
@@ -4993,7 +4951,6 @@ define dso_local zeroext i16 @ld_cst_align64_uint16_t_double() {
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
diff --git a/llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll b/llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll
index a13152e8c7ea..82d5b6f7278d 100644
--- a/llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll
@@ -4368,7 +4368,6 @@ define dso_local zeroext i32 @ld_0_uint32_t_float(i64 %ptr) {
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to float*
@@ -4384,7 +4383,6 @@ define dso_local zeroext i32 @ld_align16_uint32_t_float(i8* nocapture readonly %
; CHECK-NEXT: lfs f0, 8(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -4401,7 +4399,6 @@ define dso_local zeroext i32 @ld_align32_uint32_t_float(i8* nocapture readonly %
; CHECK-P10-NEXT: plfs f0, 99999000(r3), 0
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align32_uint32_t_float:
@@ -4411,7 +4408,6 @@ define dso_local zeroext i32 @ld_align32_uint32_t_float(i8* nocapture readonly %
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -4430,7 +4426,6 @@ define dso_local zeroext i32 @ld_align64_uint32_t_float(i8* nocapture readonly %
; CHECK-P10-NEXT: lfsx f0, r3, r4
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint32_t_float:
@@ -4441,7 +4436,6 @@ define dso_local zeroext i32 @ld_align64_uint32_t_float(i8* nocapture readonly %
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -4458,7 +4452,6 @@ define dso_local zeroext i32 @ld_reg_uint32_t_float(i8* nocapture readonly %ptr,
; CHECK-NEXT: lfsx f0, r3, r4
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -4476,7 +4469,6 @@ define dso_local zeroext i32 @ld_or_uint32_t_float(i64 %ptr, i8 zeroext %off) {
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -4495,7 +4487,6 @@ define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_float(i64 %ptr) {
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -4513,7 +4504,6 @@ define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_float(i64 %ptr) {
; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -4533,7 +4523,6 @@ define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_float(i64 %ptr) {
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -4552,7 +4541,6 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_float(i64 %ptr) {
; CHECK-P10-NEXT: plfs f0, 999990000(r3), 0
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_float:
@@ -4564,7 +4552,6 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_float(i64 %ptr) {
; CHECK-P9-NEXT: lfsx f0, r3, r4
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_float:
@@ -4576,7 +4563,6 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_float(i64 %ptr) {
; CHECK-P8-NEXT: lfsx f0, r3, r4
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -4598,7 +4584,6 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_float(i64 %ptr) {
; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_float:
@@ -4611,7 +4596,6 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_float(i64 %ptr) {
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -4631,7 +4615,6 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_float(i64 %ptr) {
; CHECK-P10-NEXT: lfsx f0, r3, r4
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_float:
@@ -4643,7 +4626,6 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_float(i64 %ptr) {
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -4661,7 +4643,6 @@ define dso_local zeroext i32 @ld_cst_align16_uint32_t_float() {
; CHECK-NEXT: lfs f0, 4080(0)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16
@@ -4677,7 +4658,6 @@ define dso_local zeroext i32 @ld_cst_align32_uint32_t_float() {
; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4
@@ -4694,7 +4674,6 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_float() {
; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_float:
@@ -4705,7 +4684,6 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_float() {
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
@@ -4720,7 +4698,6 @@ define dso_local zeroext i32 @ld_0_uint32_t_double(i64 %ptr) {
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to double*
@@ -4736,7 +4713,6 @@ define dso_local zeroext i32 @ld_align16_uint32_t_double(i8* nocapture readonly
; CHECK-NEXT: lfd f0, 8(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -4753,7 +4729,6 @@ define dso_local zeroext i32 @ld_align32_uint32_t_double(i8* nocapture readonly
; CHECK-P10-NEXT: plfd f0, 99999000(r3), 0
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align32_uint32_t_double:
@@ -4763,7 +4738,6 @@ define dso_local zeroext i32 @ld_align32_uint32_t_double(i8* nocapture readonly
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -4782,7 +4756,6 @@ define dso_local zeroext i32 @ld_align64_uint32_t_double(i8* nocapture readonly
; CHECK-P10-NEXT: lfdx f0, r3, r4
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint32_t_double:
@@ -4793,7 +4766,6 @@ define dso_local zeroext i32 @ld_align64_uint32_t_double(i8* nocapture readonly
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -4810,7 +4782,6 @@ define dso_local zeroext i32 @ld_reg_uint32_t_double(i8* nocapture readonly %ptr
; CHECK-NEXT: lfdx f0, r3, r4
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -4828,7 +4799,6 @@ define dso_local zeroext i32 @ld_or_uint32_t_double(i64 %ptr, i8 zeroext %off) {
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -4847,7 +4817,6 @@ define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_double(i64 %ptr) {
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -4865,7 +4834,6 @@ define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_double(i64 %ptr) {
; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -4885,7 +4853,6 @@ define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_double(i64 %ptr) {
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -4904,7 +4871,6 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_double(i64 %ptr) {
; CHECK-P10-NEXT: plfd f0, 999990000(r3), 0
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_double:
@@ -4916,7 +4882,6 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_double(i64 %ptr) {
; CHECK-P9-NEXT: lfdx f0, r3, r4
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_double:
@@ -4928,7 +4893,6 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_double(i64 %ptr) {
; CHECK-P8-NEXT: lfdx f0, r3, r4
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -4950,7 +4914,6 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_double(i64 %ptr) {
; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_double:
@@ -4963,7 +4926,6 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_double(i64 %ptr) {
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -4983,7 +4945,6 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_double(i64 %ptr) {
; CHECK-P10-NEXT: lfdx f0, r3, r4
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_double:
@@ -4995,7 +4956,6 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_double(i64 %ptr) {
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -5013,7 +4973,6 @@ define dso_local zeroext i32 @ld_cst_align16_uint32_t_double() {
; CHECK-NEXT: lfd f0, 4080(0)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16
@@ -5029,7 +4988,6 @@ define dso_local zeroext i32 @ld_cst_align32_uint32_t_double() {
; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8
@@ -5046,7 +5004,6 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_double() {
; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_double:
@@ -5057,7 +5014,6 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_double() {
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
diff --git a/llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll b/llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll
index 333718e402bf..e1dbad0dcc8d 100644
--- a/llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll
@@ -5290,7 +5290,6 @@ define dso_local zeroext i8 @ld_0_uint8_t_float(i64 %ptr) {
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to float*
@@ -5306,7 +5305,6 @@ define dso_local zeroext i8 @ld_align16_uint8_t_float(i8* nocapture readonly %pt
; CHECK-NEXT: lfs f0, 8(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -5323,7 +5321,6 @@ define dso_local zeroext i8 @ld_align32_uint8_t_float(i8* nocapture readonly %pt
; CHECK-P10-NEXT: plfs f0, 99999000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align32_uint8_t_float:
@@ -5333,7 +5330,6 @@ define dso_local zeroext i8 @ld_align32_uint8_t_float(i8* nocapture readonly %pt
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -5353,7 +5349,6 @@ define dso_local zeroext i8 @ld_unalign64_uint8_t_float(i8* nocapture readonly %
; CHECK-P10-NEXT: lfsx f0, r3, r5
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_unalign64_uint8_t_float:
@@ -5365,7 +5360,6 @@ define dso_local zeroext i8 @ld_unalign64_uint8_t_float(i8* nocapture readonly %
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000001
@@ -5384,7 +5378,6 @@ define dso_local zeroext i8 @ld_align64_uint8_t_float(i8* nocapture readonly %pt
; CHECK-P10-NEXT: lfsx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint8_t_float:
@@ -5395,7 +5388,6 @@ define dso_local zeroext i8 @ld_align64_uint8_t_float(i8* nocapture readonly %pt
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -5412,7 +5404,6 @@ define dso_local zeroext i8 @ld_reg_uint8_t_float(i8* nocapture readonly %ptr, i
; CHECK-NEXT: lfsx f0, r3, r4
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -5430,7 +5421,6 @@ define dso_local zeroext i8 @ld_or_uint8_t_float(i64 %ptr, i8 zeroext %off) {
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -5449,7 +5439,6 @@ define dso_local zeroext i8 @ld_not_disjoint16_uint8_t_float(i64 %ptr) {
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -5467,7 +5456,6 @@ define dso_local zeroext i8 @ld_disjoint_align16_uint8_t_float(i64 %ptr) {
; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -5487,7 +5475,6 @@ define dso_local zeroext i8 @ld_not_disjoint32_uint8_t_float(i64 %ptr) {
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -5506,7 +5493,6 @@ define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_float(i64 %ptr) {
; CHECK-P10-NEXT: plfs f0, 999990000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_float:
@@ -5518,7 +5504,6 @@ define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_float(i64 %ptr) {
; CHECK-P9-NEXT: lfsx f0, r3, r4
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_float:
@@ -5530,7 +5515,6 @@ define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_float(i64 %ptr) {
; CHECK-P8-NEXT: lfsx f0, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -5552,7 +5536,6 @@ define dso_local zeroext i8 @ld_not_disjoint64_uint8_t_float(i64 %ptr) {
; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_float:
@@ -5565,7 +5548,6 @@ define dso_local zeroext i8 @ld_not_disjoint64_uint8_t_float(i64 %ptr) {
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -5586,7 +5568,6 @@ define dso_local zeroext i8 @ld_disjoint_unalign64_uint8_t_float(i64 %ptr) {
; CHECK-P10-NEXT: lfsx f0, r3, r5
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_unalign64_uint8_t_float:
@@ -5599,7 +5580,6 @@ define dso_local zeroext i8 @ld_disjoint_unalign64_uint8_t_float(i64 %ptr) {
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -5620,7 +5600,6 @@ define dso_local zeroext i8 @ld_disjoint_align64_uint8_t_float(i64 %ptr) {
; CHECK-P10-NEXT: lfsx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_float:
@@ -5632,7 +5611,6 @@ define dso_local zeroext i8 @ld_disjoint_align64_uint8_t_float(i64 %ptr) {
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -5650,7 +5628,6 @@ define dso_local zeroext i8 @ld_cst_align16_uint8_t_float() {
; CHECK-NEXT: lfs f0, 4080(0)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16
@@ -5666,7 +5643,6 @@ define dso_local zeroext i8 @ld_cst_align32_uint8_t_float() {
; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4
@@ -5684,7 +5660,6 @@ define dso_local zeroext i8 @ld_cst_unalign64_uint8_t_float() {
; CHECK-P10-NEXT: lfs f0, 0(r4)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_unalign64_uint8_t_float:
@@ -5696,7 +5671,6 @@ define dso_local zeroext i8 @ld_cst_unalign64_uint8_t_float() {
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 1000000000001 to float*), align 4
@@ -5713,7 +5687,6 @@ define dso_local zeroext i8 @ld_cst_align64_uint8_t_float() {
; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_float:
@@ -5724,7 +5697,6 @@ define dso_local zeroext i8 @ld_cst_align64_uint8_t_float() {
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
@@ -5739,7 +5711,6 @@ define dso_local zeroext i8 @ld_0_uint8_t_double(i64 %ptr) {
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to double*
@@ -5755,7 +5726,6 @@ define dso_local zeroext i8 @ld_align16_uint8_t_double(i8* nocapture readonly %p
; CHECK-NEXT: lfd f0, 8(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -5772,7 +5742,6 @@ define dso_local zeroext i8 @ld_align32_uint8_t_double(i8* nocapture readonly %p
; CHECK-P10-NEXT: plfd f0, 99999000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align32_uint8_t_double:
@@ -5782,7 +5751,6 @@ define dso_local zeroext i8 @ld_align32_uint8_t_double(i8* nocapture readonly %p
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -5802,7 +5770,6 @@ define dso_local zeroext i8 @ld_unalign64_uint8_t_double(i8* nocapture readonly
; CHECK-P10-NEXT: lfdx f0, r3, r5
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_unalign64_uint8_t_double:
@@ -5814,7 +5781,6 @@ define dso_local zeroext i8 @ld_unalign64_uint8_t_double(i8* nocapture readonly
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000001
@@ -5833,7 +5799,6 @@ define dso_local zeroext i8 @ld_align64_uint8_t_double(i8* nocapture readonly %p
; CHECK-P10-NEXT: lfdx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint8_t_double:
@@ -5844,7 +5809,6 @@ define dso_local zeroext i8 @ld_align64_uint8_t_double(i8* nocapture readonly %p
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -5861,7 +5825,6 @@ define dso_local zeroext i8 @ld_reg_uint8_t_double(i8* nocapture readonly %ptr,
; CHECK-NEXT: lfdx f0, r3, r4
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -5879,7 +5842,6 @@ define dso_local zeroext i8 @ld_or_uint8_t_double(i64 %ptr, i8 zeroext %off) {
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
@@ -5898,7 +5860,6 @@ define dso_local zeroext i8 @ld_not_disjoint16_uint8_t_double(i64 %ptr) {
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
@@ -5916,7 +5877,6 @@ define dso_local zeroext i8 @ld_disjoint_align16_uint8_t_double(i64 %ptr) {
; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
@@ -5936,7 +5896,6 @@ define dso_local zeroext i8 @ld_not_disjoint32_uint8_t_double(i64 %ptr) {
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
@@ -5955,7 +5914,6 @@ define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_double(i64 %ptr) {
; CHECK-P10-NEXT: plfd f0, 999990000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_double:
@@ -5967,7 +5925,6 @@ define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_double(i64 %ptr) {
; CHECK-P9-NEXT: lfdx f0, r3, r4
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_double:
@@ -5979,7 +5936,6 @@ define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_double(i64 %ptr) {
; CHECK-P8-NEXT: lfdx f0, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
@@ -6001,7 +5957,6 @@ define dso_local zeroext i8 @ld_not_disjoint64_uint8_t_double(i64 %ptr) {
; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_double:
@@ -6014,7 +5969,6 @@ define dso_local zeroext i8 @ld_not_disjoint64_uint8_t_double(i64 %ptr) {
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
@@ -6035,7 +5989,6 @@ define dso_local zeroext i8 @ld_disjoint_unalign64_uint8_t_double(i64 %ptr) {
; CHECK-P10-NEXT: lfdx f0, r3, r5
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_unalign64_uint8_t_double:
@@ -6048,7 +6001,6 @@ define dso_local zeroext i8 @ld_disjoint_unalign64_uint8_t_double(i64 %ptr) {
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -6069,7 +6021,6 @@ define dso_local zeroext i8 @ld_disjoint_align64_uint8_t_double(i64 %ptr) {
; CHECK-P10-NEXT: lfdx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_double:
@@ -6081,7 +6032,6 @@ define dso_local zeroext i8 @ld_disjoint_align64_uint8_t_double(i64 %ptr) {
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
@@ -6099,7 +6049,6 @@ define dso_local zeroext i8 @ld_cst_align16_uint8_t_double() {
; CHECK-NEXT: lfd f0, 4080(0)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16
@@ -6115,7 +6064,6 @@ define dso_local zeroext i8 @ld_cst_align32_uint8_t_double() {
; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8
@@ -6133,7 +6081,6 @@ define dso_local zeroext i8 @ld_cst_unalign64_uint8_t_double() {
; CHECK-P10-NEXT: lfd f0, 0(r4)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_unalign64_uint8_t_double:
@@ -6145,7 +6092,6 @@ define dso_local zeroext i8 @ld_cst_unalign64_uint8_t_double() {
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 1000000000001 to double*), align 8
@@ -6162,7 +6108,6 @@ define dso_local zeroext i8 @ld_cst_align64_uint8_t_double() {
; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_double:
@@ -6173,7 +6118,6 @@ define dso_local zeroext i8 @ld_cst_align64_uint8_t_double() {
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
diff --git a/llvm/test/CodeGen/PowerPC/select-constant-xor.ll b/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
index 0f77ca6a58d2..10418e805999 100644
--- a/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
@@ -42,7 +42,6 @@ define i64 @selecti32i64(i32 %a) {
; CHECK-LABEL: selecti32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: srawi 3, 3, 31
-; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: xori 3, 3, 65535
; CHECK-NEXT: xoris 3, 3, 32767
; CHECK-NEXT: blr
@@ -69,7 +68,6 @@ define i32 @selecti32i32(i32 %a) {
; CHECK-LABEL: selecti32i32:
; CHECK: # %bb.0:
; CHECK-NEXT: srawi 3, 3, 31
-; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: xori 3, 3, 84
; CHECK-NEXT: blr
%c = icmp sgt i32 %a, -1
@@ -81,7 +79,6 @@ define i8 @selecti32i8(i32 %a) {
; CHECK-LABEL: selecti32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: srawi 3, 3, 31
-; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: xori 3, 3, 84
; CHECK-NEXT: blr
%c = icmp sgt i32 %a, -1
@@ -94,7 +91,6 @@ define i32 @selecti8i32(i8 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: extsb 3, 3
; CHECK-NEXT: srawi 3, 3, 7
-; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: xori 3, 3, 84
; CHECK-NEXT: blr
%c = icmp sgt i8 %a, -1
diff --git a/llvm/test/CodeGen/PowerPC/sext_elimination.mir b/llvm/test/CodeGen/PowerPC/sext_elimination.mir
new file mode 100644
index 000000000000..93feb9cb2e9e
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/sext_elimination.mir
@@ -0,0 +1,67 @@
+# RUN: llc -run-pass ppc-mi-peepholes -ppc-eliminate-signext -ppc-eliminate-zeroext -verify-machineinstrs -o - %s | FileCheck %s
+
+--- |
+ target datalayout = "E-m:e-i64:64-n32:64"
+ target triple = "powerpc64le-unknown-linux-gnu"
+ define i8* @func(i8* %a) {
+ entry:
+ ret i8* %a
+ }
+
+...
+---
+name: func
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+liveins:
+ - { reg: '$x3', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+body: |
+ bb.0.entry:
+ liveins: $x3
+
+ ; CHECK-LABEL: bb.0.entry:
+ ; CHECK: %4:g8rc = EXTSW_32_64 %3
+ ; CHECK: %5:g8rc = INSERT_SUBREG %15, %1, %subreg.sub_32
+ ; CHECK: %7:g8rc = EXTSW_32_64 %6
+ ; CHECK: %9:g8rc = INSERT_SUBREG %16, %8, %subreg.sub_32
+ ; CHECK: %11:g8rc = INSERT_SUBREG %17, %10, %subreg.sub_32
+ ; CHECK: %14:g8rc = COPY %1
+
+ %0:g8rc_nox0 = COPY $x3
+ %1:gprc, %2:g8rc_nox0 = LBZU 0, %0:g8rc_nox0
+ %3:gprc = COPY %2:g8rc_nox0
+ %4:g8rc = EXTSW_32_64 %3:gprc ; should not be eliminated
+ %5:g8rc = EXTSW_32_64 %1:gprc
+
+ %6:gprc = ORIS %1:gprc, 32768 ; should not be eliminated
+ %7:g8rc = EXTSW_32_64 %6:gprc
+
+ %8:gprc = ORIS %1:gprc, 32767
+ %9:g8rc = EXTSW_32_64 %8:gprc
+
+ %10:gprc = ORI %1:gprc, 32768
+ %11:g8rc = EXTSW_32_64 %10:gprc
+
+ %12:g8rc = IMPLICIT_DEF
+ %13:g8rc = INSERT_SUBREG %12:g8rc, %1:gprc, %subreg.sub_32
+ %14:g8rc = RLDICL %13:g8rc, 0, 32
+
+...
diff --git a/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll b/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll
index 7716dc0cedcc..7afe07142463 100644
--- a/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll
+++ b/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll
@@ -70,21 +70,20 @@ top:
define i16 @noSEXTLoad(i16 *%p) #0 {
; CHECK-LABEL: noSEXTLoad:
; CHECK: # %bb.0: # %top
-; CHECK-NEXT: lhz 5, 0(3)
+; CHECK-NEXT: lha 3, 0(3)
; CHECK-NEXT: li 4, 0
-; CHECK-NEXT: addi 3, 1, -4
; CHECK-NEXT: sth 4, -4(1)
-; CHECK-NEXT: extsh 4, 5
+; CHECK-NEXT: addi 4, 1, -4
; CHECK-NEXT: lwsync
; CHECK-NEXT: .LBB2_1: # %top
; CHECK-NEXT: #
-; CHECK-NEXT: lharx 5, 0, 3
+; CHECK-NEXT: lharx 5, 0, 4
; CHECK-NEXT: extsh 5, 5
-; CHECK-NEXT: cmpw 4, 5
+; CHECK-NEXT: cmpw 3, 5
; CHECK-NEXT: bge 0, .LBB2_3
; CHECK-NEXT: # %bb.2: # %top
; CHECK-NEXT: #
-; CHECK-NEXT: sthcx. 4, 0, 3
+; CHECK-NEXT: sthcx. 3, 0, 4
; CHECK-NEXT: bne 0, .LBB2_1
; CHECK-NEXT: .LBB2_3: # %top
; CHECK-NEXT: lwsync
diff --git a/llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll b/llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll
index 9928a111734b..50dcffc235dd 100644
--- a/llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll
+++ b/llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll
@@ -39,7 +39,7 @@ define dso_local signext i32 @main(i32 signext %argc, i8** nocapture readnone %a
; CHECK-NEXT: nop
; CHECK-NEXT: # kill: def $r3 killed $r3 killed $x3
; CHECK-NEXT: .LBB0_3: # %return
-; CHECK-NEXT: extsw 3, 3
+; CHECK-NEXT: # kill: def $r3 killed $r3 def $x3
; CHECK-NEXT: addi 1, 31, 784
; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: lwz 12, 8(1)
@@ -88,7 +88,7 @@ define dso_local signext i32 @main(i32 signext %argc, i8** nocapture readnone %a
; BE-NEXT: nop
; BE-NEXT: # kill: def $r3 killed $r3 killed $x3
; BE-NEXT: .LBB0_3: # %return
-; BE-NEXT: extsw 3, 3
+; BE-NEXT: # kill: def $r3 killed $r3 def $x3
; BE-NEXT: addi 1, 31, 800
; BE-NEXT: ld 0, 16(1)
; BE-NEXT: lwz 12, 8(1)
diff --git a/llvm/test/CodeGen/PowerPC/store-forward-be64.ll b/llvm/test/CodeGen/PowerPC/store-forward-be64.ll
index 016b8a464f53..e798f5c85acc 100644
--- a/llvm/test/CodeGen/PowerPC/store-forward-be64.ll
+++ b/llvm/test/CodeGen/PowerPC/store-forward-be64.ll
@@ -150,7 +150,6 @@ define signext i32 @tc43(%struct.ST* noundef byval(%struct.ST) align 8 %s) {
; CHECK-NEXT: std 3, 48(1)
; CHECK-NEXT: lwz 3, 48(1)
; CHECK-NEXT: srawi 3, 3, 8
-; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: blr
entry:
%a = getelementptr inbounds %struct.ST, %struct.ST* %s, i32 0, i32 0
diff --git a/llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll b/llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
index 18e47f131dd6..fbc094bcf516 100644
--- a/llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
+++ b/llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
@@ -16,29 +16,29 @@ define dso_local void @test(void (i32)* nocapture %fp, i32 signext %Arg, i32 sig
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -64(r1)
; CHECK-NEXT: mr r29, r5
-; CHECK-NEXT: mr r30, r3
-; CHECK-NEXT: extsw r28, r4
+; CHECK-NEXT: mr r30, r4
+; CHECK-NEXT: mr r28, r3
; CHECK-NEXT: std r2, 24(r1)
; CHECK-NEXT: cmpwi r29, 1
; CHECK-NEXT: bc 12, lt, .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: cmpwi r4, 11
+; CHECK-NEXT: cmpwi r30, 11
; CHECK-NEXT: bc 12, lt, .LBB0_3
; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_2: # %for.body.us
; CHECK-NEXT: #
-; CHECK-NEXT: mtctr r30
-; CHECK-NEXT: mr r3, r28
-; CHECK-NEXT: mr r12, r30
+; CHECK-NEXT: mtctr r28
+; CHECK-NEXT: mr r3, r30
+; CHECK-NEXT: mr r12, r28
; CHECK-NEXT: bctrl
; CHECK-NEXT: ld 2, 24(r1)
; CHECK-NEXT: addi r29, r29, -1
; CHECK-NEXT: cmplwi r29, 0
; CHECK-NEXT: bne cr0, .LBB0_2
; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup
-; CHECK-NEXT: mtctr r30
-; CHECK-NEXT: mr r3, r28
-; CHECK-NEXT: mr r12, r30
+; CHECK-NEXT: mtctr r28
+; CHECK-NEXT: mr r3, r30
+; CHECK-NEXT: mr r12, r28
; CHECK-NEXT: bctrl
; CHECK-NEXT: ld 2, 24(r1)
; CHECK-NEXT: addi r1, r1, 64
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