[PATCH] D130993: [AArch64][SVE] Extend LD1RQ ISel patterns to cover missing addressing modes

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:2229-2245
   def : Pat<(nxv16i8 (AArch64ld1rq_z PPR:$gp, GPR64:$base)),
             (LD1RQ_B_IMM $gp, $base, (i64 0))>;
   def : Pat<(nxv8i16 (AArch64ld1rq_z PPR:$gp, GPR64:$base)),
             (LD1RQ_H_IMM $gp, $base, (i64 0))>;
   def : Pat<(nxv4i32 (AArch64ld1rq_z PPR:$gp, GPR64:$base)),
             (LD1RQ_W_IMM $gp, $base, (i64 0))>;
   def : Pat<(nxv2i64 (AArch64ld1rq_z PPR:$gp, GPR64:$base)),
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Can these be moved into `LD1RQPat` to mirror the three forms use by `sve_ld1rq_pat`.

I guess there's also a shout for all the patterns to exist within a single multiclass given they're related but that's up to you.


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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll:20-21
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ld1rqb { z0.b }, p0/z, [x0, #16]
+; CHECK-NEXT:    mov w8, #16
+; CHECK-NEXT:    ld1rqb { z0.b }, p0/z, [x0, x8]
 ; CHECK-NEXT:    ret
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You shouldn't be regressing existing code.  You likely need to wrap the immediate variants with `AddedComplexity`, see `pred_load` so the immediate forms are matched first then the register ones only match when necessary. 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D130993/new/

https://reviews.llvm.org/D130993