[PATCH] D132042: [IR] Update llvm.prefetch to match docs

[Sam Elliott via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3a729069e463: [IR] Update llvm.prefetch to match docs (authored by lenary).
Herald added subscribers: bzcheeseman, awarzynski, sdasgup3, wenzhicui, wrengr, cota, teijeong, rdzhabarov, tatianashp, msifontes, jurahul, Kayjukh, grosul1, Joonsoo, stephenneuendorffer, liufengdb, aartbik, mgester, arpith-jacob, nicolasvasilache, antiagainst, shauheen, rriddle, mehdi_amini.
Herald added a reviewer: ftynse.
Herald added a reviewer: dcaballe.
Herald added a project: MLIR.

Changed prior to commit:
  https://reviews.llvm.org/D132042?vs=453343&id=453913#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132042/new/

https://reviews.llvm.org/D132042

Files:
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/IR/Verifier.cpp
  llvm/test/Assembler/auto_upgrade_intrinsics.ll
  llvm/test/CodeGen/RISCV/prefetch.ll
  mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir


Index: mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
===================================================================
--- mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
+++ mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
@@ -712,7 +712,7 @@
 // CHECK-DAG: declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>) #0
 // CHECK-DAG: declare float @llvm.fmuladd.f32(float, float, float)
 // CHECK-DAG: declare <8 x float> @llvm.fmuladd.v8f32(<8 x float>, <8 x float>, <8 x float>) #0
-// CHECK-DAG: declare void @llvm.prefetch.p0(ptr nocapture readonly, i32 immarg, i32 immarg, i32)
+// CHECK-DAG: declare void @llvm.prefetch.p0(ptr nocapture readonly, i32 immarg, i32 immarg, i32 immarg)
 // CHECK-DAG: declare float @llvm.exp.f32(float)
 // CHECK-DAG: declare <8 x float> @llvm.exp.v8f32(<8 x float>) #0
 // CHECK-DAG: declare float @llvm.log.f32(float)
Index: llvm/test/CodeGen/RISCV/prefetch.ll
===================================================================
--- llvm/test/CodeGen/RISCV/prefetch.ll
+++ llvm/test/CodeGen/RISCV/prefetch.ll
@@ -14,6 +14,6 @@
 ; RV64I-LABEL: test_prefetch:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    ret
-  call void @llvm.prefetch(i8* %a, i32 0, i32 1, i32 2)
+  call void @llvm.prefetch(i8* %a, i32 0, i32 2, i32 1)
   ret void
 }
Index: llvm/test/Assembler/auto_upgrade_intrinsics.ll
===================================================================
--- llvm/test/Assembler/auto_upgrade_intrinsics.ll
+++ llvm/test/Assembler/auto_upgrade_intrinsics.ll
@@ -189,24 +189,24 @@
 declare void @llvm.prefetch(i8*, i32, i32, i32)
 define void @test.prefetch(i8* %ptr) {
 ; CHECK-LABEL: @test.prefetch(
-; CHECK: @llvm.prefetch.p0i8(i8* %ptr, i32 0, i32 3, i32 2)
-  call void @llvm.prefetch(i8* %ptr, i32 0, i32 3, i32 2)
+; CHECK: @llvm.prefetch.p0i8(i8* %ptr, i32 0, i32 3, i32 1)
+  call void @llvm.prefetch(i8* %ptr, i32 0, i32 3, i32 1)
   ret void
 }
 
 declare void @llvm.prefetch.p0i8(i8*, i32, i32, i32)
 define void @test.prefetch.2(i8* %ptr) {
 ; CHECK-LABEL: @test.prefetch.2(
-; CHECK: @llvm.prefetch.p0i8(i8* %ptr, i32 0, i32 3, i32 2)
-  call void @llvm.prefetch(i8* %ptr, i32 0, i32 3, i32 2)
+; CHECK: @llvm.prefetch.p0i8(i8* %ptr, i32 0, i32 3, i32 1)
+  call void @llvm.prefetch(i8* %ptr, i32 0, i32 3, i32 1)
   ret void
 }
 
 declare void @llvm.prefetch.unnamed(%0**, i32, i32, i32)
 define void @test.prefetch.unnamed(%0** %ptr) {
 ; CHECK-LABEL: @test.prefetch.unnamed(
-; CHECK: @llvm.prefetch.p0p0s_s.0(%0** %ptr, i32 0, i32 3, i32 2)
-  call void @llvm.prefetch.unnamed(%0** %ptr, i32 0, i32 3, i32 2)
+; CHECK: @llvm.prefetch.p0p0s_s.0(%0** %ptr, i32 0, i32 3, i32 1)
+  call void @llvm.prefetch.unnamed(%0** %ptr, i32 0, i32 3, i32 1)
   ret void
 }
 
Index: llvm/lib/IR/Verifier.cpp
===================================================================
--- llvm/lib/IR/Verifier.cpp
+++ llvm/lib/IR/Verifier.cpp
@@ -5121,9 +5121,12 @@
           Call);
     break;
   case Intrinsic::prefetch:
-    Check(cast<ConstantInt>(Call.getArgOperand(1))->getZExtValue() < 2 &&
-              cast<ConstantInt>(Call.getArgOperand(2))->getZExtValue() < 4,
-          "invalid arguments to llvm.prefetch", Call);
+    Check(cast<ConstantInt>(Call.getArgOperand(1))->getZExtValue() < 2,
+          "rw argument to llvm.prefetch must be 0-1", Call);
+    Check(cast<ConstantInt>(Call.getArgOperand(2))->getZExtValue() < 4,
+          "locality argument to llvm.prefetch must be 0-4", Call);
+    Check(cast<ConstantInt>(Call.getArgOperand(3))->getZExtValue() < 2,
+          "cache type argument to llvm.prefetch must be 0-1", Call);
     break;
   case Intrinsic::stackprotector:
     Check(isa<AllocaInst>(Call.getArgOperand(1)->stripPointerCasts()),
Index: llvm/include/llvm/IR/Intrinsics.td
===================================================================
--- llvm/include/llvm/IR/Intrinsics.td
+++ llvm/include/llvm/IR/Intrinsics.td
@@ -567,7 +567,7 @@
     : DefaultAttrsIntrinsic<[], [ llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty ],
                 [IntrInaccessibleMemOrArgMemOnly, IntrWillReturn,
                  ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
-                 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
+                 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
 def int_pcmarker      : DefaultAttrsIntrinsic<[], [llvm_i32_ty]>;
 
 def int_readcyclecounter : DefaultAttrsIntrinsic<[llvm_i64_ty]>;


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