[PATCH] D132211: Optimize x > 1 ? x : 1 -> x > 0 ? x : 1

[Liao Chunyu via Phabricator via llvm-commits]

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if x == 1,

  x > 1 ? x : 1  return x, which is also 1.
  x > 0 ? x : 1  return 1.

Reduce the number of load 1 instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D132211

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/forced-atomics.ll


Index: llvm/test/CodeGen/RISCV/forced-atomics.ll
===================================================================
--- llvm/test/CodeGen/RISCV/forced-atomics.ll
+++ llvm/test/CodeGen/RISCV/forced-atomics.ll
@@ -995,9 +995,8 @@
 ; RV32-NO-ATOMIC-NEXT:    bnez a0, .LBB23_4
 ; RV32-NO-ATOMIC-NEXT:  .LBB23_2: # %atomicrmw.start
 ; RV32-NO-ATOMIC-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32-NO-ATOMIC-NEXT:    li a0, 1
 ; RV32-NO-ATOMIC-NEXT:    mv a2, a1
-; RV32-NO-ATOMIC-NEXT:    blt a0, a1, .LBB23_1
+; RV32-NO-ATOMIC-NEXT:    bgtz a1, .LBB23_1
 ; RV32-NO-ATOMIC-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32-NO-ATOMIC-NEXT:    # in Loop: Header=BB23_2 Depth=1
 ; RV32-NO-ATOMIC-NEXT:    li a2, 1
@@ -1039,9 +1038,8 @@
 ; RV64-NO-ATOMIC-NEXT:    bnez a0, .LBB23_4
 ; RV64-NO-ATOMIC-NEXT:  .LBB23_2: # %atomicrmw.start
 ; RV64-NO-ATOMIC-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64-NO-ATOMIC-NEXT:    li a0, 1
 ; RV64-NO-ATOMIC-NEXT:    mv a2, a1
-; RV64-NO-ATOMIC-NEXT:    blt a0, a1, .LBB23_1
+; RV64-NO-ATOMIC-NEXT:    bgtz a1, .LBB23_1
 ; RV64-NO-ATOMIC-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64-NO-ATOMIC-NEXT:    # in Loop: Header=BB23_2 Depth=1
 ; RV64-NO-ATOMIC-NEXT:    li a2, 1
@@ -1183,9 +1181,8 @@
 ; RV32-NO-ATOMIC-NEXT:    bnez a0, .LBB25_4
 ; RV32-NO-ATOMIC-NEXT:  .LBB25_2: # %atomicrmw.start
 ; RV32-NO-ATOMIC-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32-NO-ATOMIC-NEXT:    li a0, 1
 ; RV32-NO-ATOMIC-NEXT:    mv a2, a1
-; RV32-NO-ATOMIC-NEXT:    bltu a0, a1, .LBB25_1
+; RV32-NO-ATOMIC-NEXT:    bltu zero, a1, .LBB25_1
 ; RV32-NO-ATOMIC-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32-NO-ATOMIC-NEXT:    # in Loop: Header=BB25_2 Depth=1
 ; RV32-NO-ATOMIC-NEXT:    li a2, 1
@@ -1227,9 +1224,8 @@
 ; RV64-NO-ATOMIC-NEXT:    bnez a0, .LBB25_4
 ; RV64-NO-ATOMIC-NEXT:  .LBB25_2: # %atomicrmw.start
 ; RV64-NO-ATOMIC-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64-NO-ATOMIC-NEXT:    li a0, 1
 ; RV64-NO-ATOMIC-NEXT:    mv a2, a1
-; RV64-NO-ATOMIC-NEXT:    bltu a0, a1, .LBB25_1
+; RV64-NO-ATOMIC-NEXT:    bltu zero, a1, .LBB25_1
 ; RV64-NO-ATOMIC-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64-NO-ATOMIC-NEXT:    # in Loop: Header=BB25_2 Depth=1
 ; RV64-NO-ATOMIC-NEXT:    li a2, 1
@@ -2563,9 +2559,8 @@
 ; RV64-NO-ATOMIC-NEXT:    bnez a0, .LBB49_4
 ; RV64-NO-ATOMIC-NEXT:  .LBB49_2: # %atomicrmw.start
 ; RV64-NO-ATOMIC-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64-NO-ATOMIC-NEXT:    li a0, 1
 ; RV64-NO-ATOMIC-NEXT:    mv a2, a1
-; RV64-NO-ATOMIC-NEXT:    blt a0, a1, .LBB49_1
+; RV64-NO-ATOMIC-NEXT:    bgtz a1, .LBB49_1
 ; RV64-NO-ATOMIC-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64-NO-ATOMIC-NEXT:    # in Loop: Header=BB49_2 Depth=1
 ; RV64-NO-ATOMIC-NEXT:    li a2, 1
@@ -2756,9 +2751,8 @@
 ; RV64-NO-ATOMIC-NEXT:    bnez a0, .LBB51_4
 ; RV64-NO-ATOMIC-NEXT:  .LBB51_2: # %atomicrmw.start
 ; RV64-NO-ATOMIC-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64-NO-ATOMIC-NEXT:    li a0, 1
 ; RV64-NO-ATOMIC-NEXT:    mv a2, a1
-; RV64-NO-ATOMIC-NEXT:    bltu a0, a1, .LBB51_1
+; RV64-NO-ATOMIC-NEXT:    bltu zero, a1, .LBB51_1
 ; RV64-NO-ATOMIC-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64-NO-ATOMIC-NEXT:    # in Loop: Header=BB51_2 Depth=1
 ; RV64-NO-ATOMIC-NEXT:    li a2, 1
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4019,6 +4019,13 @@
     }
 
     translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG);
+    auto *RCst = dyn_cast<ConstantSDNode>(RHS);
+    // x > 1 ? x : 1 -> x > 0 ? x : 1
+    if (isOneConstant(LHS) && !RCst &&
+        (CCVal == ISD::SETLT || CCVal == ISD::SETULT) &&
+        isOneConstant(FalseV)) {
+      LHS = DAG.getConstant(0, DL, VT);
+    }
 
     SDValue TargetCC = DAG.getCondCode(CCVal);
     SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};


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