[PATCH] D132206: [DAGCombiner] Fold vecreduce_xor/or/and(splat_vector(val)) to constant
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 19 00:12:55 PDT 2022
craig.topper added a comment.
Do you have real world examples of C code where this occurs?
Would this be better to do in InstCombine?
Where are the test deltas?
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:23506
+ if (Opcode == ISD::VECREDUCE_XOR)
+ return DAG.getConstant(0, SDLoc(N), N->getValueType(0));
+ if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR)
----------------
What if the element count is odd?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D132206/new/
https://reviews.llvm.org/D132206
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