[llvm] fc2b4df - [DAGCombiner] Add use check for VSCALE in visitSUB.
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Thu Aug 18 19:06:30 PDT 2022
Author: wanglian
Date: 2022-08-19T09:46:18+08:00
New Revision: fc2b4dfef2f1c4d04d0d5d25e14ffaa0622d5189
URL: https://github.com/llvm/llvm-project/commit/fc2b4dfef2f1c4d04d0d5d25e14ffaa0622d5189
DIFF: https://github.com/llvm/llvm-project/commit/fc2b4dfef2f1c4d04d0d5d25e14ffaa0622d5189.diff
LOG: [DAGCombiner] Add use check for VSCALE in visitSUB.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D132115
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/AArch64/sve-vscale-combine.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 56beea3e248ae..11fb6fe1c165e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3720,7 +3720,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
}
// canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C))
- if (N1.getOpcode() == ISD::VSCALE) {
+ if (N1.getOpcode() == ISD::VSCALE && N1.hasOneUse()) {
const APInt &IntVal = N1.getConstantOperandAPInt(0);
return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal));
}
diff --git a/llvm/test/CodeGen/AArch64/sve-vscale-combine.ll b/llvm/test/CodeGen/AArch64/sve-vscale-combine.ll
index 1ebe91f329b38..9306c208c3b55 100644
--- a/llvm/test/CodeGen/AArch64/sve-vscale-combine.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vscale-combine.ll
@@ -76,10 +76,8 @@ define i32 @combine_sub_vscale_i32(i32 %in) nounwind {
define i64 @multiple_uses_sub_vscale_i64(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: multiple_uses_sub_vscale_i64:
; CHECK-NEXT: rdvl x8, #1
-; CHECK-NEXT: rdvl x9, #-1
; CHECK-NEXT: lsr x8, x8, #4
-; CHECK-NEXT: asr x9, x9, #4
-; CHECK-NEXT: add x9, x0, x9
+; CHECK-NEXT: sub x9, x0, x8
; CHECK-NEXT: add x8, x1, x8
; CHECK-NEXT: mul x0, x9, x8
; CHECK-NEXT: ret
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