[llvm] 063ee26 - [AMDGPU] Update comment on shrinking dpp. NFC

[Joe Nash via llvm-commits]

Author: Joe Nash
Date: 2022-08-18T11:29:32-04:00
New Revision: 063ee26ea36abf343e0730e5aec82afa509a8c28

URL: https://github.com/llvm/llvm-project/commit/063ee26ea36abf343e0730e5aec82afa509a8c28
DIFF: https://github.com/llvm/llvm-project/commit/063ee26ea36abf343e0730e5aec82afa509a8c28.diff

LOG: [AMDGPU] Update comment on shrinking dpp. NFC

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
index 11f7156b80458..1e07a617cb79b 100644
--- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
@@ -124,9 +124,10 @@ bool GCNDPPCombine::isShrinkable(MachineInstr &MI) const {
     return false;
   }
   if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) {
-    // Give up if there are any uses of the carry-out from instructions like
-    // V_ADD_CO_U32. The shrunken form of the instruction would write it to vcc
-    // instead of to a virtual register.
+    // Give up if there are any uses of the sdst in carry-out or VOPC.
+    // The shrunken form of the instruction would write it to vcc instead of to
+    // a virtual register. If we rewrote the uses the shrinking would be
+    // possible.
     if (!MRI->use_nodbg_empty(SDst->getReg()))
       return false;
   }