[llvm] f4410d4 - [X86] Add schedule module for Alderlake-P
Haohai Wen via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 18 01:40:26 PDT 2022
Author: Haohai Wen
Date: 2022-08-18T16:40:14+08:00
New Revision: f4410d471f1f2664db382431ffb15c1c07db97d5
URL: https://github.com/llvm/llvm-project/commit/f4410d471f1f2664db382431ffb15c1c07db97d5
DIFF: https://github.com/llvm/llvm-project/commit/f4410d471f1f2664db382431ffb15c1c07db97d5.diff
LOG: [X86] Add schedule module for Alderlake-P
The X86SchedAlderlakeP.td file is automatically generated by schedtool
(D130897). Most of instruction's scheduling information is based on
measured ADL-P data in uops.info. Some data is from GLC tpt/lat data
provided by intel doc. The rest instruction's scheduling information is
from skylake client schedule model in order to get a relative complete
model.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D130959
Added:
llvm/lib/Target/X86/X86SchedAlderlakeP.td
llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-adx.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmpxchg.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fsgsbase.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lzcnt.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-movbe.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-popcnt.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-prefetchw.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdrand.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdseed.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_32.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x87.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s
Modified:
llvm/lib/Target/X86/X86.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index fa0a6bd415dc0..4c208df8f342e 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -675,6 +675,7 @@ include "X86ScheduleBtVer2.td"
include "X86SchedSkylakeClient.td"
include "X86SchedSkylakeServer.td"
include "X86SchedIceLake.td"
+include "X86SchedAlderlakeP.td"
//===----------------------------------------------------------------------===//
// X86 Processor Feature Lists
@@ -1479,7 +1480,7 @@ def : ProcModel<"tigerlake", IceLakeModel,
ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;
def : ProcModel<"sapphirerapids", SkylakeServerModel,
ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
-def : ProcModel<"alderlake", SkylakeClientModel,
+def : ProcModel<"alderlake", AlderlakePModel,
ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
// AMD CPUs.
diff --git a/llvm/lib/Target/X86/X86SchedAlderlakeP.td b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
new file mode 100644
index 0000000000000..4278c436d1f96
--- /dev/null
+++ b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
@@ -0,0 +1,2448 @@
+//===- X86SchedAlderlakeP.td - X86 Alderlake-P Scheduling ----*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for Alderlake-P core to support
+// instruction scheduling and other instruction cost heuristics.
+//
+//===----------------------------------------------------------------------===//
+
+def AlderlakePModel : SchedMachineModel {
+ // Alderlake-P core can allocate 6 uops per cycle.
+ let IssueWidth = 6; // Based on allocator width.
+ let MicroOpBufferSize = 512; // Based on the reorder buffer.
+ let LoadLatency = 5;
+ let MispredictPenalty = 14;
+
+ // Latency for microcoded instructions or instructions without latency info.
+ int MaxLatency = 100;
+
+ // Based on the LSD (loop-stream detector) queue size (ST).
+ let LoopMicroOpBufferSize = 72;
+
+ // This flag is set to allow the scheduler to assign a default model to
+ // unrecognized opcodes.
+ let CompleteModel = 0;
+}
+
+let SchedModel = AlderlakePModel in {
+
+// Alderlake-P core can issue micro-ops to 12
diff erent ports in one cycle.
+def ADLPPort00 : ProcResource<1>;
+def ADLPPort01 : ProcResource<1>;
+def ADLPPort02 : ProcResource<1>;
+def ADLPPort03 : ProcResource<1>;
+def ADLPPort04 : ProcResource<1>;
+def ADLPPort05 : ProcResource<1>;
+def ADLPPort06 : ProcResource<1>;
+def ADLPPort07 : ProcResource<1>;
+def ADLPPort08 : ProcResource<1>;
+def ADLPPort09 : ProcResource<1>;
+def ADLPPort10 : ProcResource<1>;
+def ADLPPort11 : ProcResource<1>;
+
+// Workaround to represent invalid ports. WriteRes shouldn't use this resource.
+def ADLPPortInvalid : ProcResource<1>;
+
+// Many micro-ops are capable of issuing on multiple ports.
+def ADLPPort00_01 : ProcResGroup<[ADLPPort00, ADLPPort01]>;
+def ADLPPort00_01_05 : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort05]>;
+def ADLPPort00_01_05_06 : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort05, ADLPPort06]>;
+def ADLPPort00_05 : ProcResGroup<[ADLPPort00, ADLPPort05]>;
+def ADLPPort00_05_06 : ProcResGroup<[ADLPPort00, ADLPPort05, ADLPPort06]>;
+def ADLPPort00_06 : ProcResGroup<[ADLPPort00, ADLPPort06]>;
+def ADLPPort01_05 : ProcResGroup<[ADLPPort01, ADLPPort05]>;
+def ADLPPort01_05_10 : ProcResGroup<[ADLPPort01, ADLPPort05, ADLPPort10]>;
+def ADLPPort02_03 : ProcResGroup<[ADLPPort02, ADLPPort03]>;
+def ADLPPort02_03_07 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort07]>;
+def ADLPPort02_03_11 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort11]>;
+def ADLPPort07_08 : ProcResGroup<[ADLPPort07, ADLPPort08]>;
+
+// EU has 112 reservation stations.
+def ADLPPort00_01_05_06_10 : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort05,
+ ADLPPort06, ADLPPort10]> {
+ let BufferSize = 112;
+}
+
+// STD has 48 reservation stations.
+def ADLPPort04_09 : ProcResGroup<[ADLPPort04, ADLPPort09]> {
+ let BufferSize = 48;
+}
+
+// MEM has 72 reservation stations.
+def ADLPPort02_03_07_08_11 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort07,
+ ADLPPort08, ADLPPort11]> {
+ let BufferSize = 72;
+}
+
+// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available
+// until 5 cycles after the memory operand.
+def : ReadAdvance<ReadAfterLd, 5>;
+
+// Vector loads are 6 cycles, so ReadAfterVec*Ld registers needn't be available
+// until 6 cycles after the memory operand.
+def : ReadAdvance<ReadAfterVecLd, 6>;
+def : ReadAdvance<ReadAfterVecXLd, 6>;
+def : ReadAdvance<ReadAfterVecYLd, 6>;
+
+def : ReadAdvance<ReadInt2Fpu, 0>;
+
+// Many SchedWrites are defined in pairs with and without a folded load.
+// Instructions with folded loads are usually micro-fused, so they only appear
+// as two micro-ops when queued in the reservation station.
+// This multiclass defines the resource usage for variants with and without
+// folded loads.
+multiclass ADLPWriteResPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts,
+ int Lat, list<int> Res = [1], int UOps = 1,
+ int LoadLat = 5> {
+ // Register variant is using a single cycle on ExePort.
+ def : WriteRes<SchedRW, ExePorts> {
+ let Latency = Lat;
+ let ResourceCycles = Res;
+ let NumMicroOps = UOps;
+ }
+
+ // Memory variant also uses a cycle on port 2/3/11 and adds LoadLat cycles to
+ // the latency (default = 5).
+ def : WriteRes<SchedRW.Folded, !listconcat([ADLPPort02_03_11], ExePorts)> {
+ let Latency = !add(Lat, LoadLat);
+ let ResourceCycles = !listconcat([1], Res);
+ let NumMicroOps = !add(UOps, 1);
+ }
+}
+
+//===----------------------------------------------------------------------===//
+// The following definitons are infered by smg.
+//===----------------------------------------------------------------------===//
+
+// Infered SchedWrite definition.
+def : WriteRes<WriteADC, [ADLPPort00_06]>;
+defm : X86WriteRes<WriteADCLd, [ADLPPort00_01_05_06_10, ADLPPort00_06], 11, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteAESDecEnc, [ADLPPort00_01], 5, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteAESIMC, [ADLPPort00_01], 8, [2], 2, 7>;
+defm : X86WriteRes<WriteAESKeyGen, [ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort05], 7, [4, 1, 1, 2, 3, 3], 14>;
+defm : X86WriteRes<WriteAESKeyGenLd, [ADLPPort00, ADLPPort00_01, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05], 12, [4, 1, 2, 3, 1, 3], 14>;
+def : WriteRes<WriteALU, [ADLPPort00_01_05_06_10]>;
+def : WriteRes<WriteALULd, [ADLPPort00_01_05_06_10]> {
+ let Latency = 11;
+}
+defm : ADLPWriteResPair<WriteBEXTR, [ADLPPort00_06, ADLPPort01], 6, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteBLS, [ADLPPort01_05_10], 2, [1]>;
+defm : ADLPWriteResPair<WriteBSF, [ADLPPort01], 3, [1]>;
+defm : ADLPWriteResPair<WriteBSR, [ADLPPort01], 3, [1]>;
+def : WriteRes<WriteBSWAP32, [ADLPPort01]>;
+defm : X86WriteRes<WriteBSWAP64, [ADLPPort00_06, ADLPPort01], 2, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteBZHI, [ADLPPort01], 3, [1]>;
+def : WriteRes<WriteBitTest, [ADLPPort01]>;
+defm : X86WriteRes<WriteBitTestImmLd, [ADLPPort01, ADLPPort02_03_11], 6, [1, 1], 2>;
+defm : X86WriteRes<WriteBitTestRegLd, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11], 11, [4, 2, 1, 2, 1], 10>;
+def : WriteRes<WriteBitTestSet, [ADLPPort01]>;
+def : WriteRes<WriteBitTestSetImmLd, [ADLPPort01]> {
+ let Latency = 11;
+}
+defm : X86WriteRes<WriteBitTestSetRegLd, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10], 17, [3, 2, 1, 2], 8>;
+defm : ADLPWriteResPair<WriteBlend, [ADLPPort01_05], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteBlendY, [ADLPPort00_01_05], 1, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteCLMul, [ADLPPort05], 3, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteCMOV, [ADLPPort00_06], 1, [1], 1, 6>;
+defm : X86WriteRes<WriteCMPXCHG, [ADLPPort00_01_05_06_10, ADLPPort00_06], 3, [3, 2], 5>;
+defm : X86WriteRes<WriteCMPXCHGRMW, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08], 12, [1, 2, 1, 1, 1], 6>;
+defm : ADLPWriteResPair<WriteCRC32, [ADLPPort01], 3, [1]>;
+defm : X86WriteRes<WriteCvtI2PD, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtI2PDLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtI2PDY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtI2PDYLd, [ADLPPort00_01, ADLPPort02_03_11], 12, [1, 1], 2>;
+defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
+defm : ADLPWriteResPair<WriteCvtI2PS, [ADLPPort00_01], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteCvtI2PSY, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
+defm : X86WriteRes<WriteCvtI2SD, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtI2SDLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtI2SS, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtI2SSLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteCvtPD2I, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2, 7>;
+defm : ADLPWriteResPair<WriteCvtPD2IY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2, 8>;
+defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
+defm : ADLPWriteResPair<WriteCvtPD2PS, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2, 7>;
+defm : ADLPWriteResPair<WriteCvtPD2PSY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2, 8>;
+defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
+defm : X86WriteRes<WriteCvtPH2PS, [ADLPPort00_01, ADLPPort05], 6, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPH2PSLd, [ADLPPort00_01, ADLPPort02_03_11], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPH2PSY, [ADLPPort00_01, ADLPPort05], 8, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPH2PSYLd, [ADLPPort00_01, ADLPPort02_03_11], 12, [1, 1], 2>;
+defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
+defm : ADLPWriteResPair<WriteCvtPS2I, [ADLPPort00_01], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteCvtPS2IY, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
+defm : X86WriteRes<WriteCvtPS2PD, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPS2PDLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPS2PDY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPS2PDYLd, [ADLPPort00_01, ADLPPort02_03_11], 12, [1, 1], 2>;
+defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
+defm : X86WriteRes<WriteCvtPS2PH, [ADLPPort00_01, ADLPPort05], 6, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPS2PHSt, [ADLPPort00_01, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteCvtPS2PHY, [ADLPPort00_01, ADLPPort05], 8, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPS2PHYSt, [ADLPPort00_01, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1], 3>;
+defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
+defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
+defm : ADLPWriteResPair<WriteCvtSD2I, [ADLPPort00, ADLPPort00_01], 7, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteCvtSD2SS, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2, 7>;
+defm : ADLPWriteResPair<WriteCvtSS2I, [ADLPPort00, ADLPPort00_01], 7, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtSS2SD, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtSS2SDLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteDPPD, [ADLPPort00_01, ADLPPort01_05], 9, [2, 1], 3, 7>;
+defm : ADLPWriteResPair<WriteDPPS, [ADLPPort00_01, ADLPPort00_06, ADLPPort01_05, ADLPPort05], 14, [2, 1, 2, 1], 6, 7>;
+defm : ADLPWriteResPair<WriteDPPSY, [ADLPPort00_01, ADLPPort00_06, ADLPPort01_05, ADLPPort05], 14, [2, 1, 2, 1], 6, 8>;
+defm : ADLPWriteResPair<WriteDiv16, [ADLPPort00_01_05_06_10, ADLPPort01], 16, [1, 3], 4, 4>;
+defm : ADLPWriteResPair<WriteDiv32, [ADLPPort00_01_05_06_10, ADLPPort01], 15, [1, 3], 4, 4>;
+defm : ADLPWriteResPair<WriteDiv64, [ADLPPort01], 18, [3], 3>;
+defm : X86WriteRes<WriteDiv8, [ADLPPort01], 17, [3], 3>;
+defm : X86WriteRes<WriteDiv8Ld, [ADLPPort01], 22, [3], 3>;
+defm : X86WriteRes<WriteEMMS, [ADLPPort00, ADLPPort00_05, ADLPPort00_06], 10, [1, 8, 1], 10>;
+def : WriteRes<WriteFAdd, [ADLPPort05]> {
+ let Latency = 3;
+}
+defm : X86WriteRes<WriteFAddLd, [ADLPPort02_03, ADLPPort05], 10, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteFAdd64, [ADLPPort01_05], 3, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFAdd64X, [ADLPPort01_05], 3, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFAdd64Y, [ADLPPort01_05], 3, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
+defm : ADLPWriteResPair<WriteFAddX, [ADLPPort01_05], 3, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFAddY, [ADLPPort01_05], 3, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFAddZ>;
+defm : ADLPWriteResPair<WriteFBlend, [ADLPPort00_01_05], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFBlendY, [ADLPPort00_01_05], 1, [1], 1, 8>;
+def : WriteRes<WriteFCMOV, [ADLPPort01]> {
+ let Latency = 3;
+}
+defm : ADLPWriteResPair<WriteFCmp, [ADLPPort00_01], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFCmp64, [ADLPPort00_01], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFCmp64X, [ADLPPort00_01], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFCmp64Y, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
+defm : ADLPWriteResPair<WriteFCmpX, [ADLPPort00_01], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFCmpY, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFCmpZ>;
+def : WriteRes<WriteFCom, [ADLPPort05]>;
+defm : X86WriteRes<WriteFComLd, [ADLPPort02_03, ADLPPort05], 8, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteFComX, [ADLPPort00], 3, [1]>;
+def : WriteRes<WriteFDiv, [ADLPPort00]> {
+ let Latency = 15;
+}
+defm : X86WriteRes<WriteFDivLd, [ADLPPort00, ADLPPort02_03], 27, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteFDiv64, [ADLPPort00], 14, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFDiv64X, [ADLPPort00], 14, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFDiv64Y, [ADLPPort00], 14, [1], 1, 7>;
+defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
+defm : ADLPWriteResPair<WriteFDivX, [ADLPPort00], 11, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFDivY, [ADLPPort00], 11, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFDivZ>;
+defm : ADLPWriteResPair<WriteFHAdd, [ADLPPort01_05, ADLPPort05], 6, [1, 2], 3, 6>;
+defm : ADLPWriteResPair<WriteFHAddY, [ADLPPort01_05, ADLPPort05], 5, [1, 2], 3, 8>;
+def : WriteRes<WriteFLD0, [ADLPPort00_05]>;
+defm : X86WriteRes<WriteFLD1, [ADLPPort00_05], 1, [2], 2>;
+defm : X86WriteRes<WriteFLDC, [ADLPPort00_05], 1, [2], 2>;
+def : WriteRes<WriteFLoad, [ADLPPort02_03_11]> {
+ let Latency = 7;
+}
+def : WriteRes<WriteFLoadX, [ADLPPort02_03_11]> {
+ let Latency = 7;
+}
+def : WriteRes<WriteFLoadY, [ADLPPort02_03_11]> {
+ let Latency = 8;
+}
+defm : ADLPWriteResPair<WriteFLogic, [ADLPPort00_01_05], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFLogicY, [ADLPPort00_01_05], 1, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFLogicZ>;
+defm : ADLPWriteResPair<WriteFMA, [ADLPPort00_01], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFMAX, [ADLPPort00_01], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFMAY, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFMAZ>;
+def : WriteRes<WriteFMOVMSK, [ADLPPort00]> {
+ let Latency = 3;
+}
+defm : X86WriteRes<WriteFMaskedLoad, [ADLPPort00_01_05, ADLPPort02_03_11], 8, [1, 1], 2>;
+defm : X86WriteRes<WriteFMaskedLoadY, [ADLPPort00_01_05, ADLPPort02_03_11], 9, [1, 1], 2>;
+defm : X86WriteRes<WriteFMaskedStore32, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMaskedStore32Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMaskedStore64, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMaskedStore64Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMoveX, [], 1, [], 0>;
+defm : X86WriteRes<WriteFMoveY, [], 1, [], 0>;
+defm : X86WriteResUnsupported<WriteFMoveZ>;
+def : WriteRes<WriteFMul, [ADLPPort00]> {
+ let Latency = 4;
+}
+defm : X86WriteRes<WriteFMulLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteFMul64, [ADLPPort00_01], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFMul64X, [ADLPPort00_01], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFMul64Y, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFMul64Z>;
+defm : ADLPWriteResPair<WriteFMulX, [ADLPPort00_01], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFMulY, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFMulZ>;
+defm : ADLPWriteResPair<WriteFRcp, [ADLPPort00], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFRcpX, [ADLPPort00], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFRcpY, [ADLPPort00], 4, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFRcpZ>;
+defm : ADLPWriteResPair<WriteFRnd, [ADLPPort00_01], 8, [2], 2, 7>;
+defm : ADLPWriteResPair<WriteFRndY, [ADLPPort00_01], 8, [2], 2, 8>;
+defm : X86WriteResPairUnsupported<WriteFRndZ>;
+defm : ADLPWriteResPair<WriteFRsqrt, [ADLPPort00], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFRsqrtX, [ADLPPort00], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFRsqrtY, [ADLPPort00], 4, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
+defm : ADLPWriteResPair<WriteFShuffle, [ADLPPort05], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFShuffle256, [ADLPPort05], 3, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFShuffleY, [ADLPPort05], 1, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
+def : WriteRes<WriteFSign, [ADLPPort00]>;
+defm : ADLPWriteResPair<WriteFSqrt, [ADLPPort00], 12, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFSqrt64, [ADLPPort00], 18, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFSqrt64X, [ADLPPort00], 18, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFSqrt64Y, [ADLPPort00], 18, [1], 1, 7>;
+defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
+def : WriteRes<WriteFSqrt80, [ADLPPortInvalid, ADLPPort00]> {
+ let ResourceCycles = [7, 1];
+ let Latency = 21;
+}
+defm : ADLPWriteResPair<WriteFSqrtX, [ADLPPort00], 12, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFSqrtY, [ADLPPort00], 12, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
+defm : X86WriteRes<WriteFStore, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
+defm : X86WriteResUnsupported<WriteFStoreNT>;
+defm : X86WriteRes<WriteFStoreNTX, [ADLPPort04_09, ADLPPort07_08], 518, [1, 1], 2>;
+defm : X86WriteRes<WriteFStoreNTY, [ADLPPort04_09, ADLPPort07_08], 542, [1, 1], 2>;
+defm : X86WriteRes<WriteFStoreX, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteFStoreY, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteFTest, [ADLPPort00], 3, [1]>;
+defm : ADLPWriteResPair<WriteFTestY, [ADLPPort00], 5, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFVarBlend, [ADLPPort00_01_05], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFVarBlendY, [ADLPPort00_01_05], 3, [3], 3, 7>;
+defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
+defm : ADLPWriteResPair<WriteFVarShuffle, [ADLPPort05], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFVarShuffle256, [ADLPPort05], 3, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFVarShuffleY, [ADLPPort05], 1, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
+def : WriteRes<WriteFence, [ADLPPort00_06]> {
+ let Latency = 2;
+}
+defm : ADLPWriteResPair<WriteIDiv16, [ADLPPort00_01_05_06_10, ADLPPort01], 16, [1, 3], 4, 4>;
+defm : ADLPWriteResPair<WriteIDiv32, [ADLPPort00_01_05_06_10, ADLPPort01], 15, [1, 3], 4, 4>;
+defm : ADLPWriteResPair<WriteIDiv64, [ADLPPort01], 18, [3], 3>;
+defm : X86WriteRes<WriteIDiv8, [ADLPPort01], 17, [3], 3>;
+defm : X86WriteRes<WriteIDiv8Ld, [ADLPPort01], 22, [3], 3>;
+defm : ADLPWriteResPair<WriteIMul16, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01], 5, [2, 1, 1], 4>;
+defm : ADLPWriteResPair<WriteIMul16Imm, [ADLPPort00_01_05_06_10, ADLPPort01], 4, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteIMul16Reg, [ADLPPort01], 3, [1]>;
+defm : ADLPWriteResPair<WriteIMul32, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01], 4, [1, 1, 1], 3>;
+defm : ADLPWriteResPair<WriteIMul32Imm, [ADLPPort01], 3, [1]>;
+defm : ADLPWriteResPair<WriteIMul32Reg, [ADLPPort01], 3, [1]>;
+defm : ADLPWriteResPair<WriteIMul64, [ADLPPort01, ADLPPort05], 4, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteIMul64Imm, [ADLPPort01], 3, [1]>;
+defm : ADLPWriteResPair<WriteIMul64Reg, [ADLPPort01], 3, [1]>;
+defm : ADLPWriteResPair<WriteIMul8, [ADLPPort01], 3, [1]>;
+def : WriteRes<WriteIMulH, []> {
+ let Latency = 3;
+}
+def : WriteRes<WriteIMulHLd, []> {
+ let Latency = 3;
+}
+def : WriteRes<WriteJump, [ADLPPort00_06]>;
+defm : X86WriteRes<WriteJumpLd, [ADLPPort00_06, ADLPPort02_03], 6, [1, 1], 2>;
+def : WriteRes<WriteLAHFSAHF, [ADLPPort00_06]> {
+ let Latency = 3;
+}
+defm : X86WriteRes<WriteLDMXCSR, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_11], 7, [1, 1, 1, 1], 4>;
+def : WriteRes<WriteLEA, [ADLPPort01]>;
+defm : ADLPWriteResPair<WriteLZCNT, [ADLPPort01], 3, [1]>;
+def : WriteRes<WriteLoad, [ADLPPort02_03_11]> {
+ let Latency = 5;
+}
+def : WriteRes<WriteMMXMOVMSK, [ADLPPort00]> {
+ let Latency = 3;
+}
+defm : ADLPWriteResPair<WriteMPSAD, [ADLPPort01_05, ADLPPort05], 4, [1, 1], 2, 7>;
+defm : ADLPWriteResPair<WriteMPSADY, [ADLPPort01_05, ADLPPort05], 4, [1, 1], 2, 8>;
+defm : ADLPWriteResPair<WriteMULX32, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01], 4, [1, 1, 1], 2>;
+defm : ADLPWriteResPair<WriteMULX64, [ADLPPort01, ADLPPort05], 4, [1, 1]>;
+def : WriteRes<WriteMicrocoded, [ADLPPort00_01_05_06]> {
+ let Latency = AlderlakePModel.MaxLatency;
+}
+def : WriteRes<WriteMove, [ADLPPort00_01_05_06_10]>;
+defm : X86WriteRes<WriteNop, [], 1, [], 0>;
+defm : X86WriteRes<WritePCmpEStrI, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01, ADLPPort05], 16, [3, 2, 1, 1, 1], 8>;
+defm : X86WriteRes<WritePCmpEStrILd, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05], 31, [3, 1, 1, 1, 1, 1], 8>;
+defm : X86WriteRes<WritePCmpEStrM, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01, ADLPPort05], 16, [3, 3, 1, 1, 1], 9>;
+defm : X86WriteRes<WritePCmpEStrMLd, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05], 17, [3, 2, 1, 1, 1, 1], 9>;
+defm : ADLPWriteResPair<WritePCmpIStrI, [ADLPPort00], 11, [3], 3, 20>;
+defm : ADLPWriteResPair<WritePCmpIStrM, [ADLPPort00], 11, [3], 3>;
+defm : ADLPWriteResPair<WritePHAdd, [ADLPPort00_05, ADLPPort05], 3, [1, 2], 3, 8>;
+defm : ADLPWriteResPair<WritePHAddX, [ADLPPort00_01_05, ADLPPort01_05], 2, [1, 2], 3, 7>;
+defm : ADLPWriteResPair<WritePHAddY, [ADLPPort00_01_05, ADLPPort01_05], 2, [1, 2], 3, 8>;
+defm : ADLPWriteResPair<WritePHMINPOS, [ADLPPort00], 4, [1], 1, 7>;
+defm : ADLPWriteResPair<WritePMULLD, [ADLPPort00_01], 10, [2], 2, 8>;
+defm : ADLPWriteResPair<WritePMULLDY, [ADLPPort00_01], 10, [2], 2, 8>;
+defm : X86WriteResPairUnsupported<WritePMULLDZ>;
+defm : ADLPWriteResPair<WritePOPCNT, [ADLPPort01], 3, [1]>;
+defm : ADLPWriteResPair<WritePSADBW, [ADLPPort05], 3, [1], 1, 8>;
+defm : ADLPWriteResPair<WritePSADBWX, [ADLPPort05], 3, [1], 1, 7>;
+defm : ADLPWriteResPair<WritePSADBWY, [ADLPPort05], 3, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WritePSADBWZ>;
+defm : X86WriteRes<WriteRMW, [ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08], 1, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteRotate, [ADLPPort00_01_05_06_10, ADLPPort00_06], 2, [1, 2], 3>;
+defm : X86WriteRes<WriteRotateLd, [ADLPPort00_01_05_06_10, ADLPPort00_06], 12, [1, 2], 3>;
+defm : X86WriteRes<WriteRotateCL, [ADLPPort00_06], 2, [2], 2>;
+defm : X86WriteRes<WriteRotateCLLd, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01], 19, [2, 3, 2], 7>;
+defm : X86WriteRes<WriteSETCC, [ADLPPort00_06], 2, [2], 2>;
+defm : X86WriteRes<WriteSETCCStore, [ADLPPort00_06, ADLPPort04_09, ADLPPort07_08], 13, [2, 1, 1], 4>;
+defm : X86WriteRes<WriteSHDmrcl, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1, 1, 1, 1], 6>;
+defm : X86WriteRes<WriteSHDmri, [ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1, 1, 1], 5>;
+defm : X86WriteRes<WriteSHDrrcl, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01], 5, [1, 1, 1], 3>;
+def : WriteRes<WriteSHDrri, [ADLPPort01]> {
+ let Latency = 3;
+}
+defm : X86WriteRes<WriteSTMXCSR, [ADLPPort00, ADLPPort00_06, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1, 1], 4>;
+def : WriteRes<WriteShift, [ADLPPort00_06]>;
+def : WriteRes<WriteShiftLd, [ADLPPort00_06]> {
+ let Latency = 12;
+}
+defm : X86WriteRes<WriteShiftCL, [ADLPPort00_06], 2, [2], 2>;
+defm : X86WriteRes<WriteShiftCLLd, [ADLPPort00_06], 12, [2], 2>;
+defm : ADLPWriteResPair<WriteShuffle, [ADLPPort05], 1, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteShuffle256, [ADLPPort05], 3, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteShuffleX, [ADLPPort01_05], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteShuffleY, [ADLPPort01_05], 1, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteShuffleZ>;
+defm : X86WriteRes<WriteStore, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteStoreNT, [ADLPPort04_09, ADLPPort07_08], 512, [1, 1], 2>;
+def : WriteRes<WriteSystem, [ADLPPort00_01_05_06]> {
+ let Latency = AlderlakePModel.MaxLatency;
+}
+defm : ADLPWriteResPair<WriteTZCNT, [ADLPPort01], 3, [1]>;
+defm : ADLPWriteResPair<WriteVPMOV256, [ADLPPort05], 3, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteVarBlend, [ADLPPort00_01_05], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteVarBlendY, [ADLPPort00_01_05], 3, [3], 3, 7>;
+defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
+defm : ADLPWriteResPair<WriteVarShuffle, [ADLPPort00, ADLPPort05], 3, [1, 1], 2, 8>;
+defm : ADLPWriteResPair<WriteVarShuffle256, [ADLPPort05], 3, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteVarShuffleX, [ADLPPort01_05], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteVarShuffleY, [ADLPPort01_05], 1, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
+defm : ADLPWriteResPair<WriteVarVecShift, [ADLPPort00_01], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteVarVecShiftY, [ADLPPort00_01], 1, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
+defm : ADLPWriteResPair<WriteVecALU, [ADLPPort00], 1, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteVecALUX, [ADLPPort00_01], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteVecALUY, [ADLPPort00_01], 1, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteVecALUZ>;
+defm : X86WriteRes<WriteVecExtract, [ADLPPort00, ADLPPort01_05], 4, [1, 1], 2>;
+defm : X86WriteRes<WriteVecExtractSt, [ADLPPort01_05, ADLPPort04_09, ADLPPort07_08], 19, [1, 1, 1], 3>;
+defm : ADLPWriteResPair<WriteVecIMul, [ADLPPort00], 5, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteVecIMulX, [ADLPPort00_01], 5, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteVecIMulY, [ADLPPort00_01], 5, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
+defm : X86WriteRes<WriteVecInsert, [ADLPPort01_05, ADLPPort05], 4, [1, 1], 2>;
+defm : X86WriteRes<WriteVecInsertLd, [ADLPPort01_05, ADLPPort02_03_11], 8, [1, 1], 2>;
+def : WriteRes<WriteVecLoad, [ADLPPort02_03_11]> {
+ let Latency = 7;
+}
+def : WriteRes<WriteVecLoadNT, [ADLPPort02_03_11]> {
+ let Latency = 7;
+}
+def : WriteRes<WriteVecLoadNTY, [ADLPPort02_03_11]> {
+ let Latency = 8;
+}
+def : WriteRes<WriteVecLoadX, [ADLPPort02_03_11]> {
+ let Latency = 7;
+}
+def : WriteRes<WriteVecLoadY, [ADLPPort02_03_11]> {
+ let Latency = 8;
+}
+defm : ADLPWriteResPair<WriteVecLogic, [ADLPPort00_05], 1, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteVecLogicX, [ADLPPort00_01_05], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteVecLogicY, [ADLPPort00_01_05], 1, [1], 1, 8>;
+defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
+def : WriteRes<WriteVecMOVMSK, [ADLPPort00]> {
+ let Latency = 3;
+}
+def : WriteRes<WriteVecMOVMSKY, [ADLPPort00]> {
+ let Latency = 4;
+}
+defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
+defm : X86WriteRes<WriteVecMaskedLoad, [ADLPPort00_01_05, ADLPPort02_03_11], 8, [1, 1], 2>;
+defm : X86WriteRes<WriteVecMaskedLoadY, [ADLPPort00_01_05, ADLPPort02_03_11], 9, [1, 1], 2>;
+defm : X86WriteRes<WriteVecMaskedStore32, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore32Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore64, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore64Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
+def : WriteRes<WriteVecMove, [ADLPPort00_05]>;
+def : WriteRes<WriteVecMoveFromGpr, [ADLPPort05]> {
+ let Latency = 3;
+}
+def : WriteRes<WriteVecMoveToGpr, [ADLPPort00]> {
+ let Latency = 3;
+}
+defm : X86WriteRes<WriteVecMoveX, [], 1, [], 0>;
+defm : X86WriteRes<WriteVecMoveY, [], 1, [], 0>;
+defm : X86WriteResUnsupported<WriteVecMoveZ>;
+defm : ADLPWriteResPair<WriteVecShift, [ADLPPort00], 1, [1], 1, 8>;
+def : WriteRes<WriteVecShiftImm, [ADLPPort00]>;
+def : WriteRes<WriteVecShiftImmX, [ADLPPort00_01]>;
+defm : X86WriteResUnsupported<WriteVecShiftImmXLd>;
+def : WriteRes<WriteVecShiftImmY, [ADLPPort00_01]>;
+defm : X86WriteResUnsupported<WriteVecShiftImmYLd>;
+defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
+defm : X86WriteRes<WriteVecShiftX, [ADLPPort00_01, ADLPPort01_05], 2, [1, 1], 2>;
+defm : X86WriteRes<WriteVecShiftXLd, [ADLPPort00_01, ADLPPort02_03_11], 8, [1, 1], 2>;
+defm : X86WriteRes<WriteVecShiftY, [ADLPPort00_01, ADLPPort05], 4, [1, 1], 2>;
+defm : X86WriteRes<WriteVecShiftYLd, [ADLPPort00_01, ADLPPort02_03_11], 9, [1, 1], 2>;
+defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
+defm : X86WriteRes<WriteVecStore, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStoreNT, [ADLPPort04_09, ADLPPort07_08], 511, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStoreNTY, [ADLPPort04_09, ADLPPort07_08], 507, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStoreX, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStoreY, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteVecTest, [ADLPPort00, ADLPPort05], 4, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteVecTestY, [ADLPPort00, ADLPPort05], 6, [1, 1], 2, 6>;
+defm : X86WriteRes<WriteXCHG, [ADLPPort00_01_05_06_10], 2, [3], 3>;
+def : WriteRes<WriteZero, []>;
+
+// Infered SchedWriteRes and InstRW definition.
+
+def ADLPWriteResGroup0 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [2, 1, 1, 1, 1];
+ let Latency = 12;
+ let NumMicroOps = 6;
+}
+def : InstRW<[ADLPWriteResGroup0, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>;
+
+def ADLPWriteResGroup1 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup1], (instregex "^JMP(16|32|64)m$",
+ "^RET(16|32)$",
+ "^RORX(32|64)mi$")>;
+def : InstRW<[ADLPWriteResGroup1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
+ "^AD(C|O)X(32|64)rm$")>;
+
+def ADLPWriteResGroup2 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 13;
+ let NumMicroOps = 5;
+}
+def : InstRW<[ADLPWriteResGroup2], (instregex "^(ADC|SBB)8mi$")>;
+
+def ADLPWriteResGroup3 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [2, 1, 1, 1, 1];
+ let Latency = 13;
+ let NumMicroOps = 6;
+}
+def : InstRW<[ADLPWriteResGroup3, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)8mr$")>;
+
+def ADLPWriteResGroup4 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup4], (instregex "^CMP(8|16|32)mi$",
+ "^CMP(16|32|64)mi8$",
+ "^CMP64mi32$",
+ "^MOV(8|16)rm$",
+ "^MOVZX16rm8$",
+ "^POP(16|32)r$")>;
+def : InstRW<[ADLPWriteResGroup4, ReadAfterLd], (instregex "^(ADD|CMP|SUB)(8|16|32|64)rm$",
+ "^(OR|AND|XOR)(8|16|32)rm$")>;
+def : InstRW<[ADLPWriteResGroup4, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^CMP(8|16|32|64)mr$")>;
+
+def ADLPWriteResGroup5 : SchedWriteRes<[]> {
+ let NumMicroOps = 0;
+}
+def : InstRW<[ADLPWriteResGroup5], (instregex "^(ADD|SUB)64ri8$",
+ "^CLC$",
+ "^(DE|IN)C64r$",
+ "^MOV64rr$",
+ "^MOV64rr_REV$")>;
+
+def ADLPWriteResGroup6 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 13;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup6], (instregex "^(OR|ADD|SUB|XOR)8mi$",
+ "^AND8mi$",
+ "^(DEC|NEG|NOT)8m$",
+ "^INC8m$")>;
+def : InstRW<[ADLPWriteResGroup6, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(OR|ADD|SUB|XOR)8mr$",
+ "^AND8mr$")>;
+
+def ADLPWriteResGroup7 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup7, ReadAfterVecLd], (instregex "^(V?)(ADD|SUB)SSrm_Int$")>;
+
+def ADLPWriteResGroup8 : SchedWriteRes<[ADLPPort01_05]> {
+ let Latency = 3;
+}
+def : InstRW<[ADLPWriteResGroup8], (instregex "^(V?)(ADD|SUB)SSrr_Int$")>;
+
+def ADLPWriteResGroup9 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
+ let ResourceCycles = [1, 2];
+ let Latency = 13;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup9], (instregex "^(ADD|SUB)_FI(16|32)m$",
+ "^SUBR_FI(16|32)m$")>;
+
+def ADLPWriteResGroup10 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+ let Latency = 2;
+}
+def : InstRW<[ADLPWriteResGroup10], (instregex "^(OR|AND|XOR)(16|32|64)ri8$",
+ "^(OR|AND|XOR)(8|16|32|64)rr$",
+ "^(OR|AND|XOR)(32|64)i32$",
+ "^(OR|AND|XOR)(8|32)ri$",
+ "^(OR|AND|XOR)64ri32$",
+ "^(OR|AND|XOR)8i8$",
+ "^TEST(8|16|32|64)rr$",
+ "^TEST(32|64)i32$",
+ "^TEST(8|32)ri$",
+ "^TEST64ri32$",
+ "^TEST8i8$")>;
+
+def ADLPWriteResGroup11 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup11], (instregex "^TEST(8|16|32)mi$",
+ "^TEST64mi32$")>;
+def : InstRW<[ADLPWriteResGroup11, ReadAfterLd], (instregex "^(OR|AND|XOR)64rm$")>;
+def : InstRW<[ADLPWriteResGroup11, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^TEST(8|16|32|64)mr$")>;
+
+def ADLPWriteResGroup12 : SchedWriteRes<[ADLPPort01_05_10, ADLPPort02_03_11]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup12, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>;
+
+def ADLPWriteResGroup13 : SchedWriteRes<[ADLPPort01_05_10]> {
+ let Latency = 2;
+}
+def : InstRW<[ADLPWriteResGroup13], (instregex "^ANDN(32|64)rr$")>;
+
+def ADLPWriteResGroup14 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+ let ResourceCycles = [5, 2, 1, 1];
+ let Latency = 10;
+ let NumMicroOps = 9;
+}
+def : InstRW<[ADLPWriteResGroup14], (instregex "^BT64mr$")>;
+
+def ADLPWriteResGroup15 : SchedWriteRes<[ADLPPort01]> {
+ let Latency = 3;
+}
+def : InstRW<[ADLPWriteResGroup15], (instregex "^(B|PEX)T64rr$",
+ "^BT(C|R|S)64rr$",
+ "^PDEP(32|64)rr$",
+ "^PEXT32rr$")>;
+
+def ADLPWriteResGroup16 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [4, 2, 1, 1, 1, 1];
+ let Latency = 17;
+ let NumMicroOps = 10;
+}
+def : InstRW<[ADLPWriteResGroup16], (instregex "^BT(C|R|S)64mr$")>;
+
+def ADLPWriteResGroup17 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 7;
+ let NumMicroOps = 5;
+}
+def : InstRW<[ADLPWriteResGroup17], (instregex "^CALL(16|32|64)m$")>;
+
+def ADLPWriteResGroup18 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 3;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup18], (instregex "^CALL(16|32|64)r$")>;
+
+def ADLPWriteResGroup19 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 3;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup19], (instregex "^CALL64pcrel32$",
+ "^MFENCE$")>;
+
+def ADLPWriteResGroup20 : SchedWriteRes<[ADLPPort01_05]>;
+def : InstRW<[ADLPWriteResGroup20], (instregex "^C(BW|DQE|WDE)$",
+ "^(V?)MOVS(H|L)DUPrr$",
+ "^(V?)SHUFP(D|S)rri$",
+ "^VMOVS(H|L)DUPYrr$",
+ "^VPBLENDWYrri$",
+ "^VSHUFP(D|S)Yrri$")>;
+
+def ADLPWriteResGroup21 : SchedWriteRes<[ADLPPort00_06]>;
+def : InstRW<[ADLPWriteResGroup21], (instregex "^C(DQ|QO|LAC)$",
+ "^STAC$")>;
+
+def ADLPWriteResGroup22 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+ let Latency = 3;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup22], (instregex "^CLD$")>;
+
+def ADLPWriteResGroup23 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 3;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup23], (instregex "^CLDEMOTE$")>;
+
+def ADLPWriteResGroup24 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 2;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup24], (instregex "^CLFLUSH$")>;
+
+def ADLPWriteResGroup25 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 2;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup25], (instregex "^CLFLUSHOPT$")>;
+
+def ADLPWriteResGroup26 : SchedWriteRes<[ADLPPort00_06, ADLPPort01]> {
+ let ResourceCycles = [2, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup26], (instregex "^CLI$")>;
+
+def ADLPWriteResGroup27 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+ let ResourceCycles = [6, 1, 3];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 10;
+}
+def : InstRW<[ADLPWriteResGroup27], (instregex "^CLTS$")>;
+
+def ADLPWriteResGroup28 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 5;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup28], (instregex "^CLWB$",
+ "^MOV16o(16|32|64)a$")>;
+
+def ADLPWriteResGroup29 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+ let ResourceCycles = [5, 2];
+ let Latency = 6;
+ let NumMicroOps = 7;
+}
+def : InstRW<[ADLPWriteResGroup29], (instregex "^CMPS(B|L|Q|W)$")>;
+
+def ADLPWriteResGroup30 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [2, 7, 6, 2, 1, 1, 2, 1];
+ let Latency = 32;
+ let NumMicroOps = 22;
+}
+def : InstRW<[ADLPWriteResGroup30], (instregex "^CMPXCHG16B$")>;
+
+def ADLPWriteResGroup31 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [4, 7, 2, 1, 1, 1];
+ let Latency = 25;
+ let NumMicroOps = 16;
+}
+def : InstRW<[ADLPWriteResGroup31], (instregex "^CMPXCHG8B$")>;
+
+def ADLPWriteResGroup32 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [1, 2, 1, 1, 1];
+ let Latency = 13;
+ let NumMicroOps = 6;
+}
+def : InstRW<[ADLPWriteResGroup32], (instregex "^CMPXCHG8rm$")>;
+
+def ADLPWriteResGroup33 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [2, 1, 10, 6, 1, 5, 1];
+ let Latency = 18;
+ let NumMicroOps = 26;
+}
+def : InstRW<[ADLPWriteResGroup33], (instregex "^CPUID$")>;
+
+def ADLPWriteResGroup34 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort02_03_11]> {
+ let Latency = 26;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup34], (instregex "^(V?)CVT(T?)SD2SIrm_Int$")>;
+
+def ADLPWriteResGroup35 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup35, ReadAfterVecLd], (instregex "^(V?)CVTSI642SSrm_Int$")>;
+
+def ADLPWriteResGroup36 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+ let ResourceCycles = [1, 2];
+ let Latency = 8;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup36, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$")>;
+
+def ADLPWriteResGroup37 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort05]> {
+ let Latency = 8;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup37], (instregex "^(V?)CVT(T?)SS2SI64rr_Int$")>;
+
+def ADLPWriteResGroup38 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup38], (instregex "^CWD$",
+ "^J(E|R)CXZ$")>;
+
+def ADLPWriteResGroup39 : SchedWriteRes<[ADLPPort00_01_05_06]>;
+def : InstRW<[ADLPWriteResGroup39], (instregex "^DEC16r_alt$",
+ "^(LD|ST)_Frr$",
+ "^MOV16s(m|r)$",
+ "^MOV(32|64)sr$",
+ "^SALC$",
+ "^ST_FPrr$",
+ "^SYSCALL$")>;
+
+def ADLPWriteResGroup40 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 7;
+}
+def : InstRW<[ADLPWriteResGroup40], (instregex "^DEC32r_alt$")>;
+
+def ADLPWriteResGroup41 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
+ let Latency = 30;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup41], (instregex "^DIVR_FI(16|32)m$")>;
+
+def ADLPWriteResGroup42 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+ let Latency = 18;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup42, ReadAfterVecLd], (instregex "^(V?)DIVSSrm_Int$")>;
+
+def ADLPWriteResGroup43 : SchedWriteRes<[ADLPPort00]> {
+ let Latency = 11;
+}
+def : InstRW<[ADLPWriteResGroup43], (instregex "^(V?)DIVSSrr_Int$")>;
+
+def ADLPWriteResGroup44 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
+ let Latency = 22;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup44], (instregex "^DIV_F(32|64)m$")>;
+
+def ADLPWriteResGroup45 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
+ let Latency = 25;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup45], (instregex "^DIV_FI(16|32)m$")>;
+
+def ADLPWriteResGroup46 : SchedWriteRes<[ADLPPort00]> {
+ let Latency = 20;
+}
+def : InstRW<[ADLPWriteResGroup46], (instregex "^DIV_F(P?)rST0$",
+ "^DIV_FST0r$")>;
+
+def ADLPWriteResGroup47 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [2, 21, 2, 14, 4, 9, 5];
+ let Latency = 126;
+ let NumMicroOps = 57;
+}
+def : InstRW<[ADLPWriteResGroup47], (instregex "^ENTER$")>;
+
+def ADLPWriteResGroup48 : SchedWriteRes<[ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup48], (instregex "^(V?)EXTRACTPSmr$",
+ "^SMSW16m$")>;
+
+def ADLPWriteResGroup49 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
+ let Latency = 4;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup49], (instregex "^(V?)EXTRACTPSrr$",
+ "^MMX_PEXTRWrr$")>;
+
+def ADLPWriteResGroup50 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
+ let Latency = 7;
+ let NumMicroOps = 5;
+}
+def : InstRW<[ADLPWriteResGroup50], (instregex "^FARCALL64m$")>;
+
+def ADLPWriteResGroup51 : SchedWriteRes<[ADLPPort02_03, ADLPPort06]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup51], (instregex "^FARJMP64m$")>;
+
+def ADLPWriteResGroup52 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]> {
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup52], (instregex "^FBSTPm$",
+ "^(V?)MASKMOVDQU((64)?)$",
+ "^ST_FP(32|64|80)m$",
+ "^VMPTRSTm$")>;
+
+def ADLPWriteResGroup53 : SchedWriteRes<[ADLPPort00_05]> {
+ let ResourceCycles = [2];
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup53], (instregex "^FDECSTP$")>;
+
+def ADLPWriteResGroup54 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
+ let ResourceCycles = [1, 2];
+ let Latency = 11;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup54], (instregex "^FICOM(P?)(16|32)m$")>;
+
+def ADLPWriteResGroup55 : SchedWriteRes<[ADLPPort00_05]>;
+def : InstRW<[ADLPWriteResGroup55], (instregex "^FINCSTP$",
+ "^FNOP$",
+ "^MMX_P(ADD|SUB)(B|D|Q|W)rr$")>;
+
+def ADLPWriteResGroup56 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort02_03]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup56], (instregex "^FLDCW16m$")>;
+
+def ADLPWriteResGroup57 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort02_03]> {
+ let ResourceCycles = [2, 39, 5, 10, 8];
+ let Latency = 62;
+ let NumMicroOps = 64;
+}
+def : InstRW<[ADLPWriteResGroup57], (instregex "^FLDENVm$")>;
+
+def ADLPWriteResGroup58 : SchedWriteRes<[ADLPPort00_01_05_06]> {
+ let ResourceCycles = [4];
+ let Latency = 4;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup58], (instregex "^FNCLEX$")>;
+
+def ADLPWriteResGroup59 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort05]> {
+ let ResourceCycles = [6, 3, 6];
+ let Latency = 75;
+ let NumMicroOps = 15;
+}
+def : InstRW<[ADLPWriteResGroup59], (instregex "^FNINIT$")>;
+
+def ADLPWriteResGroup60 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
+ let Latency = 2;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup60], (instregex "^FNSTCW16m$")>;
+
+def ADLPWriteResGroup61 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06]> {
+ let Latency = 3;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup61], (instregex "^FNSTSW16r$")>;
+
+def ADLPWriteResGroup62 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_07, ADLPPort04]> {
+ let Latency = 3;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup62], (instregex "^FNSTSWm$")>;
+
+def ADLPWriteResGroup63 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
+ let ResourceCycles = [9, 30, 21, 1, 11, 11, 16, 1];
+ let Latency = 106;
+ let NumMicroOps = 100;
+}
+def : InstRW<[ADLPWriteResGroup63], (instregex "^FSTENVm$")>;
+
+def ADLPWriteResGroup64 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
+ let ResourceCycles = [4, 47, 1, 2, 1, 33, 2];
+ let Latency = 63;
+ let NumMicroOps = 90;
+}
+def : InstRW<[ADLPWriteResGroup64], (instregex "^FXRSTOR$")>;
+
+def ADLPWriteResGroup65 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
+ let ResourceCycles = [4, 45, 1, 2, 1, 31, 4];
+ let Latency = 63;
+ let NumMicroOps = 88;
+}
+def : InstRW<[ADLPWriteResGroup65], (instregex "^FXRSTOR64$")>;
+
+def ADLPWriteResGroup66 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [2, 5, 10, 10, 2, 38, 5, 38];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 110;
+}
+def : InstRW<[ADLPWriteResGroup66], (instregex "^FXSAVE((64)?)$")>;
+
+def ADLPWriteResGroup67 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
+ let Latency = 12;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup67, ReadAfterVecXLd], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrmi$",
+ "^(V?)GF2P8MULBrm$",
+ "^VGF2P8AFFINE((INV)?)QBYrmi$",
+ "^VGF2P8MULBYrm$")>;
+
+def ADLPWriteResGroup68 : SchedWriteRes<[ADLPPort00_01]> {
+ let Latency = 5;
+}
+def : InstRW<[ADLPWriteResGroup68], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrri$",
+ "^(V?)GF2P8MULBrr$",
+ "^VGF2P8AFFINE((INV)?)QBYrri$",
+ "^VGF2P8MULBYrr$")>;
+
+def ADLPWriteResGroup69 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup69], (instregex "^ILD_F(16|32|64)m$")>;
+
+def ADLPWriteResGroup70 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [7, 5, 26, 19, 2, 7, 21];
+ let Latency = 35;
+ let NumMicroOps = 87;
+}
+def : InstRW<[ADLPWriteResGroup70], (instregex "^IN16ri$")>;
+
+def ADLPWriteResGroup71 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [7, 1, 4, 26, 19, 3, 7, 20];
+ let Latency = 35;
+ let NumMicroOps = 87;
+}
+def : InstRW<[ADLPWriteResGroup71], (instregex "^IN16rr$")>;
+
+def ADLPWriteResGroup72 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [7, 6, 28, 21, 2, 10, 20];
+ let Latency = 35;
+ let NumMicroOps = 94;
+}
+def : InstRW<[ADLPWriteResGroup72], (instregex "^IN32ri$")>;
+
+def ADLPWriteResGroup73 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [7, 9, 28, 21, 2, 11, 21];
+ let NumMicroOps = 99;
+}
+def : InstRW<[ADLPWriteResGroup73], (instregex "^IN32rr$")>;
+
+def ADLPWriteResGroup74 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [7, 6, 25, 19, 2, 8, 20];
+ let Latency = 35;
+ let NumMicroOps = 87;
+}
+def : InstRW<[ADLPWriteResGroup74], (instregex "^IN8ri$")>;
+
+def ADLPWriteResGroup75 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [7, 6, 25, 19, 2, 7, 20];
+ let Latency = 35;
+ let NumMicroOps = 86;
+}
+def : InstRW<[ADLPWriteResGroup75], (instregex "^IN8rr$")>;
+
+def ADLPWriteResGroup76 : SchedWriteRes<[ADLPPort00_06]> {
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup76], (instregex "^INC16r_alt$")>;
+
+def ADLPWriteResGroup77 : SchedWriteRes<[ADLPPort02_03_11]> {
+ let Latency = 7;
+}
+def : InstRW<[ADLPWriteResGroup77], (instregex "^INC32r_alt$",
+ "^(V?)MOV(D|SH|SL)DUPrm$",
+ "^VBROADCASTSSrm$",
+ "^VPBROADCAST(D|Q)rm$")>;
+
+def ADLPWriteResGroup78 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [7, 6, 24, 17, 8, 1, 19, 1];
+ let Latency = 20;
+ let NumMicroOps = 83;
+}
+def : InstRW<[ADLPWriteResGroup78], (instregex "^INSB$")>;
+
+def ADLPWriteResGroup79 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
+ let Latency = 20;
+ let NumMicroOps = 92;
+}
+def : InstRW<[ADLPWriteResGroup79], (instregex "^INSL$")>;
+
+def ADLPWriteResGroup80 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
+ let Latency = 20;
+ let NumMicroOps = 86;
+}
+def : InstRW<[ADLPWriteResGroup80], (instregex "^INSW$")>;
+
+def ADLPWriteResGroup81 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [5, 4, 8, 6, 2, 5, 7, 5];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 42;
+}
+def : InstRW<[ADLPWriteResGroup81], (instregex "^INVLPG$")>;
+
+def ADLPWriteResGroup82 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort05]> {
+ let Latency = 4;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup82], (instregex "^IST(T?)_FP(16|32|64)m$",
+ "^IST_F(16|32)m$")>;
+
+def ADLPWriteResGroup83 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_06]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup83], (instregex "^JCXZ$")>;
+
+def ADLPWriteResGroup84 : SchedWriteRes<[]> {
+ let Latency = 0;
+ let NumMicroOps = 0;
+}
+def : InstRW<[ADLPWriteResGroup84], (instregex "^JMP_1$",
+ "^VZEROUPPER$")>;
+
+def ADLPWriteResGroup85 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [8, 2, 14, 3, 1];
+ let Latency = 198;
+ let NumMicroOps = 81;
+}
+def : InstRW<[ADLPWriteResGroup85], (instregex "^LAR16rm$")>;
+
+def ADLPWriteResGroup86 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
+ let Latency = 66;
+ let NumMicroOps = 22;
+}
+def : InstRW<[ADLPWriteResGroup86], (instregex "^LAR16rr$")>;
+
+def ADLPWriteResGroup87 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
+ let Latency = 71;
+ let NumMicroOps = 85;
+}
+def : InstRW<[ADLPWriteResGroup87], (instregex "^LAR32rm$")>;
+
+def ADLPWriteResGroup88 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
+ let Latency = 65;
+ let NumMicroOps = 22;
+}
+def : InstRW<[ADLPWriteResGroup88], (instregex "^LAR(32|64)rr$")>;
+
+def ADLPWriteResGroup89 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
+ let Latency = 71;
+ let NumMicroOps = 87;
+}
+def : InstRW<[ADLPWriteResGroup89], (instregex "^LAR64rm$")>;
+
+def ADLPWriteResGroup90 : SchedWriteRes<[ADLPPort02_03]> {
+ let Latency = 7;
+}
+def : InstRW<[ADLPWriteResGroup90], (instregex "^LD_F(32|64|80)m$")>;
+
+def ADLPWriteResGroup91 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup91], (instregex "^LEA16r$")>;
+
+def ADLPWriteResGroup92 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+ let ResourceCycles = [3, 1];
+ let Latency = 6;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup92], (instregex "^LEAVE$",
+ "^(LOD|SCA)S(B|W)$",
+ "^SCAS(L|Q)$")>;
+
+def ADLPWriteResGroup93 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+ let ResourceCycles = [2, 1];
+ let Latency = 6;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup93], (instregex "^LEAVE64$")>;
+
+def ADLPWriteResGroup94 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [1, 2, 4, 3, 2, 1, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 14;
+}
+def : InstRW<[ADLPWriteResGroup94], (instregex "^LGDT64m$")>;
+
+def ADLPWriteResGroup95 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [1, 1, 5, 3, 2, 1, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 14;
+}
+def : InstRW<[ADLPWriteResGroup95], (instregex "^LIDT64m$")>;
+
+def ADLPWriteResGroup96 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [5, 3, 2, 1, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 12;
+}
+def : InstRW<[ADLPWriteResGroup96], (instregex "^LLDT16m$")>;
+
+def ADLPWriteResGroup97 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [1, 4, 3, 1, 1, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 11;
+}
+def : InstRW<[ADLPWriteResGroup97], (instregex "^LLDT16r$")>;
+
+def ADLPWriteResGroup98 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 27;
+}
+def : InstRW<[ADLPWriteResGroup98], (instregex "^LMSW16m$")>;
+
+def ADLPWriteResGroup99 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [5, 7, 1, 2, 5, 2];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 22;
+}
+def : InstRW<[ADLPWriteResGroup99], (instregex "^LMSW16r$")>;
+
+def ADLPWriteResGroup100 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+ let ResourceCycles = [2, 1];
+ let Latency = 5;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup100], (instregex "^LODS(L|Q)$")>;
+
+def ADLPWriteResGroup101 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+ let ResourceCycles = [2, 4, 1];
+ let Latency = 3;
+ let NumMicroOps = 7;
+}
+def : InstRW<[ADLPWriteResGroup101], (instregex "^LOOP$")>;
+
+def ADLPWriteResGroup102 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+ let ResourceCycles = [4, 6, 1];
+ let Latency = 3;
+ let NumMicroOps = 11;
+}
+def : InstRW<[ADLPWriteResGroup102], (instregex "^LOOPE$")>;
+
+def ADLPWriteResGroup103 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+ let ResourceCycles = [4, 6, 1];
+ let Latency = 2;
+ let NumMicroOps = 11;
+}
+def : InstRW<[ADLPWriteResGroup103], (instregex "^LOOPNE$")>;
+
+def ADLPWriteResGroup104 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort06]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup104], (instregex "^LRET64$")>;
+
+def ADLPWriteResGroup105 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [1, 5, 3, 3, 1];
+ let Latency = 70;
+ let NumMicroOps = 13;
+}
+def : InstRW<[ADLPWriteResGroup105], (instregex "^LSL(16|32|64)rm$")>;
+
+def ADLPWriteResGroup106 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [1, 4, 4, 3, 2, 1];
+ let Latency = 63;
+ let NumMicroOps = 15;
+}
+def : InstRW<[ADLPWriteResGroup106], (instregex "^LSL(16|32|64)rr$")>;
+
+def ADLPWriteResGroup107 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 24;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup107], (instregex "^MMX_CVT(T?)PD2PIrm$")>;
+
+def ADLPWriteResGroup108 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup108], (instregex "^MMX_CVT(T?)PD2PIrr$")>;
+
+def ADLPWriteResGroup109 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup109], (instregex "^MMX_CVTPI2PDrr$")>;
+
+def ADLPWriteResGroup110 : SchedWriteRes<[ADLPPort00, ADLPPort00_01]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup110], (instregex "^MMX_CVTPI2PSrr$")>;
+
+def ADLPWriteResGroup111 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+ let Latency = 13;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup111], (instregex "^MMX_CVT(T?)PS2PIrm$")>;
+
+def ADLPWriteResGroup112 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup112], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
+
+def ADLPWriteResGroup113 : SchedWriteRes<[ADLPPort00, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [2, 1, 1];
+ let Latency = 12;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup113], (instregex "^MMX_MASKMOVQ((64)?)$")>;
+
+def ADLPWriteResGroup114 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 18;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup114], (instregex "^MMX_MOVD64mr$")>;
+
+def ADLPWriteResGroup115 : SchedWriteRes<[ADLPPort02_03_11]> {
+ let Latency = 8;
+}
+def : InstRW<[ADLPWriteResGroup115], (instregex "^MMX_MOV(D|Q)64rm$",
+ "^VBROADCAST(F|I)128$",
+ "^VBROADCASTS(D|S)Yrm$",
+ "^VMOV(D|SH|SL)DUPYrm$",
+ "^VPBROADCAST(D|Q)Yrm$")>;
+
+def ADLPWriteResGroup116 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_05]> {
+ let Latency = 3;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup116], (instregex "^MMX_MOVDQ2Qrr$")>;
+
+def ADLPWriteResGroup117 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
+ let Latency = 3;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup117], (instregex "^MMX_MOVQ2DQrr$")>;
+
+def ADLPWriteResGroup118 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [1, 2];
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup118, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$",
+ "^MMX_PACKUSWBrm$")>;
+
+def ADLPWriteResGroup119 : SchedWriteRes<[ADLPPort05]> {
+ let ResourceCycles = [2];
+ let Latency = 4;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup119], (instregex "^MMX_PACKSS(DW|WB)rr$",
+ "^MMX_PACKUSWBrr$")>;
+def : InstRW<[ADLPWriteResGroup119, ReadDefault, ReadInt2Fpu], (instregex "^MMX_PINSRWrr$")>;
+
+def ADLPWriteResGroup120 : SchedWriteRes<[ADLPPort00_05, ADLPPort02_03_11]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup120, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;
+
+def ADLPWriteResGroup121 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [1, 1, 2];
+ let Latency = 11;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup121, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
+
+def ADLPWriteResGroup122 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
+ let ResourceCycles = [1, 2];
+ let Latency = 3;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup122], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;
+
+def ADLPWriteResGroup123 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup123], (instregex "^VPBROADCAST(B|W)Yrm$")>;
+def : InstRW<[ADLPWriteResGroup123, ReadAfterLd], (instregex "^MMX_PINSRWrm$")>;
+def : InstRW<[ADLPWriteResGroup123, ReadAfterVecYLd], (instregex "^VPALIGNRYrmi$")>;
+
+def ADLPWriteResGroup124 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+ let Latency = 5;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup124], (instregex "^MOV16ao(16|32|64)$")>;
+
+def ADLPWriteResGroup125 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup125], (instregex "^MOV16ms$",
+ "^MOVBE32mr$",
+ "^PUSH(F|G)S(16|32)$")>;
+
+def ADLPWriteResGroup126 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup126], (instregex "^MOV(16|32|64)rs$",
+ "^S(TR|LDT)16r$")>;
+
+def ADLPWriteResGroup127 : SchedWriteRes<[ADLPPort02_03_11]>;
+def : InstRW<[ADLPWriteResGroup127], (instregex "^MOV32ao(16|32|64)$",
+ "^MOV64ao64$")>;
+
+def ADLPWriteResGroup128 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup128], (instregex "^MOV(8|32)o(16|32)a$",
+ "^MOV(8|32|64)o64a$")>;
+
+def ADLPWriteResGroup129 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+ let Latency = 0;
+}
+def : InstRW<[ADLPWriteResGroup129], (instregex "^MOV32rr$",
+ "^MOV32rr_REV$",
+ "^MOVZX(32|64)rr8$")>;
+
+def ADLPWriteResGroup130 : SchedWriteRes<[ADLPPort02_03_11]> {
+ let Latency = 5;
+}
+def : InstRW<[ADLPWriteResGroup130], (instregex "^MOV64ao32$",
+ "^MOVZX(32|64)rm(8|16)$")>;
+
+def ADLPWriteResGroup131 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
+ let Latency = 217;
+ let NumMicroOps = 48;
+}
+def : InstRW<[ADLPWriteResGroup131], (instregex "^MOV64dr$")>;
+
+def ADLPWriteResGroup132 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 12;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup132], (instregex "^MOV64o32a$")>;
+
+def ADLPWriteResGroup133 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort05]> {
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup133], (instregex "^MOV64rc$")>;
+
+def ADLPWriteResGroup134 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
+ let ResourceCycles = [3, 4, 8, 4, 2, 3];
+ let Latency = 181;
+ let NumMicroOps = 24;
+}
+def : InstRW<[ADLPWriteResGroup134], (instregex "^MOV64rd$")>;
+
+def ADLPWriteResGroup135 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup135], (instregex "^MOV8ao(16|32|64)$")>;
+
+def ADLPWriteResGroup136 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 13;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup136], (instregex "^MOV8m(i|r)$")>;
+
+def ADLPWriteResGroup137 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup137], (instregex "^MOVBE16mr$")>;
+
+def ADLPWriteResGroup138 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup138], (instregex "^MOVBE16rm$")>;
+
+def ADLPWriteResGroup139 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup139], (instregex "^MOVBE32rm$")>;
+
+def ADLPWriteResGroup140 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 12;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup140], (instregex "^MOVBE64mr$",
+ "^PUSHF16$",
+ "^SLDT16m$",
+ "^STRm$")>;
+
+def ADLPWriteResGroup141 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup141], (instregex "^MOVBE64rm$")>;
+
+def ADLPWriteResGroup142 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup142], (instregex "^MOVDIR64B(16|32|64)$")>;
+
+def ADLPWriteResGroup143 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 511;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup143], (instregex "^MOVDIRI32$")>;
+
+def ADLPWriteResGroup144 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 514;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup144], (instregex "^MOVDIRI64$")>;
+
+def ADLPWriteResGroup145 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup145, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$",
+ "^(V?)SHUFP(D|S)rmi$")>;
+
+def ADLPWriteResGroup146 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 512;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup146], (instregex "^MOVNTDQmr$")>;
+
+def ADLPWriteResGroup147 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 518;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup147], (instregex "^MOVNTImr$")>;
+
+def ADLPWriteResGroup148 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [4, 1, 1, 1];
+ let Latency = 8;
+ let NumMicroOps = 7;
+}
+def : InstRW<[ADLPWriteResGroup148], (instregex "^MOVSB$")>;
+
+def ADLPWriteResGroup149 : SchedWriteRes<[ADLPPort00_01_05]>;
+def : InstRW<[ADLPWriteResGroup149], (instregex "^(V?)MOVS(D|S)rr$",
+ "^(V?)MOVS(D|S)rr_REV$",
+ "^(V?)P(ADD|SUB)(B|D|Q|W)rr$",
+ "^VP(ADD|SUB)(B|D|Q|W)Yrr$",
+ "^VPBLENDDrri$")>;
+
+def ADLPWriteResGroup150 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [4, 1, 1, 1];
+ let Latency = 7;
+ let NumMicroOps = 7;
+}
+def : InstRW<[ADLPWriteResGroup150], (instregex "^MOVS(L|Q|W)$")>;
+
+def ADLPWriteResGroup151 : SchedWriteRes<[ADLPPort01_05_10, ADLPPort02_03_11]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup151], (instregex "^MOVSX16rm8$")>;
+
+def ADLPWriteResGroup152 : SchedWriteRes<[ADLPPort01_05_10]>;
+def : InstRW<[ADLPWriteResGroup152], (instregex "^MOVSX(16|32|64)rr8$",
+ "^MOVSX(32|64)rr16$",
+ "^MOVSX64rr32$")>;
+
+def ADLPWriteResGroup153 : SchedWriteRes<[ADLPPort02_03_11]> {
+ let Latency = 6;
+}
+def : InstRW<[ADLPWriteResGroup153], (instregex "^MOVSX(32|64)rm(8|16)$",
+ "^MOVSX64rm32$")>;
+
+def ADLPWriteResGroup154 : SchedWriteRes<[ADLPPort00_01]> {
+ let Latency = 4;
+}
+def : InstRW<[ADLPWriteResGroup154], (instregex "^(V?)MULSSrr_Int$")>;
+
+def ADLPWriteResGroup155 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
+ let Latency = 11;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup155], (instregex "^MUL_F(32|64)m$")>;
+
+def ADLPWriteResGroup156 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
+ let Latency = 14;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup156], (instregex "^MUL_FI(16|32)m$")>;
+
+def ADLPWriteResGroup157 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort05, ADLPPort06]> {
+ let ResourceCycles = [7, 1, 2];
+ let Latency = 20;
+ let NumMicroOps = 10;
+}
+def : InstRW<[ADLPWriteResGroup157], (instregex "^MWAITrr$")>;
+
+def ADLPWriteResGroup158 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
+ let Latency = 35;
+ let NumMicroOps = 79;
+}
+def : InstRW<[ADLPWriteResGroup158], (instregex "^OUT16ir$")>;
+
+def ADLPWriteResGroup159 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [6, 6, 27, 15, 7, 1, 16, 1];
+ let Latency = 35;
+ let NumMicroOps = 79;
+}
+def : InstRW<[ADLPWriteResGroup159], (instregex "^OUT16rr$")>;
+
+def ADLPWriteResGroup160 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
+ let Latency = 35;
+ let NumMicroOps = 85;
+}
+def : InstRW<[ADLPWriteResGroup160], (instregex "^OUT32ir$")>;
+
+def ADLPWriteResGroup161 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [6, 6, 29, 15, 9, 1, 18, 1];
+ let Latency = 35;
+ let NumMicroOps = 85;
+}
+def : InstRW<[ADLPWriteResGroup161], (instregex "^OUT32rr$")>;
+
+def ADLPWriteResGroup162 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
+ let Latency = 35;
+ let NumMicroOps = 73;
+}
+def : InstRW<[ADLPWriteResGroup162], (instregex "^OUT8ir$")>;
+
+def ADLPWriteResGroup163 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [5, 5, 26, 15, 5, 1, 15, 1];
+ let Latency = 35;
+ let NumMicroOps = 73;
+}
+def : InstRW<[ADLPWriteResGroup163], (instregex "^OUT8rr$")>;
+
+def ADLPWriteResGroup164 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [7, 6, 25, 16, 7, 1, 17, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 80;
+}
+def : InstRW<[ADLPWriteResGroup164], (instregex "^OUTSB$")>;
+
+def ADLPWriteResGroup165 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [7, 6, 28, 16, 10, 1, 20, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 89;
+}
+def : InstRW<[ADLPWriteResGroup165], (instregex "^OUTSL$")>;
+
+def ADLPWriteResGroup166 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 83;
+}
+def : InstRW<[ADLPWriteResGroup166], (instregex "^OUTSW$")>;
+
+def ADLPWriteResGroup167 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup167, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",
+ "^(V?)PCMPGTQrm$")>;
+
+def ADLPWriteResGroup168 : SchedWriteRes<[ADLPPort05]> {
+ let Latency = 3;
+}
+def : InstRW<[ADLPWriteResGroup168], (instregex "^(V?)PACK(S|U)S(DW|WB)rr$",
+ "^(V?)PCMPGTQrr$",
+ "^VPACK(S|U)S(DW|WB)Yrr$",
+ "^VPCMPGTQYrr$")>;
+
+def ADLPWriteResGroup169 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup169, ReadAfterVecXLd], (instregex "^(V?)P(ADD|SUB)(B|D|Q|W)rm$",
+ "^VPBLENDDrmi$")>;
+
+def ADLPWriteResGroup170 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup170], (instregex "^VPBROADCAST(B|W)rm$")>;
+def : InstRW<[ADLPWriteResGroup170, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$")>;
+
+def ADLPWriteResGroup171 : SchedWriteRes<[ADLPPort05]>;
+def : InstRW<[ADLPWriteResGroup171], (instregex "^(V?)PALIGNRrri$",
+ "^VPALIGNRYrri$",
+ "^VPBROADCAST(B|D|Q|W)rr$")>;
+
+def ADLPWriteResGroup172 : SchedWriteRes<[ADLPPort00_06, ADLPPort05]> {
+ let Latency = 4;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup172], (instregex "^PAUSE$")>;
+
+def ADLPWriteResGroup173 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup173, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;
+
+def ADLPWriteResGroup174 : SchedWriteRes<[ADLPPort01_05, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup174], (instregex "^(V?)PEXTR(D|Q)mr$")>;
+
+def ADLPWriteResGroup175 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
+ let ResourceCycles = [1, 2, 1];
+ let Latency = 9;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup175, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
+
+def ADLPWriteResGroup176 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05]> {
+ let ResourceCycles = [1, 2];
+ let Latency = 2;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup176], (instregex "^(V?)PH(ADD|SUB)SWrr$",
+ "^VPH(ADD|SUB)SWYrr$")>;
+
+def ADLPWriteResGroup177 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup177], (instregex "^POP(16|32|64)rmm$",
+ "^PUSH(16|32)rmm$")>;
+
+def ADLPWriteResGroup178 : SchedWriteRes<[ADLPPort02_03]> {
+ let Latency = 5;
+}
+def : InstRW<[ADLPWriteResGroup178], (instregex "^POPA(16|32)$",
+ "^POPF32$")>;
+
+def ADLPWriteResGroup179 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+ let ResourceCycles = [6, 2, 1, 1];
+ let Latency = 5;
+ let NumMicroOps = 10;
+}
+def : InstRW<[ADLPWriteResGroup179], (instregex "^POPF16$")>;
+
+def ADLPWriteResGroup180 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+ let ResourceCycles = [2, 1, 1];
+ let Latency = 5;
+ let NumMicroOps = 7;
+}
+def : InstRW<[ADLPWriteResGroup180], (instregex "^POPF64$")>;
+
+def ADLPWriteResGroup181 : SchedWriteRes<[ADLPPort02_03_11]> {
+ let Latency = 0;
+}
+def : InstRW<[ADLPWriteResGroup181], (instregex "^PREFETCH(T0|T1|T2|NTA)$")>;
+
+def ADLPWriteResGroup182 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort06]> {
+ let ResourceCycles = [1, 1, 2];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup182], (instregex "^PTWRITE((64)?)m$")>;
+
+def ADLPWriteResGroup183 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
+ let ResourceCycles = [1, 2];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup183], (instregex "^PTWRITE64r$")>;
+
+def ADLPWriteResGroup184 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
+ let ResourceCycles = [2, 2];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup184], (instregex "^PTWRITEr$")>;
+
+def ADLPWriteResGroup185 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup185], (instregex "^PUSH64r$")>;
+
+def ADLPWriteResGroup186 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup186], (instregex "^PUSH64rmm$")>;
+
+def ADLPWriteResGroup187 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]>;
+def : InstRW<[ADLPWriteResGroup187], (instregex "^PUSHA(16|32)$",
+ "^PUSHF32$",
+ "^ST_F(32|64)m$")>;
+
+def ADLPWriteResGroup188 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 4;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup188], (instregex "^PUSHF64$")>;
+
+def ADLPWriteResGroup189 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup189], (instregex "^PUSH(F|G)S64$")>;
+
+def ADLPWriteResGroup190 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+ let ResourceCycles = [2, 3, 2];
+ let Latency = 8;
+ let NumMicroOps = 7;
+}
+def : InstRW<[ADLPWriteResGroup190], (instregex "^RC(L|R)(16|32|64)rCL$")>;
+
+def ADLPWriteResGroup191 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+ let ResourceCycles = [1, 2];
+ let Latency = 13;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup191, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
+
+def ADLPWriteResGroup192 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+ let ResourceCycles = [1, 5, 2];
+ let Latency = 20;
+ let NumMicroOps = 8;
+}
+def : InstRW<[ADLPWriteResGroup192, WriteRMW], (instregex "^RCL8mCL$")>;
+
+def ADLPWriteResGroup193 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+ let ResourceCycles = [2, 5, 2];
+ let Latency = 7;
+ let NumMicroOps = 9;
+}
+def : InstRW<[ADLPWriteResGroup193], (instregex "^RCL8rCL$")>;
+
+def ADLPWriteResGroup194 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+ let ResourceCycles = [2, 4, 3];
+ let Latency = 20;
+ let NumMicroOps = 9;
+}
+def : InstRW<[ADLPWriteResGroup194, WriteRMW], (instregex "^RCR8mCL$")>;
+
+def ADLPWriteResGroup195 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+ let ResourceCycles = [3, 4, 3];
+ let Latency = 9;
+ let NumMicroOps = 10;
+}
+def : InstRW<[ADLPWriteResGroup195], (instregex "^RCR8rCL$")>;
+
+def ADLPWriteResGroup196 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort01_05_10, ADLPPort05]> {
+ let ResourceCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 54;
+}
+def : InstRW<[ADLPWriteResGroup196], (instregex "^RDMSR$")>;
+
+def ADLPWriteResGroup197 : SchedWriteRes<[ADLPPort01]> {
+ let Latency = AlderlakePModel.MaxLatency;
+}
+def : InstRW<[ADLPWriteResGroup197], (instregex "^RDPID64$")>;
+
+def ADLPWriteResGroup198 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup198], (instregex "^RDPKRUr$")>;
+
+def ADLPWriteResGroup199 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+ let ResourceCycles = [9, 6, 2, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 18;
+}
+def : InstRW<[ADLPWriteResGroup199], (instregex "^RDPMC$")>;
+
+def ADLPWriteResGroup200 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
+ let Latency = 1386;
+ let NumMicroOps = 25;
+}
+def : InstRW<[ADLPWriteResGroup200], (instregex "^RDRAND16r$")>;
+
+def ADLPWriteResGroup201 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 25;
+}
+def : InstRW<[ADLPWriteResGroup201], (instregex "^RDRAND(32|64)r$")>;
+
+def ADLPWriteResGroup202 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
+ let Latency = 1381;
+ let NumMicroOps = 25;
+}
+def : InstRW<[ADLPWriteResGroup202], (instregex "^RDSEED16r$")>;
+
+def ADLPWriteResGroup203 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 25;
+}
+def : InstRW<[ADLPWriteResGroup203], (instregex "^RDSEED(32|64)r$")>;
+
+def ADLPWriteResGroup204 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+ let ResourceCycles = [5, 6, 3, 1];
+ let Latency = 18;
+ let NumMicroOps = 15;
+}
+def : InstRW<[ADLPWriteResGroup204], (instregex "^RDTSC$")>;
+
+def ADLPWriteResGroup205 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+ let ResourceCycles = [2, 2, 1, 2, 7, 4, 3];
+ let Latency = 42;
+ let NumMicroOps = 21;
+}
+def : InstRW<[ADLPWriteResGroup205], (instregex "^RDTSCP$")>;
+
+def ADLPWriteResGroup206 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup206], (instregex "^RET64$")>;
+
+def ADLPWriteResGroup207 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+ let ResourceCycles = [2, 1];
+ let Latency = 6;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup207], (instregex "^RETI(16|32|64)$")>;
+
+def ADLPWriteResGroup208 : SchedWriteRes<[]>;
+def : InstRW<[ADLPWriteResGroup208], (instregex "^REX64_PREFIX$")>;
+
+def ADLPWriteResGroup209 : SchedWriteRes<[ADLPPort00_06]> {
+ let ResourceCycles = [2];
+ let Latency = 12;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup209, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
+
+def ADLPWriteResGroup210 : SchedWriteRes<[ADLPPort00_06]> {
+ let ResourceCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup210], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
+
+def ADLPWriteResGroup211 : SchedWriteRes<[ADLPPort00_06]> {
+ let ResourceCycles = [2];
+ let Latency = 13;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup211, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
+ "^(ROL|SAR|SHR)8mCL$",
+ "^(ROR|SHL)8mCL$")>;
+
+def ADLPWriteResGroup212 : SchedWriteRes<[ADLPPort00_06]> {
+ let ResourceCycles = [2];
+ let Latency = 4;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup212], (instregex "^SAHF$")>;
+
+def ADLPWriteResGroup213 : SchedWriteRes<[ADLPPort00_06]> {
+ let Latency = 13;
+}
+def : InstRW<[ADLPWriteResGroup213, WriteRMW], (instregex "^S(A|H)R8m(1|i)$",
+ "^SHL8m(1|i)$")>;
+
+def ADLPWriteResGroup214 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup214, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$",
+ "^SHLX(32|64)rm$")>;
+
+def ADLPWriteResGroup215 : SchedWriteRes<[ADLPPort00_06]> {
+ let Latency = 3;
+}
+def : InstRW<[ADLPWriteResGroup215], (instregex "^S(A|H)RX(32|64)rr$",
+ "^SHLX(32|64)rr$")>;
+
+def ADLPWriteResGroup216 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [2, 2, 1, 1, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 7;
+}
+def : InstRW<[ADLPWriteResGroup216], (instregex "^SERIALIZE$")>;
+
+def ADLPWriteResGroup217 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup217], (instregex "^SFENCE$")>;
+
+def ADLPWriteResGroup218 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [1, 2, 2, 2];
+ let Latency = 21;
+ let NumMicroOps = 7;
+}
+def : InstRW<[ADLPWriteResGroup218], (instregex "^S(G|I)DT64m$")>;
+
+def ADLPWriteResGroup219 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 9;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup219, ReadAfterVecXLd], (instregex "^SHA1MSG1rm$")>;
+
+def ADLPWriteResGroup220 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort05]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup220], (instregex "^SHA1MSG1rr$")>;
+
+def ADLPWriteResGroup221 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11]> {
+ let ResourceCycles = [2, 2, 1, 2, 1];
+ let Latency = 13;
+ let NumMicroOps = 8;
+}
+def : InstRW<[ADLPWriteResGroup221, ReadAfterVecXLd], (instregex "^SHA1MSG2rm$")>;
+
+def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {
+ let ResourceCycles = [2, 2, 1, 2];
+ let Latency = 6;
+ let NumMicroOps = 7;
+}
+def : InstRW<[ADLPWriteResGroup222], (instregex "^SHA1MSG2rr$")>;
+
+def ADLPWriteResGroup223 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+ let Latency = 8;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup223, ReadAfterVecXLd], (instregex "^SHA1NEXTErm$")>;
+
+def ADLPWriteResGroup224 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05]> {
+ let Latency = 3;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup224], (instregex "^SHA1NEXTErr$")>;
+
+def ADLPWriteResGroup225 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 13;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup225, ReadAfterVecXLd], (instregex "^SHA1RNDS4rmi$",
+ "^SHA256RNDS2rm$")>;
+
+def ADLPWriteResGroup226 : SchedWriteRes<[ADLPPort05]> {
+ let Latency = 6;
+}
+def : InstRW<[ADLPWriteResGroup226], (instregex "^SHA1RNDS4rri$",
+ "^SHA256RNDS2rr$")>;
+
+def ADLPWriteResGroup227 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [3, 2, 1, 1, 1];
+ let Latency = 12;
+ let NumMicroOps = 8;
+}
+def : InstRW<[ADLPWriteResGroup227, ReadAfterVecXLd], (instregex "^SHA256MSG1rm$")>;
+
+def ADLPWriteResGroup228 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort05]> {
+ let ResourceCycles = [3, 2, 1, 1];
+ let Latency = 5;
+ let NumMicroOps = 7;
+}
+def : InstRW<[ADLPWriteResGroup228], (instregex "^SHA256MSG1rr$")>;
+
+def ADLPWriteResGroup229 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [1, 2];
+ let Latency = 13;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup229, ReadAfterVecXLd], (instregex "^SHA256MSG2rm$")>;
+
+def ADLPWriteResGroup230 : SchedWriteRes<[ADLPPort05]> {
+ let ResourceCycles = [2];
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup230], (instregex "^SHA256MSG2rr$")>;
+
+def ADLPWriteResGroup231 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 13;
+ let NumMicroOps = 5;
+}
+def : InstRW<[ADLPWriteResGroup231], (instregex "^SHRD16mri8$")>;
+
+def ADLPWriteResGroup232 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup232], (instregex "^SLDT(32|64)r$")>;
+
+def ADLPWriteResGroup233 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup233], (instregex "^SMSW16r$")>;
+
+def ADLPWriteResGroup234 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup234], (instregex "^SMSW(32|64)r$")>;
+
+def ADLPWriteResGroup235 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup235], (instregex "^STD$")>;
+
+def ADLPWriteResGroup236 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+ let ResourceCycles = [1, 4, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 6;
+}
+def : InstRW<[ADLPWriteResGroup236], (instregex "^STI$")>;
+
+def ADLPWriteResGroup237 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [2, 1, 1];
+ let Latency = 8;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup237], (instregex "^STOSB$")>;
+
+def ADLPWriteResGroup238 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+ let ResourceCycles = [2, 1, 1];
+ let Latency = 7;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup238], (instregex "^STOS(L|Q|W)$")>;
+
+def ADLPWriteResGroup239 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+ let Latency = 5;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup239], (instregex "^STR(32|64)r$")>;
+
+def ADLPWriteResGroup240 : SchedWriteRes<[ADLPPort00]> {
+ let Latency = 2;
+}
+def : InstRW<[ADLPWriteResGroup240], (instregex "^(TST|XAM)_F$",
+ "^UCOM_FPPr$")>;
+
+def ADLPWriteResGroup241 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+ let ResourceCycles = [3, 1];
+ let Latency = 9;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup241, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$",
+ "^VPBLENDVBrm$")>;
+
+def ADLPWriteResGroup242 : SchedWriteRes<[ADLPPort00_01_05]> {
+ let ResourceCycles = [3];
+ let Latency = 3;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup242], (instregex "^VBLENDVP(D|S)rr$",
+ "^VPBLENDVBrr$")>;
+
+def ADLPWriteResGroup243 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+ let ResourceCycles = [6, 7, 18];
+ let Latency = 81;
+ let NumMicroOps = 31;
+}
+def : InstRW<[ADLPWriteResGroup243], (instregex "^VERRm$")>;
+
+def ADLPWriteResGroup244 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+ let ResourceCycles = [6, 7, 17];
+ let Latency = 74;
+ let NumMicroOps = 30;
+}
+def : InstRW<[ADLPWriteResGroup244], (instregex "^VERRr$")>;
+
+def ADLPWriteResGroup245 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+ let ResourceCycles = [5, 8, 21];
+ let Latency = 81;
+ let NumMicroOps = 34;
+}
+def : InstRW<[ADLPWriteResGroup245], (instregex "^VERWm$")>;
+
+def ADLPWriteResGroup246 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+ let ResourceCycles = [5, 8, 20];
+ let Latency = 74;
+ let NumMicroOps = 33;
+}
+def : InstRW<[ADLPWriteResGroup246], (instregex "^VERWr$")>;
+
+def ADLPWriteResGroup247 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+ let ResourceCycles = [1, 1, 2, 4];
+ let Latency = 29;
+ let NumMicroOps = 8;
+}
+def : InstRW<[ADLPWriteResGroup247, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(DPD|QPS)Yrm$",
+ "^VGATHERQPDYrm$",
+ "^VPGATHER(D|Q)QYrm$",
+ "^VPGATHERQDYrm$")>;
+
+def ADLPWriteResGroup248 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+ let ResourceCycles = [1, 1, 1, 2];
+ let Latency = 20;
+ let NumMicroOps = 5;
+}
+def : InstRW<[ADLPWriteResGroup248, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(DPD|QPS)rm$",
+ "^VGATHERQPDrm$",
+ "^VPGATHER(D|Q)Qrm$",
+ "^VPGATHERQDrm$")>;
+
+def ADLPWriteResGroup249 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+ let ResourceCycles = [1, 1, 2, 8];
+ let Latency = 30;
+ let NumMicroOps = 12;
+}
+def : InstRW<[ADLPWriteResGroup249, WriteVecMaskedGatherWriteback], (instregex "^VGATHERDPSYrm$",
+ "^VPGATHERDDYrm$")>;
+
+def ADLPWriteResGroup250 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+ let ResourceCycles = [1, 1, 2, 4];
+ let Latency = 28;
+ let NumMicroOps = 8;
+}
+def : InstRW<[ADLPWriteResGroup250, WriteVecMaskedGatherWriteback], (instregex "^VGATHERDPSrm$",
+ "^VPGATHERDDrm$")>;
+
+def ADLPWriteResGroup251 : SchedWriteRes<[ADLPPort01_05, ADLPPort05]> {
+ let ResourceCycles = [1, 2];
+ let Latency = 5;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup251], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;
+
+def ADLPWriteResGroup252 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup252, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rm$",
+ "^VP(ADD|SUB)(B|D|Q|W)Yrm$")>;
+
+def ADLPWriteResGroup253 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort02_03_11]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup253], (instregex "^VLDMXCSR$")>;
+
+def ADLPWriteResGroup254 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
+ let ResourceCycles = [8, 1, 1, 1, 1, 1, 2, 3];
+ let Latency = 40;
+ let NumMicroOps = 18;
+}
+def : InstRW<[ADLPWriteResGroup254], (instregex "^VMCLEARm$")>;
+
+def ADLPWriteResGroup255 : SchedWriteRes<[ADLPPort00]> {
+ let Latency = 5;
+}
+def : InstRW<[ADLPWriteResGroup255], (instregex "^VMOVMSKP(D|S)Yrr$")>;
+
+def ADLPWriteResGroup256 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 521;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup256], (instregex "^VMOVNTDQmr$")>;
+
+def ADLPWriteResGroup257 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 473;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup257], (instregex "^VMOVNTPDmr$")>;
+
+def ADLPWriteResGroup258 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 494;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup258], (instregex "^VMOVNTPSYmr$")>;
+
+def ADLPWriteResGroup259 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 470;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup259], (instregex "^VMOVNTPSmr$")>;
+
+def ADLPWriteResGroup260 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 11;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup260, ReadAfterVecYLd], (instregex "^VPACK(S|U)S(DW|WB)Yrm$",
+ "^VPCMPGTQYrm$")>;
+def : InstRW<[ADLPWriteResGroup260, ReadAfterVecXLd], (instregex "^VPCLMULQDQYrm$")>;
+
+def ADLPWriteResGroup261 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup261, ReadAfterVecYLd], (instregex "^VPBLENDWYrmi$",
+ "^VSHUFP(D|S)Yrmi$")>;
+
+def ADLPWriteResGroup262 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
+ let Latency = 13;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup262], (instregex "^VPDP(BU|WS)SD((SY)?)rm$",
+ "^VPDP(BU|WS)SD(S|Y)rm$")>;
+
+def ADLPWriteResGroup263 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
+ let ResourceCycles = [1, 2, 1];
+ let Latency = 10;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup263, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;
+
+def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10]> {
+ let ResourceCycles = [1, 2, 3, 3, 1];
+ let Latency = 16;
+ let NumMicroOps = 10;
+}
+def : InstRW<[ADLPWriteResGroup264], (instregex "^VZEROALL$")>;
+
+def ADLPWriteResGroup265 : SchedWriteRes<[ADLPPort00_01_05_06]> {
+ let ResourceCycles = [2];
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup265], (instregex "^WAIT$")>;
+
+def ADLPWriteResGroup266 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 144;
+}
+def : InstRW<[ADLPWriteResGroup266], (instregex "^WRMSR$")>;
+
+def ADLPWriteResGroup267 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+ let ResourceCycles = [2, 1, 4, 1];
+ let Latency = AlderlakePModel.MaxLatency;
+ let NumMicroOps = 8;
+}
+def : InstRW<[ADLPWriteResGroup267], (instregex "^WRPKRUr$")>;
+
+def ADLPWriteResGroup268 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+ let ResourceCycles = [2];
+ let Latency = 12;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup268, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
+
+def ADLPWriteResGroup269 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+ let ResourceCycles = [2];
+ let Latency = 13;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup269, WriteRMW], (instregex "^XADD8rm$")>;
+
+def ADLPWriteResGroup270 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+ let ResourceCycles = [4, 1];
+ let Latency = 39;
+ let NumMicroOps = 5;
+}
+def : InstRW<[ADLPWriteResGroup270, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
+
+def ADLPWriteResGroup271 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+ let ResourceCycles = [5, 1];
+ let Latency = 39;
+ let NumMicroOps = 6;
+}
+def : InstRW<[ADLPWriteResGroup271, WriteRMW], (instregex "^XCHG64rm$")>;
+
+def ADLPWriteResGroup272 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+ let ResourceCycles = [4, 1];
+ let Latency = 40;
+ let NumMicroOps = 5;
+}
+def : InstRW<[ADLPWriteResGroup272, WriteRMW], (instregex "^XCHG8rm$")>;
+
+def ADLPWriteResGroup273 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort01, ADLPPort05, ADLPPort06]> {
+ let ResourceCycles = [2, 4, 2, 1, 2, 4];
+ let Latency = 17;
+ let NumMicroOps = 15;
+}
+def : InstRW<[ADLPWriteResGroup273], (instregex "^XCH_F$")>;
+
+def ADLPWriteResGroup274 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01]> {
+ let ResourceCycles = [7, 3, 8, 5];
+ let Latency = 4;
+ let NumMicroOps = 23;
+}
+def : InstRW<[ADLPWriteResGroup274], (instregex "^XGETBV$")>;
+
+def ADLPWriteResGroup275 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+ let ResourceCycles = [2, 1];
+ let Latency = 7;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup275], (instregex "^XLAT$")>;
+
+def ADLPWriteResGroup276 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort02_03, ADLPPort06]> {
+ let ResourceCycles = [21, 1, 1, 8];
+ let Latency = 37;
+ let NumMicroOps = 31;
+}
+def : InstRW<[ADLPWriteResGroup276], (instregex "^XRSTOR((S|64|S64)?)$")>;
+
+def ADLPWriteResGroup277 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
+ let Latency = 42;
+ let NumMicroOps = 140;
+}
+def : InstRW<[ADLPWriteResGroup277], (instregex "^XSAVE$")>;
+
+def ADLPWriteResGroup278 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
+ let Latency = 41;
+ let NumMicroOps = 140;
+}
+def : InstRW<[ADLPWriteResGroup278], (instregex "^XSAVE64$")>;
+
+def ADLPWriteResGroup279 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
+ let Latency = 42;
+ let NumMicroOps = 151;
+}
+def : InstRW<[ADLPWriteResGroup279], (instregex "^XSAVEC$")>;
+
+def ADLPWriteResGroup280 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
+ let Latency = 42;
+ let NumMicroOps = 152;
+}
+def : InstRW<[ADLPWriteResGroup280], (instregex "^XSAVEC64$")>;
+
+def ADLPWriteResGroup281 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [25, 35, 52, 27, 4, 1, 10, 1];
+ let Latency = 46;
+ let NumMicroOps = 155;
+}
+def : InstRW<[ADLPWriteResGroup281], (instregex "^XSAVEOPT$")>;
+
+def ADLPWriteResGroup282 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [25, 35, 53, 27, 4, 1, 10, 1];
+ let Latency = 46;
+ let NumMicroOps = 156;
+}
+def : InstRW<[ADLPWriteResGroup282], (instregex "^XSAVEOPT64$")>;
+
+def ADLPWriteResGroup283 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
+ let Latency = 42;
+ let NumMicroOps = 184;
+}
+def : InstRW<[ADLPWriteResGroup283], (instregex "^XSAVES$")>;
+
+def ADLPWriteResGroup284 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let ResourceCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
+ let Latency = 42;
+ let NumMicroOps = 186;
+}
+def : InstRW<[ADLPWriteResGroup284], (instregex "^XSAVES64$")>;
+
+def ADLPWriteResGroup285 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
+ let ResourceCycles = [4, 23, 2, 14, 8, 1, 2];
+ let Latency = 5;
+ let NumMicroOps = 54;
+}
+def : InstRW<[ADLPWriteResGroup285], (instregex "^XSETBV$")>;
+
+}
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s
new file mode 100644
index 0000000000000..dd7ac2734318f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s
@@ -0,0 +1,142 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -timeline -timeline-max-iterations=1 < %s | FileCheck %s -check-prefixes=ALL,NOALIAS
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -timeline -timeline-max-iterations=1 -noalias=false < %s | FileCheck %s -check-prefixes=ALL,YESALIAS
+
+ addq $44, 64(%r14)
+ addq $44, 128(%r14)
+ addq $44, 192(%r14)
+ addq $44, 256(%r14)
+ addq $44, 320(%r14)
+ addq $44, 384(%r14)
+ addq $44, 448(%r14)
+ addq $44, 512(%r14)
+ addq $44, 576(%r14)
+ addq $44, 640(%r14)
+
+# ALL: Iterations: 100
+# ALL-NEXT: Instructions: 1000
+
+# NOALIAS-NEXT: Total Cycles: 1014
+# YESALIAS-NEXT: Total Cycles: 12003
+
+# ALL-NEXT: Total uOps: 4000
+
+# ALL: Dispatch Width: 6
+
+# NOALIAS-NEXT: uOps Per Cycle: 3.94
+# NOALIAS-NEXT: IPC: 0.99
+
+# YESALIAS-NEXT: uOps Per Cycle: 0.33
+# YESALIAS-NEXT: IPC: 0.08
+
+# ALL-NEXT: Block RThroughput: 6.7
+
+# ALL: Instruction Info:
+# ALL-NEXT: [1]: #uOps
+# ALL-NEXT: [2]: Latency
+# ALL-NEXT: [3]: RThroughput
+# ALL-NEXT: [4]: MayLoad
+# ALL-NEXT: [5]: MayStore
+# ALL-NEXT: [6]: HasSideEffects (U)
+
+# ALL: [1] [2] [3] [4] [5] [6] Instructions:
+# ALL-NEXT: 4 12 0.50 * * addq $44, 64(%r14)
+# ALL-NEXT: 4 12 0.50 * * addq $44, 128(%r14)
+# ALL-NEXT: 4 12 0.50 * * addq $44, 192(%r14)
+# ALL-NEXT: 4 12 0.50 * * addq $44, 256(%r14)
+# ALL-NEXT: 4 12 0.50 * * addq $44, 320(%r14)
+# ALL-NEXT: 4 12 0.50 * * addq $44, 384(%r14)
+# ALL-NEXT: 4 12 0.50 * * addq $44, 448(%r14)
+# ALL-NEXT: 4 12 0.50 * * addq $44, 512(%r14)
+# ALL-NEXT: 4 12 0.50 * * addq $44, 576(%r14)
+# ALL-NEXT: 4 12 0.50 * * addq $44, 640(%r14)
+
+# ALL: Resources:
+# ALL-NEXT: [0] - ADLPPort00
+# ALL-NEXT: [1] - ADLPPort01
+# ALL-NEXT: [2] - ADLPPort02
+# ALL-NEXT: [3] - ADLPPort03
+# ALL-NEXT: [4] - ADLPPort04
+# ALL-NEXT: [5] - ADLPPort05
+# ALL-NEXT: [6] - ADLPPort06
+# ALL-NEXT: [7] - ADLPPort07
+# ALL-NEXT: [8] - ADLPPort08
+# ALL-NEXT: [9] - ADLPPort09
+# ALL-NEXT: [10] - ADLPPort10
+# ALL-NEXT: [11] - ADLPPort11
+# ALL-NEXT: [12] - ADLPPortInvalid
+
+# ALL: Resource pressure per iteration:
+# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# ALL-NEXT: 2.00 2.00 3.33 3.33 5.00 2.00 2.00 5.00 5.00 5.00 2.00 3.34 -
+
+# ALL: Resource pressure by instruction:
+# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# ALL-NEXT: - - 0.33 0.33 - - - - 1.00 1.00 1.00 0.34 - addq $44, 64(%r14)
+# ALL-NEXT: - - 0.33 0.34 1.00 - 1.00 1.00 - - - 0.33 - addq $44, 128(%r14)
+# ALL-NEXT: - - 0.34 0.33 - 1.00 - - 1.00 1.00 - 0.33 - addq $44, 192(%r14)
+# ALL-NEXT: - 1.00 0.33 0.33 1.00 - - 1.00 - - - 0.34 - addq $44, 256(%r14)
+# ALL-NEXT: 1.00 - 0.33 0.34 - - - - 1.00 1.00 - 0.33 - addq $44, 320(%r14)
+# ALL-NEXT: - - 0.34 0.33 1.00 - - 1.00 - - 1.00 0.33 - addq $44, 384(%r14)
+# ALL-NEXT: - - 0.33 0.33 - - 1.00 - 1.00 1.00 - 0.34 - addq $44, 448(%r14)
+# ALL-NEXT: - - 0.33 0.34 1.00 1.00 - 1.00 - - - 0.33 - addq $44, 512(%r14)
+# ALL-NEXT: - 1.00 0.34 0.33 - - - - 1.00 1.00 - 0.33 - addq $44, 576(%r14)
+# ALL-NEXT: 1.00 - 0.33 0.33 1.00 - - 1.00 - - - 0.34 - addq $44, 640(%r14)
+
+# ALL: Timeline view:
+
+# NOALIAS-NEXT: 0123456789
+# NOALIAS-NEXT: Index 0123456789 0123
+
+# YESALIAS-NEXT: 0123456789 0123456789 0123456789 01234
+# YESALIAS-NEXT: Index 0123456789 0123456789 0123456789 0123456789
+
+# NOALIAS: [0,0] DeeeeeeeeeeeeER. . . addq $44, 64(%r14)
+# NOALIAS-NEXT: [0,1] .DeeeeeeeeeeeeER . . addq $44, 128(%r14)
+# NOALIAS-NEXT: [0,2] . DeeeeeeeeeeeeER . . addq $44, 192(%r14)
+# NOALIAS-NEXT: [0,3] . DeeeeeeeeeeeeER . . addq $44, 256(%r14)
+# NOALIAS-NEXT: [0,4] . DeeeeeeeeeeeeER . . addq $44, 320(%r14)
+# NOALIAS-NEXT: [0,5] . DeeeeeeeeeeeeER. . addq $44, 384(%r14)
+# NOALIAS-NEXT: [0,6] . .DeeeeeeeeeeeeER . addq $44, 448(%r14)
+# NOALIAS-NEXT: [0,7] . . DeeeeeeeeeeeeER . addq $44, 512(%r14)
+# NOALIAS-NEXT: [0,8] . . DeeeeeeeeeeeeER. addq $44, 576(%r14)
+# NOALIAS-NEXT: [0,9] . . DeeeeeeeeeeeeER addq $44, 640(%r14)
+
+# YESALIAS: [0,0] DeeeeeeeeeeeeER. . . . . . . . . . . . . addq $44, 64(%r14)
+# YESALIAS-NEXT: [0,1] .D===========eeeeeeeeeeeeER . . . . . . . . . . addq $44, 128(%r14)
+# YESALIAS-NEXT: [0,2] . D======================eeeeeeeeeeeeER . . . . . . . . addq $44, 192(%r14)
+# YESALIAS-NEXT: [0,3] . D=================================eeeeeeeeeeeeER . . . . . addq $44, 256(%r14)
+# YESALIAS-NEXT: [0,4] . D============================================eeeeeeeeeeeeER . . . addq $44, 320(%r14)
+# YESALIAS-NEXT: [0,5] . D=======================================================eeeeeeeeeeeeER addq $44, 384(%r14)
+# YESALIAS-NEXT: Truncated display due to cycle limit
+
+# ALL: Average Wait times (based on the timeline view):
+# ALL-NEXT: [0]: Executions
+# ALL-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# ALL-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# ALL-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# ALL: [0] [1] [2] [3]
+# ALL-NEXT: 0. 1 1.0 1.0 0.0 addq $44, 64(%r14)
+
+# NOALIAS-NEXT: 1. 1 1.0 1.0 0.0 addq $44, 128(%r14)
+# NOALIAS-NEXT: 2. 1 1.0 1.0 0.0 addq $44, 192(%r14)
+# NOALIAS-NEXT: 3. 1 1.0 1.0 0.0 addq $44, 256(%r14)
+# NOALIAS-NEXT: 4. 1 1.0 1.0 0.0 addq $44, 320(%r14)
+# NOALIAS-NEXT: 5. 1 1.0 1.0 0.0 addq $44, 384(%r14)
+# NOALIAS-NEXT: 6. 1 1.0 1.0 0.0 addq $44, 448(%r14)
+# NOALIAS-NEXT: 7. 1 1.0 1.0 0.0 addq $44, 512(%r14)
+# NOALIAS-NEXT: 8. 1 1.0 1.0 0.0 addq $44, 576(%r14)
+# NOALIAS-NEXT: 9. 1 1.0 1.0 0.0 addq $44, 640(%r14)
+# NOALIAS-NEXT: 1 1.0 1.0 0.0 <total>
+
+# YESALIAS-NEXT: 1. 1 12.0 0.0 0.0 addq $44, 128(%r14)
+# YESALIAS-NEXT: 2. 1 23.0 0.0 0.0 addq $44, 192(%r14)
+# YESALIAS-NEXT: 3. 1 34.0 0.0 0.0 addq $44, 256(%r14)
+# YESALIAS-NEXT: 4. 1 45.0 0.0 0.0 addq $44, 320(%r14)
+# YESALIAS-NEXT: 5. 1 56.0 0.0 0.0 addq $44, 384(%r14)
+# YESALIAS-NEXT: 6. 1 67.0 0.0 0.0 addq $44, 448(%r14)
+# YESALIAS-NEXT: 7. 1 78.0 0.0 0.0 addq $44, 512(%r14)
+# YESALIAS-NEXT: 8. 1 89.0 0.0 0.0 addq $44, 576(%r14)
+# YESALIAS-NEXT: 9. 1 100.0 0.0 0.0 addq $44, 640(%r14)
+# YESALIAS-NEXT: 1 50.5 0.1 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-adx.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-adx.s
new file mode 100644
index 0000000000000..5a7563d461cd9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-adx.s
@@ -0,0 +1,60 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+adcx %ebx, %ecx
+adcx (%rbx), %ecx
+adcx %rbx, %rcx
+adcx (%rbx), %rcx
+
+adox %ebx, %ecx
+adox (%rbx), %ecx
+adox %rbx, %rcx
+adox (%rbx), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 adcxl %ebx, %ecx
+# CHECK-NEXT: 2 6 0.50 * adcxl (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.50 adcxq %rbx, %rcx
+# CHECK-NEXT: 2 6 0.50 * adcxq (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.50 adoxl %ebx, %ecx
+# CHECK-NEXT: 2 6 0.50 * adoxl (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.50 adoxq %rbx, %rcx
+# CHECK-NEXT: 2 6 0.50 * adoxq (%rbx), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 4.00 - 1.33 1.33 - - 4.00 - - - - 1.33 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcxl %ebx, %ecx
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - adcxl (%rbx), %ecx
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcxq %rbx, %rcx
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - adcxq (%rbx), %rcx
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adoxl %ebx, %ecx
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - adoxl (%rbx), %ecx
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adoxq %rbx, %rcx
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - adoxq (%rbx), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s
new file mode 100644
index 0000000000000..9384488f06781
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s
@@ -0,0 +1,76 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+aesdec %xmm0, %xmm2
+aesdec (%rax), %xmm2
+
+aesdeclast %xmm0, %xmm2
+aesdeclast (%rax), %xmm2
+
+aesenc %xmm0, %xmm2
+aesenc (%rax), %xmm2
+
+aesenclast %xmm0, %xmm2
+aesenclast (%rax), %xmm2
+
+aesimc %xmm0, %xmm2
+aesimc (%rax), %xmm2
+
+aeskeygenassist $22, %xmm0, %xmm2
+aeskeygenassist $22, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.50 aesdec %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * aesdec (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 aesdeclast %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * aesdeclast (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 aesenc %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * aesenc (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 aesenclast %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * aesenclast (%rax), %xmm2
+# CHECK-NEXT: 2 8 1.00 aesimc %xmm0, %xmm2
+# CHECK-NEXT: 3 15 1.00 * aesimc (%rax), %xmm2
+# CHECK-NEXT: 14 7 4.00 aeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 14 12 4.00 * aeskeygenassist $22, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 17.33 10.33 2.00 2.00 - 9.33 2.00 - - - - 2.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - aesdec %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - aesdec (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - aesdeclast %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - aesdeclast (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - aesenc %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - aesenc (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - aesenclast %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - aesenclast (%rax), %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - aesimc %xmm0, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - aesimc (%rax), %xmm2
+# CHECK-NEXT: 5.83 2.33 - - - 4.83 1.00 - - - - - - aeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 5.50 2.00 0.33 0.33 - 4.50 1.00 - - - - 0.33 - aeskeygenassist $22, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s
new file mode 100644
index 0000000000000..dc8ad8e46a777
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s
@@ -0,0 +1,2436 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+vaddpd %xmm0, %xmm1, %xmm2
+vaddpd (%rax), %xmm1, %xmm2
+
+vaddpd %ymm0, %ymm1, %ymm2
+vaddpd (%rax), %ymm1, %ymm2
+
+vaddps %xmm0, %xmm1, %xmm2
+vaddps (%rax), %xmm1, %xmm2
+
+vaddps %ymm0, %ymm1, %ymm2
+vaddps (%rax), %ymm1, %ymm2
+
+vaddsd %xmm0, %xmm1, %xmm2
+vaddsd (%rax), %xmm1, %xmm2
+
+vaddss %xmm0, %xmm1, %xmm2
+vaddss (%rax), %xmm1, %xmm2
+
+vaddsubpd %xmm0, %xmm1, %xmm2
+vaddsubpd (%rax), %xmm1, %xmm2
+
+vaddsubpd %ymm0, %ymm1, %ymm2
+vaddsubpd (%rax), %ymm1, %ymm2
+
+vaddsubps %xmm0, %xmm1, %xmm2
+vaddsubps (%rax), %xmm1, %xmm2
+
+vaddsubps %ymm0, %ymm1, %ymm2
+vaddsubps (%rax), %ymm1, %ymm2
+
+vaesdec %xmm0, %xmm1, %xmm2
+vaesdec (%rax), %xmm1, %xmm2
+
+vaesdeclast %xmm0, %xmm1, %xmm2
+vaesdeclast (%rax), %xmm1, %xmm2
+
+vaesenc %xmm0, %xmm1, %xmm2
+vaesenc (%rax), %xmm1, %xmm2
+
+vaesenclast %xmm0, %xmm1, %xmm2
+vaesenclast (%rax), %xmm1, %xmm2
+
+vaesimc %xmm0, %xmm2
+vaesimc (%rax), %xmm2
+
+vaeskeygenassist $22, %xmm0, %xmm2
+vaeskeygenassist $22, (%rax), %xmm2
+
+vandnpd %xmm0, %xmm1, %xmm2
+vandnpd (%rax), %xmm1, %xmm2
+
+vandnpd %ymm0, %ymm1, %ymm2
+vandnpd (%rax), %ymm1, %ymm2
+
+vandnps %xmm0, %xmm1, %xmm2
+vandnps (%rax), %xmm1, %xmm2
+
+vandnps %ymm0, %ymm1, %ymm2
+vandnps (%rax), %ymm1, %ymm2
+
+vandpd %xmm0, %xmm1, %xmm2
+vandpd (%rax), %xmm1, %xmm2
+
+vandpd %ymm0, %ymm1, %ymm2
+vandpd (%rax), %ymm1, %ymm2
+
+vandps %xmm0, %xmm1, %xmm2
+vandps (%rax), %xmm1, %xmm2
+
+vandps %ymm0, %ymm1, %ymm2
+vandps (%rax), %ymm1, %ymm2
+
+vblendpd $11, %xmm0, %xmm1, %xmm2
+vblendpd $11, (%rax), %xmm1, %xmm2
+
+vblendpd $11, %ymm0, %ymm1, %ymm2
+vblendpd $11, (%rax), %ymm1, %ymm2
+
+vblendps $11, %xmm0, %xmm1, %xmm2
+vblendps $11, (%rax), %xmm1, %xmm2
+
+vblendps $11, %ymm0, %ymm1, %ymm2
+vblendps $11, (%rax), %ymm1, %ymm2
+
+vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+
+vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+
+vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+vblendvps %xmm3, (%rax), %xmm1, %xmm2
+
+vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+vblendvps %ymm3, (%rax), %ymm1, %ymm2
+
+vbroadcastf128 (%rax), %ymm2
+
+vbroadcastsd (%rax), %ymm2
+
+vbroadcastss (%rax), %xmm2
+vbroadcastss (%rax), %ymm2
+
+vcmppd $0, %xmm0, %xmm1, %xmm2
+vcmppd $0, (%rax), %xmm1, %xmm2
+
+vcmppd $0, %ymm0, %ymm1, %ymm2
+vcmppd $0, (%rax), %ymm1, %ymm2
+
+vcmpps $0, %xmm0, %xmm1, %xmm2
+vcmpps $0, (%rax), %xmm1, %xmm2
+
+vcmpps $0, %ymm0, %ymm1, %ymm2
+vcmpps $0, (%rax), %ymm1, %ymm2
+
+vcmpsd $0, %xmm0, %xmm1, %xmm2
+vcmpsd $0, (%rax), %xmm1, %xmm2
+
+vcmpss $0, %xmm0, %xmm1, %xmm2
+vcmpss $0, (%rax), %xmm1, %xmm2
+
+vcomisd %xmm0, %xmm1
+vcomisd (%rax), %xmm1
+
+vcomiss %xmm0, %xmm1
+vcomiss (%rax), %xmm1
+
+vcvtdq2pd %xmm0, %xmm2
+vcvtdq2pd (%rax), %xmm2
+
+vcvtdq2pd %xmm0, %ymm2
+vcvtdq2pd (%rax), %ymm2
+
+vcvtdq2ps %xmm0, %xmm2
+vcvtdq2ps (%rax), %xmm2
+
+vcvtdq2ps %ymm0, %ymm2
+vcvtdq2ps (%rax), %ymm2
+
+vcvtpd2dqx %xmm0, %xmm2
+vcvtpd2dqx (%rax), %xmm2
+
+vcvtpd2dqy %ymm0, %xmm2
+vcvtpd2dqy (%rax), %xmm2
+
+vcvtpd2psx %xmm0, %xmm2
+vcvtpd2psx (%rax), %xmm2
+
+vcvtpd2psy %ymm0, %xmm2
+vcvtpd2psy (%rax), %xmm2
+
+vcvtps2dq %xmm0, %xmm2
+vcvtps2dq (%rax), %xmm2
+
+vcvtps2dq %ymm0, %ymm2
+vcvtps2dq (%rax), %ymm2
+
+vcvtps2pd %xmm0, %xmm2
+vcvtps2pd (%rax), %xmm2
+
+vcvtps2pd %xmm0, %ymm2
+vcvtps2pd (%rax), %ymm2
+
+vcvtsd2si %xmm0, %ecx
+vcvtsd2si %xmm0, %rcx
+vcvtsd2si (%rax), %ecx
+vcvtsd2si (%rax), %rcx
+
+vcvtsd2ss %xmm0, %xmm1, %xmm2
+vcvtsd2ss (%rax), %xmm1, %xmm2
+
+vcvtsi2sdl %ecx, %xmm0, %xmm2
+vcvtsi2sdq %rcx, %xmm0, %xmm2
+vcvtsi2sdl (%rax), %xmm0, %xmm2
+vcvtsi2sdq (%rax), %xmm0, %xmm2
+
+vcvtsi2ssl %ecx, %xmm0, %xmm2
+vcvtsi2ssq %rcx, %xmm0, %xmm2
+vcvtsi2ssl (%rax), %xmm0, %xmm2
+vcvtsi2ssq (%rax), %xmm0, %xmm2
+
+vcvtss2sd %xmm0, %xmm1, %xmm2
+vcvtss2sd (%rax), %xmm1, %xmm2
+
+vcvtss2si %xmm0, %ecx
+vcvtss2si %xmm0, %rcx
+vcvtss2si (%rax), %ecx
+vcvtss2si (%rax), %rcx
+
+vcvttpd2dqx %xmm0, %xmm2
+vcvttpd2dqx (%rax), %xmm2
+
+vcvttpd2dqy %ymm0, %xmm2
+vcvttpd2dqy (%rax), %xmm2
+
+vcvttps2dq %xmm0, %xmm2
+vcvttps2dq (%rax), %xmm2
+
+vcvttps2dq %ymm0, %ymm2
+vcvttps2dq (%rax), %ymm2
+
+vcvttsd2si %xmm0, %ecx
+vcvttsd2si %xmm0, %rcx
+vcvttsd2si (%rax), %ecx
+vcvttsd2si (%rax), %rcx
+
+vcvttss2si %xmm0, %ecx
+vcvttss2si %xmm0, %rcx
+vcvttss2si (%rax), %ecx
+vcvttss2si (%rax), %rcx
+
+vdivpd %xmm0, %xmm1, %xmm2
+vdivpd (%rax), %xmm1, %xmm2
+
+vdivpd %ymm0, %ymm1, %ymm2
+vdivpd (%rax), %ymm1, %ymm2
+
+vdivps %xmm0, %xmm1, %xmm2
+vdivps (%rax), %xmm1, %xmm2
+
+vdivps %ymm0, %ymm1, %ymm2
+vdivps (%rax), %ymm1, %ymm2
+
+vdivsd %xmm0, %xmm1, %xmm2
+vdivsd (%rax), %xmm1, %xmm2
+
+vdivss %xmm0, %xmm1, %xmm2
+vdivss (%rax), %xmm1, %xmm2
+
+vdppd $22, %xmm0, %xmm1, %xmm2
+vdppd $22, (%rax), %xmm1, %xmm2
+
+vdpps $22, %xmm0, %xmm1, %xmm2
+vdpps $22, (%rax), %xmm1, %xmm2
+
+vdpps $22, %ymm0, %ymm1, %ymm2
+vdpps $22, (%rax), %ymm1, %ymm2
+
+vextractf128 $1, %ymm0, %xmm2
+vextractf128 $1, %ymm0, (%rax)
+
+vextractps $1, %xmm0, %rcx
+vextractps $1, %xmm0, (%rax)
+
+vhaddpd %xmm0, %xmm1, %xmm2
+vhaddpd (%rax), %xmm1, %xmm2
+
+vhaddpd %ymm0, %ymm1, %ymm2
+vhaddpd (%rax), %ymm1, %ymm2
+
+vhaddps %xmm0, %xmm1, %xmm2
+vhaddps (%rax), %xmm1, %xmm2
+
+vhaddps %ymm0, %ymm1, %ymm2
+vhaddps (%rax), %ymm1, %ymm2
+
+vhsubpd %xmm0, %xmm1, %xmm2
+vhsubpd (%rax), %xmm1, %xmm2
+
+vhsubpd %ymm0, %ymm1, %ymm2
+vhsubpd (%rax), %ymm1, %ymm2
+
+vhsubps %xmm0, %xmm1, %xmm2
+vhsubps (%rax), %xmm1, %xmm2
+
+vhsubps %ymm0, %ymm1, %ymm2
+vhsubps (%rax), %ymm1, %ymm2
+
+vinsertf128 $1, %xmm0, %ymm1, %ymm2
+vinsertf128 $1, (%rax), %ymm1, %ymm2
+
+vinsertps $1, %xmm0, %xmm1, %xmm2
+vinsertps $1, (%rax), %xmm1, %xmm2
+
+vlddqu (%rax), %xmm2
+vlddqu (%rax), %ymm2
+
+vldmxcsr (%rax)
+
+vmaskmovdqu %xmm0, %xmm1
+
+vmaskmovpd (%rax), %xmm0, %xmm2
+vmaskmovpd (%rax), %ymm0, %ymm2
+
+vmaskmovpd %xmm0, %xmm1, (%rax)
+vmaskmovpd %ymm0, %ymm1, (%rax)
+
+vmaskmovps (%rax), %xmm0, %xmm2
+vmaskmovps (%rax), %ymm0, %ymm2
+
+vmaskmovps %xmm0, %xmm1, (%rax)
+vmaskmovps %ymm0, %ymm1, (%rax)
+
+vmaxpd %xmm0, %xmm1, %xmm2
+vmaxpd (%rax), %xmm1, %xmm2
+
+vmaxpd %ymm0, %ymm1, %ymm2
+vmaxpd (%rax), %ymm1, %ymm2
+
+vmaxps %xmm0, %xmm1, %xmm2
+vmaxps (%rax), %xmm1, %xmm2
+
+vmaxps %ymm0, %ymm1, %ymm2
+vmaxps (%rax), %ymm1, %ymm2
+
+vmaxsd %xmm0, %xmm1, %xmm2
+vmaxsd (%rax), %xmm1, %xmm2
+
+vmaxss %xmm0, %xmm1, %xmm2
+vmaxss (%rax), %xmm1, %xmm2
+
+vminpd %xmm0, %xmm1, %xmm2
+vminpd (%rax), %xmm1, %xmm2
+
+vminpd %ymm0, %ymm1, %ymm2
+vminpd (%rax), %ymm1, %ymm2
+
+vminps %xmm0, %xmm1, %xmm2
+vminps (%rax), %xmm1, %xmm2
+
+vminps %ymm0, %ymm1, %ymm2
+vminps (%rax), %ymm1, %ymm2
+
+vminsd %xmm0, %xmm1, %xmm2
+vminsd (%rax), %xmm1, %xmm2
+
+vminss %xmm0, %xmm1, %xmm2
+vminss (%rax), %xmm1, %xmm2
+
+vmovapd %xmm0, %xmm2
+vmovapd %xmm0, (%rax)
+vmovapd (%rax), %xmm2
+
+vmovapd %ymm0, %ymm2
+vmovapd %ymm0, (%rax)
+vmovapd (%rax), %ymm2
+
+vmovaps %xmm0, %xmm2
+vmovaps %xmm0, (%rax)
+vmovaps (%rax), %xmm2
+
+vmovaps %ymm0, %ymm2
+vmovaps %ymm0, (%rax)
+vmovaps (%rax), %ymm2
+
+vmovd %eax, %xmm2
+vmovd (%rax), %xmm2
+
+vmovd %xmm0, %ecx
+vmovd %xmm0, (%rax)
+
+vmovddup %xmm0, %xmm2
+vmovddup (%rax), %xmm2
+
+vmovddup %ymm0, %ymm2
+vmovddup (%rax), %ymm2
+
+vmovdqa %xmm0, %xmm2
+vmovdqa %xmm0, (%rax)
+vmovdqa (%rax), %xmm2
+
+vmovdqa %ymm0, %ymm2
+vmovdqa %ymm0, (%rax)
+vmovdqa (%rax), %ymm2
+
+vmovdqu %xmm0, %xmm2
+vmovdqu %xmm0, (%rax)
+vmovdqu (%rax), %xmm2
+
+vmovdqu %ymm0, %ymm2
+vmovdqu %ymm0, (%rax)
+vmovdqu (%rax), %ymm2
+
+vmovhlps %xmm0, %xmm1, %xmm2
+vmovlhps %xmm0, %xmm1, %xmm2
+
+vmovhpd %xmm0, (%rax)
+vmovhpd (%rax), %xmm1, %xmm2
+
+vmovhps %xmm0, (%rax)
+vmovhps (%rax), %xmm1, %xmm2
+
+vmovlpd %xmm0, (%rax)
+vmovlpd (%rax), %xmm1, %xmm2
+
+vmovlps %xmm0, (%rax)
+vmovlps (%rax), %xmm1, %xmm2
+
+vmovmskpd %xmm0, %rcx
+vmovmskpd %ymm0, %rcx
+
+vmovmskps %xmm0, %rcx
+vmovmskps %ymm0, %rcx
+
+vmovntdq %xmm0, (%rax)
+vmovntdq %ymm0, (%rax)
+
+vmovntdqa (%rax), %xmm2
+vmovntdqa (%rax), %ymm2
+
+vmovntpd %xmm0, (%rax)
+vmovntpd %ymm0, (%rax)
+
+vmovntps %xmm0, (%rax)
+vmovntps %ymm0, (%rax)
+
+vmovq %xmm0, %xmm2
+
+vmovq %rax, %xmm2
+vmovq (%rax), %xmm2
+
+vmovq %xmm0, %rcx
+vmovq %xmm0, (%rax)
+
+vmovsd %xmm0, %xmm1, %xmm2
+vmovsd %xmm0, (%rax)
+vmovsd (%rax), %xmm2
+
+vmovshdup %xmm0, %xmm2
+vmovshdup (%rax), %xmm2
+
+vmovshdup %ymm0, %ymm2
+vmovshdup (%rax), %ymm2
+
+vmovsldup %xmm0, %xmm2
+vmovsldup (%rax), %xmm2
+
+vmovsldup %ymm0, %ymm2
+vmovsldup (%rax), %ymm2
+
+vmovss %xmm0, %xmm1, %xmm2
+vmovss %xmm0, (%rax)
+vmovss (%rax), %xmm2
+
+vmovupd %xmm0, %xmm2
+vmovupd %xmm0, (%rax)
+vmovupd (%rax), %xmm2
+
+vmovupd %ymm0, %ymm2
+vmovupd %ymm0, (%rax)
+vmovupd (%rax), %ymm2
+
+vmovups %xmm0, %xmm2
+vmovups %xmm0, (%rax)
+vmovups (%rax), %xmm2
+
+vmovups %ymm0, %ymm2
+vmovups %ymm0, (%rax)
+vmovups (%rax), %ymm2
+
+vmpsadbw $1, %xmm0, %xmm1, %xmm2
+vmpsadbw $1, (%rax), %xmm1, %xmm2
+
+vmulpd %xmm0, %xmm1, %xmm2
+vmulpd (%rax), %xmm1, %xmm2
+
+vmulpd %ymm0, %ymm1, %ymm2
+vmulpd (%rax), %ymm1, %ymm2
+
+vmulps %xmm0, %xmm1, %xmm2
+vmulps (%rax), %xmm1, %xmm2
+
+vmulps %ymm0, %ymm1, %ymm2
+vmulps (%rax), %ymm1, %ymm2
+
+vmulsd %xmm0, %xmm1, %xmm2
+vmulsd (%rax), %xmm1, %xmm2
+
+vmulss %xmm0, %xmm1, %xmm2
+vmulss (%rax), %xmm1, %xmm2
+
+vorpd %xmm0, %xmm1, %xmm2
+vorpd (%rax), %xmm1, %xmm2
+
+vorpd %ymm0, %ymm1, %ymm2
+vorpd (%rax), %ymm1, %ymm2
+
+vorps %xmm0, %xmm1, %xmm2
+vorps (%rax), %xmm1, %xmm2
+
+vorps %ymm0, %ymm1, %ymm2
+vorps (%rax), %ymm1, %ymm2
+
+vpabsb %xmm0, %xmm2
+vpabsb (%rax), %xmm2
+
+vpabsd %xmm0, %xmm2
+vpabsd (%rax), %xmm2
+
+vpabsw %xmm0, %xmm2
+vpabsw (%rax), %xmm2
+
+vpackssdw %xmm0, %xmm1, %xmm2
+vpackssdw (%rax), %xmm1, %xmm2
+
+vpacksswb %xmm0, %xmm1, %xmm2
+vpacksswb (%rax), %xmm1, %xmm2
+
+vpackusdw %xmm0, %xmm1, %xmm2
+vpackusdw (%rax), %xmm1, %xmm2
+
+vpackuswb %xmm0, %xmm1, %xmm2
+vpackuswb (%rax), %xmm1, %xmm2
+
+vpaddb %xmm0, %xmm1, %xmm2
+vpaddb (%rax), %xmm1, %xmm2
+
+vpaddd %xmm0, %xmm1, %xmm2
+vpaddd (%rax), %xmm1, %xmm2
+
+vpaddq %xmm0, %xmm1, %xmm2
+vpaddq (%rax), %xmm1, %xmm2
+
+vpaddsb %xmm0, %xmm1, %xmm2
+vpaddsb (%rax), %xmm1, %xmm2
+
+vpaddsw %xmm0, %xmm1, %xmm2
+vpaddsw (%rax), %xmm1, %xmm2
+
+vpaddusb %xmm0, %xmm1, %xmm2
+vpaddusb (%rax), %xmm1, %xmm2
+
+vpaddusw %xmm0, %xmm1, %xmm2
+vpaddusw (%rax), %xmm1, %xmm2
+
+vpaddw %xmm0, %xmm1, %xmm2
+vpaddw (%rax), %xmm1, %xmm2
+
+vpalignr $1, %xmm0, %xmm1, %xmm2
+vpalignr $1, (%rax), %xmm1, %xmm2
+
+vpand %xmm0, %xmm1, %xmm2
+vpand (%rax), %xmm1, %xmm2
+
+vpandn %xmm0, %xmm1, %xmm2
+vpandn (%rax), %xmm1, %xmm2
+
+vpavgb %xmm0, %xmm1, %xmm2
+vpavgb (%rax), %xmm1, %xmm2
+
+vpavgw %xmm0, %xmm1, %xmm2
+vpavgw (%rax), %xmm1, %xmm2
+
+vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+
+vpblendw $11, %xmm0, %xmm1, %xmm2
+vpblendw $11, (%rax), %xmm1, %xmm2
+
+vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+vpclmulqdq $11, (%rax), %xmm1, %xmm2
+
+vpcmpeqb %xmm0, %xmm1, %xmm2
+vpcmpeqb (%rax), %xmm1, %xmm2
+
+vpcmpeqd %xmm0, %xmm1, %xmm2
+vpcmpeqd (%rax), %xmm1, %xmm2
+
+vpcmpeqq %xmm0, %xmm1, %xmm2
+vpcmpeqq (%rax), %xmm1, %xmm2
+
+vpcmpeqw %xmm0, %xmm1, %xmm2
+vpcmpeqw (%rax), %xmm1, %xmm2
+
+vpcmpestri $1, %xmm0, %xmm2
+vpcmpestri $1, (%rax), %xmm2
+
+vpcmpestrm $1, %xmm0, %xmm2
+vpcmpestrm $1, (%rax), %xmm2
+
+vpcmpgtb %xmm0, %xmm1, %xmm2
+vpcmpgtb (%rax), %xmm1, %xmm2
+
+vpcmpgtd %xmm0, %xmm1, %xmm2
+vpcmpgtd (%rax), %xmm1, %xmm2
+
+vpcmpgtq %xmm0, %xmm1, %xmm2
+vpcmpgtq (%rax), %xmm1, %xmm2
+
+vpcmpgtw %xmm0, %xmm1, %xmm2
+vpcmpgtw (%rax), %xmm1, %xmm2
+
+vpcmpistri $1, %xmm0, %xmm2
+vpcmpistri $1, (%rax), %xmm2
+
+vpcmpistrm $1, %xmm0, %xmm2
+vpcmpistrm $1, (%rax), %xmm2
+
+vperm2f128 $1, %ymm0, %ymm1, %ymm2
+vperm2f128 $1, (%rax), %ymm1, %ymm2
+
+vpermilpd $1, %xmm0, %xmm2
+vpermilpd $1, (%rax), %xmm2
+vpermilpd %xmm0, %xmm1, %xmm2
+vpermilpd (%rax), %xmm1, %xmm2
+
+vpermilpd $1, %ymm0, %ymm2
+vpermilpd $1, (%rax), %ymm2
+vpermilpd %ymm0, %ymm1, %ymm2
+vpermilpd (%rax), %ymm1, %ymm2
+
+vpermilps $1, %xmm0, %xmm2
+vpermilps $1, (%rax), %xmm2
+vpermilps %xmm0, %xmm1, %xmm2
+vpermilps (%rax), %xmm1, %xmm2
+
+vpermilps $1, %ymm0, %ymm2
+vpermilps $1, (%rax), %ymm2
+vpermilps %ymm0, %ymm1, %ymm2
+vpermilps (%rax), %ymm1, %ymm2
+
+vpextrb $1, %xmm0, %ecx
+vpextrb $1, %xmm0, (%rax)
+
+vpextrd $1, %xmm0, %ecx
+vpextrd $1, %xmm0, (%rax)
+
+vpextrq $1, %xmm0, %rcx
+vpextrq $1, %xmm0, (%rax)
+
+vpextrw $1, %xmm0, %ecx
+vpextrw $1, %xmm0, (%rax)
+
+vphaddd %xmm0, %xmm1, %xmm2
+vphaddd (%rax), %xmm1, %xmm2
+
+vphaddsw %xmm0, %xmm1, %xmm2
+vphaddsw (%rax), %xmm1, %xmm2
+
+vphaddw %xmm0, %xmm1, %xmm2
+vphaddw (%rax), %xmm1, %xmm2
+
+vphminposuw %xmm0, %xmm2
+vphminposuw (%rax), %xmm2
+
+vphsubd %xmm0, %xmm1, %xmm2
+vphsubd (%rax), %xmm1, %xmm2
+
+vphsubsw %xmm0, %xmm1, %xmm2
+vphsubsw (%rax), %xmm1, %xmm2
+
+vphsubw %xmm0, %xmm1, %xmm2
+vphsubw (%rax), %xmm1, %xmm2
+
+vpinsrb $1, %eax, %xmm1, %xmm2
+vpinsrb $1, (%rax), %xmm1, %xmm2
+
+vpinsrd $1, %eax, %xmm1, %xmm2
+vpinsrd $1, (%rax), %xmm1, %xmm2
+
+vpinsrq $1, %rax, %xmm1, %xmm2
+vpinsrq $1, (%rax), %xmm1, %xmm2
+
+vpinsrw $1, %eax, %xmm1, %xmm2
+vpinsrw $1, (%rax), %xmm1, %xmm2
+
+vpmaddubsw %xmm0, %xmm1, %xmm2
+vpmaddubsw (%rax), %xmm1, %xmm2
+
+vpmaddwd %xmm0, %xmm1, %xmm2
+vpmaddwd (%rax), %xmm1, %xmm2
+
+vpmaxsb %xmm0, %xmm1, %xmm2
+vpmaxsb (%rax), %xmm1, %xmm2
+
+vpmaxsd %xmm0, %xmm1, %xmm2
+vpmaxsd (%rax), %xmm1, %xmm2
+
+vpmaxsw %xmm0, %xmm1, %xmm2
+vpmaxsw (%rax), %xmm1, %xmm2
+
+vpmaxub %xmm0, %xmm1, %xmm2
+vpmaxub (%rax), %xmm1, %xmm2
+
+vpmaxud %xmm0, %xmm1, %xmm2
+vpmaxud (%rax), %xmm1, %xmm2
+
+vpmaxuw %xmm0, %xmm1, %xmm2
+vpmaxuw (%rax), %xmm1, %xmm2
+
+vpminsb %xmm0, %xmm1, %xmm2
+vpminsb (%rax), %xmm1, %xmm2
+
+vpminsd %xmm0, %xmm1, %xmm2
+vpminsd (%rax), %xmm1, %xmm2
+
+vpminsw %xmm0, %xmm1, %xmm2
+vpminsw (%rax), %xmm1, %xmm2
+
+vpminub %xmm0, %xmm1, %xmm2
+vpminub (%rax), %xmm1, %xmm2
+
+vpminud %xmm0, %xmm1, %xmm2
+vpminud (%rax), %xmm1, %xmm2
+
+vpminuw %xmm0, %xmm1, %xmm2
+vpminuw (%rax), %xmm1, %xmm2
+
+vpmovmskb %xmm0, %rcx
+
+vpmovsxbd %xmm0, %xmm2
+vpmovsxbd (%rax), %xmm2
+
+vpmovsxbq %xmm0, %xmm2
+vpmovsxbq (%rax), %xmm2
+
+vpmovsxbw %xmm0, %xmm2
+vpmovsxbw (%rax), %xmm2
+
+vpmovsxdq %xmm0, %xmm2
+vpmovsxdq (%rax), %xmm2
+
+vpmovsxwd %xmm0, %xmm2
+vpmovsxwd (%rax), %xmm2
+
+vpmovsxwq %xmm0, %xmm2
+vpmovsxwq (%rax), %xmm2
+
+vpmovzxbd %xmm0, %xmm2
+vpmovzxbd (%rax), %xmm2
+
+vpmovzxbq %xmm0, %xmm2
+vpmovzxbq (%rax), %xmm2
+
+vpmovzxbw %xmm0, %xmm2
+vpmovzxbw (%rax), %xmm2
+
+vpmovzxdq %xmm0, %xmm2
+vpmovzxdq (%rax), %xmm2
+
+vpmovzxwd %xmm0, %xmm2
+vpmovzxwd (%rax), %xmm2
+
+vpmovzxwq %xmm0, %xmm2
+vpmovzxwq (%rax), %xmm2
+
+vpmuldq %xmm0, %xmm1, %xmm2
+vpmuldq (%rax), %xmm1, %xmm2
+
+vpmulhrsw %xmm0, %xmm1, %xmm2
+vpmulhrsw (%rax), %xmm1, %xmm2
+
+vpmulhuw %xmm0, %xmm1, %xmm2
+vpmulhuw (%rax), %xmm1, %xmm2
+
+vpmulhw %xmm0, %xmm1, %xmm2
+vpmulhw (%rax), %xmm1, %xmm2
+
+vpmulld %xmm0, %xmm1, %xmm2
+vpmulld (%rax), %xmm1, %xmm2
+
+vpmullw %xmm0, %xmm1, %xmm2
+vpmullw (%rax), %xmm1, %xmm2
+
+vpmuludq %xmm0, %xmm1, %xmm2
+vpmuludq (%rax), %xmm1, %xmm2
+
+vpor %xmm0, %xmm1, %xmm2
+vpor (%rax), %xmm1, %xmm2
+
+vpsadbw %xmm0, %xmm1, %xmm2
+vpsadbw (%rax), %xmm1, %xmm2
+
+vpshufb %xmm0, %xmm1, %xmm2
+vpshufb (%rax), %xmm1, %xmm2
+
+vpshufd $1, %xmm0, %xmm2
+vpshufd $1, (%rax), %xmm2
+
+vpshufhw $1, %xmm0, %xmm2
+vpshufhw $1, (%rax), %xmm2
+
+vpshuflw $1, %xmm0, %xmm2
+vpshuflw $1, (%rax), %xmm2
+
+vpsignb %xmm0, %xmm1, %xmm2
+vpsignb (%rax), %xmm1, %xmm2
+
+vpsignd %xmm0, %xmm1, %xmm2
+vpsignd (%rax), %xmm1, %xmm2
+
+vpsignw %xmm0, %xmm1, %xmm2
+vpsignw (%rax), %xmm1, %xmm2
+
+vpslld $1, %xmm0, %xmm2
+vpslld %xmm0, %xmm1, %xmm2
+vpslld (%rax), %xmm1, %xmm2
+
+vpslldq $1, %xmm1, %xmm2
+
+vpsllq $1, %xmm0, %xmm2
+vpsllq %xmm0, %xmm1, %xmm2
+vpsllq (%rax), %xmm1, %xmm2
+
+vpsllw $1, %xmm0, %xmm2
+vpsllw %xmm0, %xmm1, %xmm2
+vpsllw (%rax), %xmm1, %xmm2
+
+vpsrad $1, %xmm0, %xmm2
+vpsrad %xmm0, %xmm1, %xmm2
+vpsrad (%rax), %xmm1, %xmm2
+
+vpsraw $1, %xmm0, %xmm2
+vpsraw %xmm0, %xmm1, %xmm2
+vpsraw (%rax), %xmm1, %xmm2
+
+vpsrld $1, %xmm0, %xmm2
+vpsrld %xmm0, %xmm1, %xmm2
+vpsrld (%rax), %xmm1, %xmm2
+
+vpsrldq $1, %xmm1, %xmm2
+
+vpsrlq $1, %xmm0, %xmm2
+vpsrlq %xmm0, %xmm1, %xmm2
+vpsrlq (%rax), %xmm1, %xmm2
+
+vpsrlw $1, %xmm0, %xmm2
+vpsrlw %xmm0, %xmm1, %xmm2
+vpsrlw (%rax), %xmm1, %xmm2
+
+vpsubb %xmm0, %xmm1, %xmm2
+vpsubb (%rax), %xmm1, %xmm2
+
+vpsubd %xmm0, %xmm1, %xmm2
+vpsubd (%rax), %xmm1, %xmm2
+
+vpsubq %xmm0, %xmm1, %xmm2
+vpsubq (%rax), %xmm1, %xmm2
+
+vpsubsb %xmm0, %xmm1, %xmm2
+vpsubsb (%rax), %xmm1, %xmm2
+
+vpsubsw %xmm0, %xmm1, %xmm2
+vpsubsw (%rax), %xmm1, %xmm2
+
+vpsubusb %xmm0, %xmm1, %xmm2
+vpsubusb (%rax), %xmm1, %xmm2
+
+vpsubusw %xmm0, %xmm1, %xmm2
+vpsubusw (%rax), %xmm1, %xmm2
+
+vpsubw %xmm0, %xmm1, %xmm2
+vpsubw (%rax), %xmm1, %xmm2
+
+vptest %xmm0, %xmm1
+vptest (%rax), %xmm1
+
+vptest %ymm0, %ymm1
+vptest (%rax), %ymm1
+
+vpunpckhbw %xmm0, %xmm1, %xmm2
+vpunpckhbw (%rax), %xmm1, %xmm2
+
+vpunpckhdq %xmm0, %xmm1, %xmm2
+vpunpckhdq (%rax), %xmm1, %xmm2
+
+vpunpckhqdq %xmm0, %xmm1, %xmm2
+vpunpckhqdq (%rax), %xmm1, %xmm2
+
+vpunpckhwd %xmm0, %xmm1, %xmm2
+vpunpckhwd (%rax), %xmm1, %xmm2
+
+vpunpcklbw %xmm0, %xmm1, %xmm2
+vpunpcklbw (%rax), %xmm1, %xmm2
+
+vpunpckldq %xmm0, %xmm1, %xmm2
+vpunpckldq (%rax), %xmm1, %xmm2
+
+vpunpcklqdq %xmm0, %xmm1, %xmm2
+vpunpcklqdq (%rax), %xmm1, %xmm2
+
+vpunpcklwd %xmm0, %xmm1, %xmm2
+vpunpcklwd (%rax), %xmm1, %xmm2
+
+vpxor %xmm0, %xmm1, %xmm2
+vpxor (%rax), %xmm1, %xmm2
+
+vrcpps %xmm0, %xmm2
+vrcpps (%rax), %xmm2
+
+vrcpps %ymm0, %ymm2
+vrcpps (%rax), %ymm2
+
+vrcpss %xmm0, %xmm1, %xmm2
+vrcpss (%rax), %xmm1, %xmm2
+
+vroundpd $1, %xmm0, %xmm2
+vroundpd $1, (%rax), %xmm2
+
+vroundpd $1, %ymm0, %ymm2
+vroundpd $1, (%rax), %ymm2
+
+vroundps $1, %xmm0, %xmm2
+vroundps $1, (%rax), %xmm2
+
+vroundps $1, %ymm0, %ymm2
+vroundps $1, (%rax), %ymm2
+
+vroundsd $1, %xmm0, %xmm1, %xmm2
+vroundsd $1, (%rax), %xmm1, %xmm2
+
+vroundss $1, %xmm0, %xmm1, %xmm2
+vroundss $1, (%rax), %xmm1, %xmm2
+
+vrsqrtps %xmm0, %xmm2
+vrsqrtps (%rax), %xmm2
+
+vrsqrtps %ymm0, %ymm2
+vrsqrtps (%rax), %ymm2
+
+vrsqrtss %xmm0, %xmm1, %xmm2
+vrsqrtss (%rax), %xmm1, %xmm2
+
+vshufpd $1, %xmm0, %xmm1, %xmm2
+vshufpd $1, (%rax), %xmm1, %xmm2
+
+vshufpd $1, %ymm0, %ymm1, %ymm2
+vshufpd $1, (%rax), %ymm1, %ymm2
+
+vshufps $1, %xmm0, %xmm1, %xmm2
+vshufps $1, (%rax), %xmm1, %xmm2
+
+vshufps $1, %ymm0, %ymm1, %ymm2
+vshufps $1, (%rax), %ymm1, %ymm2
+
+vsqrtpd %xmm0, %xmm2
+vsqrtpd (%rax), %xmm2
+
+vsqrtpd %ymm0, %ymm2
+vsqrtpd (%rax), %ymm2
+
+vsqrtps %xmm0, %xmm2
+vsqrtps (%rax), %xmm2
+
+vsqrtps %ymm0, %ymm2
+vsqrtps (%rax), %ymm2
+
+vsqrtsd %xmm0, %xmm1, %xmm2
+vsqrtsd (%rax), %xmm1, %xmm2
+
+vsqrtss %xmm0, %xmm1, %xmm2
+vsqrtss (%rax), %xmm1, %xmm2
+
+vstmxcsr (%rax)
+
+vsubpd %xmm0, %xmm1, %xmm2
+vsubpd (%rax), %xmm1, %xmm2
+
+vsubpd %ymm0, %ymm1, %ymm2
+vsubpd (%rax), %ymm1, %ymm2
+
+vsubps %xmm0, %xmm1, %xmm2
+vsubps (%rax), %xmm1, %xmm2
+
+vsubps %ymm0, %ymm1, %ymm2
+vsubps (%rax), %ymm1, %ymm2
+
+vsubsd %xmm0, %xmm1, %xmm2
+vsubsd (%rax), %xmm1, %xmm2
+
+vsubss %xmm0, %xmm1, %xmm2
+vsubss (%rax), %xmm1, %xmm2
+
+vtestpd %xmm0, %xmm1
+vtestpd (%rax), %xmm1
+
+vtestpd %ymm0, %ymm1
+vtestpd (%rax), %ymm1
+
+vtestps %xmm0, %xmm1
+vtestps (%rax), %xmm1
+
+vtestps %ymm0, %ymm1
+vtestps (%rax), %ymm1
+
+vucomisd %xmm0, %xmm1
+vucomisd (%rax), %xmm1
+
+vucomiss %xmm0, %xmm1
+vucomiss (%rax), %xmm1
+
+vunpckhpd %xmm0, %xmm1, %xmm2
+vunpckhpd (%rax), %xmm1, %xmm2
+
+vunpckhpd %ymm0, %ymm1, %ymm2
+vunpckhpd (%rax), %ymm1, %ymm2
+
+vunpckhps %xmm0, %xmm1, %xmm2
+vunpckhps (%rax), %xmm1, %xmm2
+
+vunpckhps %ymm0, %ymm1, %ymm2
+vunpckhps (%rax), %ymm1, %ymm2
+
+vunpcklpd %xmm0, %xmm1, %xmm2
+vunpcklpd (%rax), %xmm1, %xmm2
+
+vunpcklpd %ymm0, %ymm1, %ymm2
+vunpcklpd (%rax), %ymm1, %ymm2
+
+vunpcklps %xmm0, %xmm1, %xmm2
+vunpcklps (%rax), %xmm1, %xmm2
+
+vunpcklps %ymm0, %ymm1, %ymm2
+vunpcklps (%rax), %ymm1, %ymm2
+
+vxorpd %xmm0, %xmm1, %xmm2
+vxorpd (%rax), %xmm1, %xmm2
+
+vxorpd %ymm0, %ymm1, %ymm2
+vxorpd (%rax), %ymm1, %ymm2
+
+vxorps %xmm0, %xmm1, %xmm2
+vxorps (%rax), %xmm1, %xmm2
+
+vxorps %ymm0, %ymm1, %ymm2
+vxorps (%rax), %ymm1, %ymm2
+
+vzeroall
+vzeroupper
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vaddsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vaddss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vaddsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vaddsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vaddsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vaddsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vaesdec %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vaesdec (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vaesdeclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vaesdeclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vaesenc %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vaesenc (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vaesenclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vaesenclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 8 1.00 vaesimc %xmm0, %xmm2
+# CHECK-NEXT: 3 15 1.00 * vaesimc (%rax), %xmm2
+# CHECK-NEXT: 14 7 4.00 vaeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 14 12 4.00 * vaeskeygenassist $22, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 vandnpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vandnpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vandnpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vandnpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vandnps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vandnps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vandnps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vandnps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vandpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vandpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vandpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vandpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vandps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vandps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vandps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vandps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vblendpd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vblendpd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vblendpd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vblendpd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vblendps $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vblendps $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vblendps $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vblendps $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 3 1.00 vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 3 1.00 vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 3 1.00 vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vblendvps %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 3 1.00 vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vblendvps %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vbroadcastf128 (%rax), %ymm2
+# CHECK-NEXT: 1 8 0.33 * vbroadcastsd (%rax), %ymm2
+# CHECK-NEXT: 1 7 0.33 * vbroadcastss (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.33 * vbroadcastss (%rax), %ymm2
+# CHECK-NEXT: 1 4 0.50 vcmpeqpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcmpeqpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vcmpeqpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vcmpeqpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vcmpeqps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcmpeqps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vcmpeqps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vcmpeqps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vcmpeqsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcmpeqsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vcmpeqss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcmpeqss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vcomisd %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * vcomisd (%rax), %xmm1
+# CHECK-NEXT: 1 3 1.00 vcomiss %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * vcomiss (%rax), %xmm1
+# CHECK-NEXT: 2 5 1.00 vcvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 vcvtdq2pd %xmm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vcvtdq2pd (%rax), %ymm2
+# CHECK-NEXT: 1 4 0.50 vcvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtdq2ps %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vcvtdq2ps (%rax), %ymm2
+# CHECK-NEXT: 2 5 1.00 vcvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 3 12 1.00 * vcvtpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 vcvtpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 3 15 1.00 * vcvtpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 2 5 1.00 vcvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 3 12 1.00 * vcvtpd2psx (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 vcvtpd2ps %ymm0, %xmm2
+# CHECK-NEXT: 3 15 1.00 * vcvtpd2psy (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtps2dq %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vcvtps2dq (%rax), %ymm2
+# CHECK-NEXT: 2 5 1.00 vcvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 vcvtps2pd %xmm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vcvtps2pd (%rax), %ymm2
+# CHECK-NEXT: 2 7 1.00 vcvtsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 7 1.00 vcvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 3 26 1.00 * vcvtsd2si (%rax), %ecx
+# CHECK-NEXT: 3 12 1.00 * vcvtsd2si (%rax), %rcx
+# CHECK-NEXT: 2 5 1.00 vcvtsd2ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 3 12 1.00 * vcvtsd2ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 1.00 vcvtsi2sd %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 2 7 1.00 vcvtsi2sd %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcvtsi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcvtsi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 7 1.00 vcvtsi2ss %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 3 8 2.00 vcvtsi2ss %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcvtsi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 3 12 1.00 * vcvtsi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 5 1.00 vcvtss2sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcvtss2sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 1.00 vcvtss2si %xmm0, %ecx
+# CHECK-NEXT: 3 8 1.00 vcvtss2si %xmm0, %rcx
+# CHECK-NEXT: 3 12 1.00 * vcvtss2si (%rax), %ecx
+# CHECK-NEXT: 3 12 1.00 * vcvtss2si (%rax), %rcx
+# CHECK-NEXT: 2 5 1.00 vcvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 3 12 1.00 * vcvttpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 vcvttpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 3 15 1.00 * vcvttpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvttps2dq %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vcvttps2dq (%rax), %ymm2
+# CHECK-NEXT: 2 7 1.00 vcvttsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 7 1.00 vcvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 3 26 1.00 * vcvttsd2si (%rax), %ecx
+# CHECK-NEXT: 3 12 1.00 * vcvttsd2si (%rax), %rcx
+# CHECK-NEXT: 2 7 1.00 vcvttss2si %xmm0, %ecx
+# CHECK-NEXT: 3 8 1.00 vcvttss2si %xmm0, %rcx
+# CHECK-NEXT: 3 12 1.00 * vcvttss2si (%rax), %ecx
+# CHECK-NEXT: 3 12 1.00 * vcvttss2si (%rax), %rcx
+# CHECK-NEXT: 1 14 1.00 vdivpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 20 1.00 * vdivpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 14 1.00 vdivpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 21 1.00 * vdivpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 vdivps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 18 1.00 * vdivps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 vdivps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 19 1.00 * vdivps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 14 1.00 vdivsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 20 1.00 * vdivsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 vdivss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 18 1.00 * vdivss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 9 1.00 vdppd $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 16 1.00 * vdppd $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 6 14 1.67 vdpps $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 21 1.67 * vdpps $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 6 14 1.67 vdpps $22, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 22 1.67 * vdpps $22, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vextractf128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vextractf128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 2 4 1.00 vextractps $1, %xmm0, %ecx
+# CHECK-NEXT: 3 12 1.00 * vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 5 2.00 vhaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 12 2.00 * vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 5 2.00 vhaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 13 2.00 * vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 5 2.00 vhaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 12 2.00 * vhaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 5 2.00 vhaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 13 2.00 * vhaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 5 2.00 vhsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 12 2.00 * vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 5 2.00 vhsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 13 2.00 * vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 5 2.00 vhsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 12 2.00 * vhsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 5 2.00 vhsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 13 2.00 * vhsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vinsertf128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vinsertf128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vinsertps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vinsertps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 7 0.33 * vlddqu (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.33 * vlddqu (%rax), %ymm2
+# CHECK-NEXT: 3 7 1.00 * * U vldmxcsr (%rax)
+# CHECK-NEXT: 2 1 1.00 * * U vmaskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 2 8 0.33 * vmaskmovpd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.33 * vmaskmovpd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 3 14 1.00 * * vmaskmovpd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 3 14 1.00 * * vmaskmovpd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 2 8 0.33 * vmaskmovps (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.33 * vmaskmovps (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 3 14 1.00 * * vmaskmovps %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 3 14 1.00 * * vmaskmovps %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 4 0.50 vmaxpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vmaxpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vmaxpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmaxpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vmaxps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vmaxps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vmaxps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmaxps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vmaxss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vmaxss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vminpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vminpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vminpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vminpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vminps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vminps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vminps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vminps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vminss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vminss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovapd %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovapd %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovapd (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovapd %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmovapd %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %ymm2
+# CHECK-NEXT: 0 1 0.00 vmovaps %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovaps %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovaps (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovaps %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmovaps %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vmovd %eax, %xmm2
+# CHECK-NEXT: 1 7 0.33 * vmovd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 vmovd %xmm0, %ecx
+# CHECK-NEXT: 2 12 0.50 * vmovd %xmm0, (%rax)
+# CHECK-NEXT: 1 1 1.00 vmovddup %xmm0, %xmm2
+# CHECK-NEXT: 1 7 0.33 * vmovddup (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovddup %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vmovddup (%rax), %ymm2
+# CHECK-NEXT: 0 1 0.00 vmovdqa %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovdqa %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovdqa (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovdqa %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmovdqa %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovdqa (%rax), %ymm2
+# CHECK-NEXT: 0 1 0.00 vmovdqu %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovdqu %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovdqu (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovdqu %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmovdqu %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovdqu (%rax), %ymm2
+# CHECK-NEXT: 1 1 1.00 vmovhlps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovlhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovhpd %xmm0, (%rax)
+# CHECK-NEXT: 2 8 1.00 * vmovhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovhps %xmm0, (%rax)
+# CHECK-NEXT: 2 8 1.00 * vmovhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovlpd %xmm0, (%rax)
+# CHECK-NEXT: 2 8 0.50 * vmovlpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovlps %xmm0, (%rax)
+# CHECK-NEXT: 2 8 0.50 * vmovlps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vmovmskpd %xmm0, %ecx
+# CHECK-NEXT: 1 5 1.00 vmovmskpd %ymm0, %ecx
+# CHECK-NEXT: 1 3 1.00 vmovmskps %xmm0, %ecx
+# CHECK-NEXT: 1 5 1.00 vmovmskps %ymm0, %ecx
+# CHECK-NEXT: 2 521 0.50 * vmovntdq %xmm0, (%rax)
+# CHECK-NEXT: 2 507 0.50 * vmovntdq %ymm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovntdqa (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.33 * vmovntdqa (%rax), %ymm2
+# CHECK-NEXT: 2 473 0.50 * vmovntpd %xmm0, (%rax)
+# CHECK-NEXT: 2 542 0.50 * vmovntpd %ymm0, (%rax)
+# CHECK-NEXT: 2 470 0.50 * vmovntps %xmm0, (%rax)
+# CHECK-NEXT: 2 494 0.50 * vmovntps %ymm0, (%rax)
+# CHECK-NEXT: 1 1 0.33 vmovq %xmm0, %xmm2
+# CHECK-NEXT: 1 3 1.00 vmovq %rax, %xmm2
+# CHECK-NEXT: 1 7 0.33 * vmovq (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 vmovq %xmm0, %rcx
+# CHECK-NEXT: 2 12 0.50 * vmovq %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.33 vmovsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovsd %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovshdup %xmm0, %xmm2
+# CHECK-NEXT: 1 7 0.33 * vmovshdup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovshdup %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vmovshdup (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vmovsldup %xmm0, %xmm2
+# CHECK-NEXT: 1 7 0.33 * vmovsldup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovsldup %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vmovsldup (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.33 vmovss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovss %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovss (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovupd %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovupd %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovupd (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovupd %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmovupd %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %ymm2
+# CHECK-NEXT: 0 1 0.00 vmovups %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vmovups %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovups (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 vmovups %ymm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmovups %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %ymm2
+# CHECK-NEXT: 2 4 1.00 vmpsadbw $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 3 11 1.00 * vmpsadbw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vmulpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vmulpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vmulpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmulpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vmulps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vmulps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vmulps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vmulsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vmulsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vmulss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vmulss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpabsb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpabsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpabsd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpabsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpabsw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpabsw (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 vpackssdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 1.00 * vpackssdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpacksswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 1.00 * vpacksswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpackusdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 1.00 * vpackusdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpackuswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 1.00 * vpackuswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpaddb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpaddb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpaddq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpaddq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpaddsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpaddsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpaddusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpaddusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpaddusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpaddusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpalignr $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vpalignr $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpand %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpand (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpandn %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpandn (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpavgb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpavgb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpavgw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpavgw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 3 1.00 vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpblendw $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpblendw $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 1.00 * vpclmulqdq $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpeqb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpeqd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpeqq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpeqw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 8 16 3.00 vpcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 31 3.00 * vpcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: 9 16 3.00 vpcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 9 17 3.00 * vpcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpgtb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpgtd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpcmpgtq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 1.00 * vpcmpgtq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpgtw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 11 3.00 vpcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 4 31 3.00 * vpcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: 3 11 3.00 vpcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 4 16 3.00 * vpcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 vperm2f128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vperm2f128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpermilpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vpermilpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 vpermilpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vpermilpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpermilpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 9 1.00 * vpermilpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 1.00 vpermilpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 1.00 * vpermilpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpermilps $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vpermilps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 vpermilps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vpermilps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpermilps $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 9 1.00 * vpermilps $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 1.00 vpermilps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 1.00 * vpermilps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 4 1.00 vpextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 3 19 0.50 * vpextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 4 1.00 vpextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 3 12 0.50 * vpextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 4 1.00 vpextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 3 12 0.50 * vpextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 4 1.00 vpextrw $1, %xmm0, %ecx
+# CHECK-NEXT: 3 19 0.50 * vpextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 2 1.00 vphaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 2 1.00 vphaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vphaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 2 1.00 vphaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vphminposuw %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * vphminposuw (%rax), %xmm2
+# CHECK-NEXT: 3 2 1.00 vphsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 2 1.00 vphsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vphsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 2 1.00 vphsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 9 1.00 * vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 4 1.00 vpinsrb $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpinsrb $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 4 1.00 vpinsrd $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpinsrd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 4 1.00 vpinsrq $1, %rax, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpinsrq $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 4 1.00 vpinsrw $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpinsrw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vpmaddubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 13 0.50 * vpmaddubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vpmaddwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 13 0.50 * vpmaddwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmaxsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmaxsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmaxsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmaxsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmaxub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmaxub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmaxud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmaxud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmaxuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmaxuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpminsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpminsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpminsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpminsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpminub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpminub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpminud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpminud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpminuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpminuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpmovmskb %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.50 vpmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovsxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovsxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovsxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovsxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovsxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovsxwq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovzxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovzxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovzxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovzxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovzxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 vpmuldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 13 0.50 * vpmuldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vpmulhrsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 13 0.50 * vpmulhrsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vpmulhuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 13 0.50 * vpmulhuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vpmulhw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 13 0.50 * vpmulhw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 1.00 vpmulld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 3 18 1.00 * vpmulld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vpmullw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 13 0.50 * vpmullw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vpmuludq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 13 0.50 * vpmuludq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpsadbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 1.00 * vpsadbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpshufb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpshufd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsignb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsignb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsignd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsignd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsignw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsignw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpslld $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.67 vpslld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpslld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpslldq $1, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllq $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.67 vpsllq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsllq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.67 vpsllw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsllw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrad $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.67 vpsrad %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsrad (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsraw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.67 vpsraw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsraw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrld $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.67 vpsrld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsrld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlq $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.67 vpsrlq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsrlq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 2 0.67 vpsrlw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsrlw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpsubb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpsubb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpsubq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpsubq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsubsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsubsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsubusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsubusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsubusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsubusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 4 1.00 vptest %xmm0, %xmm1
+# CHECK-NEXT: 3 9 1.00 * vptest (%rax), %xmm1
+# CHECK-NEXT: 2 6 1.00 vptest %ymm0, %ymm1
+# CHECK-NEXT: 3 12 1.00 * vptest (%rax), %ymm1
+# CHECK-NEXT: 1 1 0.50 vpunpckhbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckhbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckhdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckhqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckhwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpcklbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpcklqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpunpcklwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpxor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpxor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vrcpps %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * vrcpps (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 vrcpps %ymm0, %ymm2
+# CHECK-NEXT: 2 12 1.00 * vrcpps (%rax), %ymm2
+# CHECK-NEXT: 1 4 1.00 vrcpss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 1.00 * vrcpss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 8 1.00 vroundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 15 1.00 * vroundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 2 8 1.00 vroundpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 3 16 1.00 * vroundpd $1, (%rax), %ymm2
+# CHECK-NEXT: 2 8 1.00 vroundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 15 1.00 * vroundps $1, (%rax), %xmm2
+# CHECK-NEXT: 2 8 1.00 vroundps $1, %ymm0, %ymm2
+# CHECK-NEXT: 3 16 1.00 * vroundps $1, (%rax), %ymm2
+# CHECK-NEXT: 2 8 1.00 vroundsd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 3 15 1.00 * vroundsd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 8 1.00 vroundss $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 3 15 1.00 * vroundss $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vrsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * vrsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 vrsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 2 12 1.00 * vrsqrtps (%rax), %ymm2
+# CHECK-NEXT: 1 4 1.00 vrsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 1.00 * vrsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufpd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vshufpd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufpd $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vshufpd $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vshufps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vshufps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufps $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vshufps $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 18 1.00 vsqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 2 24 1.00 * vsqrtpd (%rax), %xmm2
+# CHECK-NEXT: 1 18 1.00 vsqrtpd %ymm0, %ymm2
+# CHECK-NEXT: 2 25 1.00 * vsqrtpd (%rax), %ymm2
+# CHECK-NEXT: 1 12 1.00 vsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 2 19 1.00 * vsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 12 1.00 vsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 2 20 1.00 * vsqrtps (%rax), %ymm2
+# CHECK-NEXT: 1 18 1.00 vsqrtsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 24 1.00 * vsqrtsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 12 1.00 vsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 19 1.00 * vsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 12 1.00 * U vstmxcsr (%rax)
+# CHECK-NEXT: 1 3 0.50 vsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vsubsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vsubsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vsubss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vtestpd %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * vtestpd (%rax), %xmm1
+# CHECK-NEXT: 1 5 1.00 vtestpd %ymm0, %ymm1
+# CHECK-NEXT: 2 11 1.00 * vtestpd (%rax), %ymm1
+# CHECK-NEXT: 1 3 1.00 vtestps %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * vtestps (%rax), %xmm1
+# CHECK-NEXT: 1 5 1.00 vtestps %ymm0, %ymm1
+# CHECK-NEXT: 2 11 1.00 * vtestps (%rax), %ymm1
+# CHECK-NEXT: 1 3 1.00 vucomisd %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * vucomisd (%rax), %xmm1
+# CHECK-NEXT: 1 3 1.00 vucomiss %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * vucomiss (%rax), %xmm1
+# CHECK-NEXT: 1 1 1.00 vunpckhpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vunpckhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vunpckhpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 1.00 * vunpckhpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vunpckhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vunpckhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vunpckhps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 1.00 * vunpckhps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vunpcklpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vunpcklpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vunpcklpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 1.00 * vunpcklpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vunpcklps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vunpcklps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vunpcklps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 1.00 * vunpcklps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vxorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vxorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vxorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vxorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vxorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vxorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vxorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vxorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 10 16 3.00 U vzeroall
+# CHECK-NEXT: 0 0 0.00 U vzeroupper
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 310.90 275.73 107.33 107.33 19.50 277.73 8.90 18.83 18.50 18.50 0.73 107.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vaddsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vaddsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vaddss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vaddss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vaddsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vaddsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vaddsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vaddsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vaddsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vaddsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vaddsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vaddsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vaesdec %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vaesdec (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vaesdeclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vaesdeclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vaesenc %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vaesenc (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vaesenclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vaesenclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - vaesimc %xmm0, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - vaesimc (%rax), %xmm2
+# CHECK-NEXT: 5.83 2.33 - - - 4.83 1.00 - - - - - - vaeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 5.50 2.00 0.33 0.33 - 4.50 1.00 - - - - 0.33 - vaeskeygenassist $22, (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vandnpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vandnpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vandnpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vandnpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vandnps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vandnps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vandnps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vandnps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vandpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vandpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vandpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vandpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vandps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vandps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vandps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vandps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vblendpd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vblendpd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vblendpd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vblendpd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vblendps $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vblendps $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vblendps $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vblendps $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1.00 1.00 - - - 1.00 - - - - - - - vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - 1.00 - - - - - 0.33 - vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - 1.00 - - - - - - - vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - 1.00 - - - - - 0.33 - vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1.00 1.00 - - - 1.00 - - - - - - - vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - 1.00 - - - - - 0.33 - vblendvps %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - 1.00 - - - - - - - vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - 1.00 - - - - - 0.33 - vblendvps %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vbroadcastf128 (%rax), %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vbroadcastsd (%rax), %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vbroadcastss (%rax), %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vbroadcastss (%rax), %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vcmpeqpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcmpeqpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vcmpeqpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcmpeqpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vcmpeqps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcmpeqps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vcmpeqps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcmpeqps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vcmpeqsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcmpeqsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vcmpeqss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcmpeqss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vcomisd %xmm0, %xmm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vcomisd (%rax), %xmm1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vcomiss %xmm0, %xmm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vcomiss (%rax), %xmm1
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtdq2pd %xmm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtdq2pd (%rax), %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vcvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vcvtdq2ps %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtdq2ps (%rax), %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - vcvtpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - vcvtpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - vcvtpd2psx (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtpd2ps %ymm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - vcvtpd2psy (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vcvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vcvtps2dq %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtps2dq (%rax), %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtps2pd %xmm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtps2pd (%rax), %ymm2
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - vcvtsd2si %xmm0, %ecx
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - vcvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtsd2si (%rax), %ecx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtsd2si (%rax), %rcx
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtsd2ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - vcvtsd2ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtsi2sd %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtsi2sd %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtsi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtsi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtsi2ss %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 2.00 - - - - - - - vcvtsi2ss %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtsi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - vcvtsi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtss2sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtss2sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - vcvtss2si %xmm0, %ecx
+# CHECK-NEXT: 1.50 0.50 - - - 1.00 - - - - - - - vcvtss2si %xmm0, %rcx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtss2si (%rax), %ecx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtss2si (%rax), %rcx
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - vcvttpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvttpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - vcvttpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vcvttps2dq %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvttps2dq (%rax), %ymm2
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - vcvttsd2si %xmm0, %ecx
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - vcvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvttsd2si (%rax), %ecx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvttsd2si (%rax), %rcx
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - vcvttss2si %xmm0, %ecx
+# CHECK-NEXT: 1.50 0.50 - - - 1.00 - - - - - - - vcvttss2si %xmm0, %rcx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvttss2si (%rax), %ecx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvttss2si (%rax), %rcx
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vdivpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vdivpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vdivpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vdivpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vdivps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vdivps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vdivps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vdivps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vdivsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vdivsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vdivss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vdivss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.50 - - - 0.50 - - - - - - - vdppd $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.50 0.33 0.33 - 0.50 - - - - - 0.33 - vdppd $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.50 2.00 - - - 2.00 0.50 - - - - - - vdpps $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.50 2.00 0.33 0.33 - 2.00 0.50 - - - - 0.33 - vdpps $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.50 2.00 - - - 2.00 0.50 - - - - - - vdpps $22, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1.50 2.00 0.33 0.33 - 2.00 0.50 - - - - 0.33 - vdpps $22, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vextractf128 $1, %ymm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vextractf128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - vextractps $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - 0.50 1.00 - 0.50 0.50 0.50 - - - vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: - 0.50 - - - 2.50 - - - - - - - vhaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 2.50 - - - - - 0.33 - vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 2.50 - - - - - - - vhaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 2.50 - - - - - 0.33 - vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 2.50 - - - - - - - vhaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 2.50 - - - - - 0.33 - vhaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 2.50 - - - - - - - vhaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 2.50 - - - - - 0.33 - vhaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 2.50 - - - - - - - vhsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 2.50 - - - - - 0.33 - vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 2.50 - - - - - - - vhsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 2.50 - - - - - 0.33 - vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 2.50 - - - - - - - vhsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 2.50 - - - - - 0.33 - vhsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 2.50 - - - - - - - vhsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 2.50 - - - - - 0.33 - vhsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vinsertf128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vinsertf128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vinsertps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vinsertps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vlddqu (%rax), %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vlddqu (%rax), %ymm2
+# CHECK-NEXT: 1.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - vldmxcsr (%rax)
+# CHECK-NEXT: - - 0.33 0.33 1.00 - - 0.33 - - - - - vmaskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vmaskmovpd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vmaskmovpd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 1.00 - - - 0.50 - - 0.50 0.50 0.50 - - - vmaskmovpd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 1.00 - - - 0.50 - - 0.50 0.50 0.50 - - - vmaskmovpd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vmaskmovps (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vmaskmovps (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 1.00 - - - 0.50 - - 0.50 0.50 0.50 - - - vmaskmovps %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 1.00 - - - 0.50 - - 0.50 0.50 0.50 - - - vmaskmovps %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vmaxpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vmaxpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vmaxpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vmaxpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vmaxps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vmaxps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vmaxps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vmaxps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vmaxss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vmaxss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vminpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vminpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vminpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vminpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vminps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vminps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vminps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vminps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vminss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vminss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - vmovapd %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovapd %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovapd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - vmovapd %ymm0, %ymm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovapd %ymm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovapd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - vmovaps %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovaps %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovaps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - vmovaps %ymm0, %ymm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovaps %ymm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovaps (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vmovd %eax, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovd (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vmovd %xmm0, %ecx
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vmovddup %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovddup (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vmovddup %ymm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovddup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - vmovdqa %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovdqa %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - vmovdqa %ymm0, %ymm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovdqa %ymm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovdqa (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - vmovdqu %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovdqu %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovdqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - vmovdqu %ymm0, %ymm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovdqu %ymm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovdqu (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vmovhlps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vmovlhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovhpd %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vmovhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovhps %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vmovhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovlpd %xmm0, (%rax)
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vmovlpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovlps %xmm0, (%rax)
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vmovlps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vmovmskpd %xmm0, %ecx
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vmovmskpd %ymm0, %ecx
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vmovmskps %xmm0, %ecx
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vmovmskps %ymm0, %ecx
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovntdq %xmm0, (%rax)
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovntdq %ymm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovntdqa (%rax), %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovntdqa (%rax), %ymm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovntpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovntpd %ymm0, (%rax)
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovntps %xmm0, (%rax)
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovntps %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vmovq %rax, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovq (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vmovq %xmm0, %rcx
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovq %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovsd %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovsd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vmovshdup %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovshdup (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vmovshdup %ymm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovshdup (%rax), %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vmovsldup %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovsldup (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vmovsldup %ymm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovsldup (%rax), %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovss %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - vmovupd %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovupd %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovupd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - vmovupd %ymm0, %ymm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovupd %ymm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovupd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - vmovups %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovups %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovups (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - vmovups %ymm0, %ymm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovups %ymm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovups (%rax), %ymm2
+# CHECK-NEXT: - 0.50 - - - 1.50 - - - - - - - vmpsadbw $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 1.50 - - - - - 0.33 - vmpsadbw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vmulpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vmulpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vmulpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vmulpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vmulps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vmulps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vmulps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vmulsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vmulsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vmulss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vmulss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpabsb %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpabsb (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpabsd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpabsd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpabsw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpabsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpackssdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpackssdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpacksswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpacksswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpackusdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpackusdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpackuswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpackuswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpaddb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpaddb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpaddq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpaddq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpaddsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpaddsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpaddusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpaddusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpaddusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpaddusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpalignr $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpalignr $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpand %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpand (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpandn %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpandn (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpavgb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpavgb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpavgw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpavgw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - 1.00 - - - - - - - vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - 1.00 - - - - - 0.33 - vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpblendw $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpblendw $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpclmulqdq $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpeqb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpeqb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpeqd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpeqd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpeqq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpeqq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpeqw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpeqw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4.17 1.67 - - - 1.67 0.50 - - - - - - vpcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 3.83 1.33 0.33 0.33 - 1.33 0.50 - - - - 0.33 - vpcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: 4.50 2.00 - - - 2.00 0.50 - - - - - - vpcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 4.17 1.67 0.33 0.33 - 1.67 0.50 - - - - 0.33 - vpcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpgtb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpgtb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpgtd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpgtd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpcmpgtq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpcmpgtq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpgtw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpgtw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3.00 - - - - - - - - - - - - vpcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 3.00 - 0.33 0.33 - - - - - - - 0.33 - vpcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: 3.00 - - - - - - - - - - - - vpcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 3.00 - 0.33 0.33 - - - - - - - 0.33 - vpcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vperm2f128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vperm2f128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpermilpd $1, %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpermilpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpermilpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpermilpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpermilpd $1, %ymm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpermilpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpermilpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpermilpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpermilps $1, %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpermilps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpermilps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpermilps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpermilps $1, %ymm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpermilps $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpermilps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpermilps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1.00 0.50 - - - 0.50 - - - - - - - vpextrb $1, %xmm0, %ecx
+# CHECK-NEXT: - 0.50 - - 0.50 0.50 - 0.50 0.50 0.50 - - - vpextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 1.00 0.50 - - - 0.50 - - - - - - - vpextrd $1, %xmm0, %ecx
+# CHECK-NEXT: - 0.50 - - 0.50 0.50 - 0.50 0.50 0.50 - - - vpextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 1.00 0.50 - - - 0.50 - - - - - - - vpextrq $1, %xmm0, %rcx
+# CHECK-NEXT: - 0.50 - - 0.50 0.50 - 0.50 0.50 0.50 - - - vpextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 1.00 0.50 - - - 0.50 - - - - - - - vpextrw $1, %xmm0, %ecx
+# CHECK-NEXT: - 0.50 - - 0.50 0.50 - 0.50 0.50 0.50 - - - vpextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 0.33 1.33 - - - 1.33 - - - - - - - vphaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 1.33 0.33 0.33 - 1.33 - - - - - 0.33 - vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 1.50 - - - 1.00 - - - - - - - vphaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 1.50 0.33 0.33 - 1.00 - - - - - 0.33 - vphaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 1.33 - - - 1.33 - - - - - - - vphaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 1.33 0.33 0.33 - 1.33 - - - - - 0.33 - vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vphminposuw %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vphminposuw (%rax), %xmm2
+# CHECK-NEXT: 0.33 1.33 - - - 1.33 - - - - - - - vphsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 1.33 0.33 0.33 - 1.33 - - - - - 0.33 - vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 1.50 - - - 1.00 - - - - - - - vphsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 1.50 0.33 0.33 - 1.00 - - - - - 0.33 - vphsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 1.33 - - - 1.33 - - - - - - - vphsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 1.33 0.33 0.33 - 1.33 - - - - - 0.33 - vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 1.50 - - - - - - - vpinsrb $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpinsrb $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 1.50 - - - - - - - vpinsrd $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpinsrd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 1.50 - - - - - - - vpinsrq $1, %rax, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpinsrq $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 1.50 - - - - - - - vpinsrw $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpinsrw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaddubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaddubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaddwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaddwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaxsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaxsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaxsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaxsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaxub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaxub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaxud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaxud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaxuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaxuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpminsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpminsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpminsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpminsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpminub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpminub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpminud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpminud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpminuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpminuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vpmovmskb %xmm0, %ecx
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpmovsxbd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpmovsxbq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpmovsxbw (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpmovsxdq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpmovsxwd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpmovsxwq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpmovzxbd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpmovzxbq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpmovzxbw (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpmovzxdq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpmovzxwd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmuldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmuldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmulhrsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmulhrsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmulhuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmulhuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmulhw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmulhw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - vpmulld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - vpmulld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmullw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmullw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmuludq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmuludq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsadbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpsadbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpshufb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpshufb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpshufd $1, (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsignb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsignb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsignd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsignd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsignw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsignw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpslld $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - vpslld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpslld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpslldq $1, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsllq $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - vpsllq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsllq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsllw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - vpsllw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsllw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsrad $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - vpsrad %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsrad (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsraw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - vpsraw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsraw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsrld $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - vpsrld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsrld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpsrldq $1, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsrlq $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - vpsrlq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsrlq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsrlw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - vpsrlw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsrlw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpsubb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpsubb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpsubq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpsubq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsubsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsubsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsubusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsubusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsubusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsubusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - vptest %xmm0, %xmm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - 1.00 - - - - - 0.33 - vptest (%rax), %xmm1
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - vptest %ymm0, %ymm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - 1.00 - - - - - 0.33 - vptest (%rax), %ymm1
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpckhbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpckhbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpckhdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpckhdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpckhqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpckhqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpckhwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpckhwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpcklbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpcklbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpckldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpckldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpcklqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpcklqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpcklwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpcklwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpxor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpxor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vrcpps %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vrcpps (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vrcpps %ymm0, %ymm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vrcpps (%rax), %ymm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vrcpss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vrcpss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - vroundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - vroundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - vroundpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - vroundpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - vroundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - vroundps $1, (%rax), %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - vroundps $1, %ymm0, %ymm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - vroundps $1, (%rax), %ymm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - vroundsd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - vroundsd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - vroundss $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - vroundss $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vrsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vrsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vrsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vrsqrtps (%rax), %ymm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vrsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vrsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vshufpd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vshufpd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vshufpd $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vshufpd $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vshufps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vshufps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vshufps $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vshufps $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vsqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vsqrtpd (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vsqrtpd %ymm0, %ymm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vsqrtpd (%rax), %ymm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vsqrtps (%rax), %ymm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vsqrtsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vsqrtsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - vstmxcsr (%rax)
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vsubsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vsubsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vsubss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vsubss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vtestpd %xmm0, %xmm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vtestpd (%rax), %xmm1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vtestpd %ymm0, %ymm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vtestpd (%rax), %ymm1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vtestps %xmm0, %xmm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vtestps (%rax), %xmm1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vtestps %ymm0, %ymm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vtestps (%rax), %ymm1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vucomisd %xmm0, %xmm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vucomisd (%rax), %xmm1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vucomiss %xmm0, %xmm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vucomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vunpckhpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vunpckhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vunpckhpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vunpckhpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vunpckhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vunpckhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vunpckhps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vunpckhps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vunpcklpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vunpcklpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vunpcklpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vunpcklpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vunpcklps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vunpcklps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vunpcklps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vunpcklps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vxorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vxorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vxorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vxorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vxorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vxorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vxorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vxorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2.23 4.07 - - - 1.07 1.90 - - - 0.73 - - vzeroall
+# CHECK-NEXT: - - - - - - - - - - - - - vzeroupper
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s
new file mode 100644
index 0000000000000..96f66d1aad6c5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s
@@ -0,0 +1,1086 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+vbroadcasti128 (%rax), %ymm0
+
+vbroadcastsd %xmm0, %ymm0
+vbroadcastss %xmm0, %ymm0
+
+vextracti128 $1, %ymm0, %xmm2
+vextracti128 $1, %ymm0, (%rax)
+
+vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+
+vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+
+vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+
+vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+
+vinserti128 $1, %xmm0, %ymm1, %ymm2
+vinserti128 $1, (%rax), %ymm1, %ymm2
+
+vmovntdqa (%rax), %ymm0
+
+vmpsadbw $1, %ymm0, %ymm1, %ymm2
+vmpsadbw $1, (%rax), %ymm1, %ymm2
+
+vpabsb %ymm0, %ymm2
+vpabsb (%rax), %ymm2
+
+vpabsd %ymm0, %ymm2
+vpabsd (%rax), %ymm2
+
+vpabsw %ymm0, %ymm2
+vpabsw (%rax), %ymm2
+
+vpackssdw %ymm0, %ymm1, %ymm2
+vpackssdw (%rax), %ymm1, %ymm2
+
+vpacksswb %ymm0, %ymm1, %ymm2
+vpacksswb (%rax), %ymm1, %ymm2
+
+vpackusdw %ymm0, %ymm1, %ymm2
+vpackusdw (%rax), %ymm1, %ymm2
+
+vpackuswb %ymm0, %ymm1, %ymm2
+vpackuswb (%rax), %ymm1, %ymm2
+
+vpaddb %ymm0, %ymm1, %ymm2
+vpaddb (%rax), %ymm1, %ymm2
+
+vpaddd %ymm0, %ymm1, %ymm2
+vpaddd (%rax), %ymm1, %ymm2
+
+vpaddq %ymm0, %ymm1, %ymm2
+vpaddq (%rax), %ymm1, %ymm2
+
+vpaddsb %ymm0, %ymm1, %ymm2
+vpaddsb (%rax), %ymm1, %ymm2
+
+vpaddsw %ymm0, %ymm1, %ymm2
+vpaddsw (%rax), %ymm1, %ymm2
+
+vpaddusb %ymm0, %ymm1, %ymm2
+vpaddusb (%rax), %ymm1, %ymm2
+
+vpaddusw %ymm0, %ymm1, %ymm2
+vpaddusw (%rax), %ymm1, %ymm2
+
+vpaddw %ymm0, %ymm1, %ymm2
+vpaddw (%rax), %ymm1, %ymm2
+
+vpalignr $1, %ymm0, %ymm1, %ymm2
+vpalignr $1, (%rax), %ymm1, %ymm2
+
+vpand %ymm0, %ymm1, %ymm2
+vpand (%rax), %ymm1, %ymm2
+
+vpandn %ymm0, %ymm1, %ymm2
+vpandn (%rax), %ymm1, %ymm2
+
+vpavgb %ymm0, %ymm1, %ymm2
+vpavgb (%rax), %ymm1, %ymm2
+
+vpavgw %ymm0, %ymm1, %ymm2
+vpavgw (%rax), %ymm1, %ymm2
+
+vpblendd $11, %xmm0, %xmm1, %xmm2
+vpblendd $11, (%rax), %xmm1, %xmm2
+
+vpblendd $11, %ymm0, %ymm1, %ymm2
+vpblendd $11, (%rax), %ymm1, %ymm2
+
+vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+
+vpblendw $11, %ymm0, %ymm1, %ymm2
+vpblendw $11, (%rax), %ymm1, %ymm2
+
+vpbroadcastb %xmm0, %xmm0
+vpbroadcastb (%rax), %xmm0
+
+vpbroadcastb %xmm0, %ymm0
+vpbroadcastb (%rax), %ymm0
+
+vpbroadcastd %xmm0, %xmm0
+vpbroadcastd (%rax), %xmm0
+
+vpbroadcastd %xmm0, %ymm0
+vpbroadcastd (%rax), %ymm0
+
+vpbroadcastq %xmm0, %xmm0
+vpbroadcastq (%rax), %xmm0
+
+vpbroadcastq %xmm0, %ymm0
+vpbroadcastq (%rax), %ymm0
+
+vpbroadcastw %xmm0, %xmm0
+vpbroadcastw (%rax), %xmm0
+
+vpbroadcastw %xmm0, %ymm0
+vpbroadcastw (%rax), %ymm0
+
+vpcmpeqb %ymm0, %ymm1, %ymm2
+vpcmpeqb (%rax), %ymm1, %ymm2
+
+vpcmpeqd %ymm0, %ymm1, %ymm2
+vpcmpeqd (%rax), %ymm1, %ymm2
+
+vpcmpeqq %ymm0, %ymm1, %ymm2
+vpcmpeqq (%rax), %ymm1, %ymm2
+
+vpcmpeqw %ymm0, %ymm1, %ymm2
+vpcmpeqw (%rax), %ymm1, %ymm2
+
+vpcmpgtb %ymm0, %ymm1, %ymm2
+vpcmpgtb (%rax), %ymm1, %ymm2
+
+vpcmpgtd %ymm0, %ymm1, %ymm2
+vpcmpgtd (%rax), %ymm1, %ymm2
+
+vpcmpgtq %ymm0, %ymm1, %ymm2
+vpcmpgtq (%rax), %ymm1, %ymm2
+
+vpcmpgtw %ymm0, %ymm1, %ymm2
+vpcmpgtw (%rax), %ymm1, %ymm2
+
+vperm2i128 $1, %ymm0, %ymm1, %ymm2
+vperm2i128 $1, (%rax), %ymm1, %ymm2
+
+vpermd %ymm0, %ymm1, %ymm2
+vpermd (%rax), %ymm1, %ymm2
+
+vpermpd $1, %ymm0, %ymm2
+vpermpd $1, (%rax), %ymm2
+
+vpermps %ymm0, %ymm1, %ymm2
+vpermps (%rax), %ymm1, %ymm2
+
+vpermq $1, %ymm0, %ymm2
+vpermq $1, (%rax), %ymm2
+
+vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+
+vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+
+vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+
+vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+
+vphaddd %ymm0, %ymm1, %ymm2
+vphaddd (%rax), %ymm1, %ymm2
+
+vphaddsw %ymm0, %ymm1, %ymm2
+vphaddsw (%rax), %ymm1, %ymm2
+
+vphaddw %ymm0, %ymm1, %ymm2
+vphaddw (%rax), %ymm1, %ymm2
+
+vphsubd %ymm0, %ymm1, %ymm2
+vphsubd (%rax), %ymm1, %ymm2
+
+vphsubsw %ymm0, %ymm1, %ymm2
+vphsubsw (%rax), %ymm1, %ymm2
+
+vphsubw %ymm0, %ymm1, %ymm2
+vphsubw (%rax), %ymm1, %ymm2
+
+vpmaddubsw %ymm0, %ymm1, %ymm2
+vpmaddubsw (%rax), %ymm1, %ymm2
+
+vpmaddwd %ymm0, %ymm1, %ymm2
+vpmaddwd (%rax), %ymm1, %ymm2
+
+vpmaskmovd (%rax), %xmm0, %xmm2
+vpmaskmovd (%rax), %ymm0, %ymm2
+
+vpmaskmovd %xmm0, %xmm1, (%rax)
+vpmaskmovd %ymm0, %ymm1, (%rax)
+
+vpmaskmovq (%rax), %xmm0, %xmm2
+vpmaskmovq (%rax), %ymm0, %ymm2
+
+vpmaskmovq %xmm0, %xmm1, (%rax)
+vpmaskmovq %ymm0, %ymm1, (%rax)
+
+vpmaxsb %ymm0, %ymm1, %ymm2
+vpmaxsb (%rax), %ymm1, %ymm2
+
+vpmaxsd %ymm0, %ymm1, %ymm2
+vpmaxsd (%rax), %ymm1, %ymm2
+
+vpmaxsw %ymm0, %ymm1, %ymm2
+vpmaxsw (%rax), %ymm1, %ymm2
+
+vpmaxub %ymm0, %ymm1, %ymm2
+vpmaxub (%rax), %ymm1, %ymm2
+
+vpmaxud %ymm0, %ymm1, %ymm2
+vpmaxud (%rax), %ymm1, %ymm2
+
+vpmaxuw %ymm0, %ymm1, %ymm2
+vpmaxuw (%rax), %ymm1, %ymm2
+
+vpminsb %ymm0, %ymm1, %ymm2
+vpminsb (%rax), %ymm1, %ymm2
+
+vpminsd %ymm0, %ymm1, %ymm2
+vpminsd (%rax), %ymm1, %ymm2
+
+vpminsw %ymm0, %ymm1, %ymm2
+vpminsw (%rax), %ymm1, %ymm2
+
+vpminub %ymm0, %ymm1, %ymm2
+vpminub (%rax), %ymm1, %ymm2
+
+vpminud %ymm0, %ymm1, %ymm2
+vpminud (%rax), %ymm1, %ymm2
+
+vpminuw %ymm0, %ymm1, %ymm2
+vpminuw (%rax), %ymm1, %ymm2
+
+vpmovmskb %ymm0, %rcx
+
+vpmovsxbd %xmm0, %ymm2
+vpmovsxbd (%rax), %ymm2
+
+vpmovsxbq %xmm0, %ymm2
+vpmovsxbq (%rax), %ymm2
+
+vpmovsxbw %xmm0, %ymm2
+vpmovsxbw (%rax), %ymm2
+
+vpmovsxdq %xmm0, %ymm2
+vpmovsxdq (%rax), %ymm2
+
+vpmovsxwd %xmm0, %ymm2
+vpmovsxwd (%rax), %ymm2
+
+vpmovsxwq %xmm0, %ymm2
+vpmovsxwq (%rax), %ymm2
+
+vpmovzxbd %xmm0, %ymm2
+vpmovzxbd (%rax), %ymm2
+
+vpmovzxbq %xmm0, %ymm2
+vpmovzxbq (%rax), %ymm2
+
+vpmovzxbw %xmm0, %ymm2
+vpmovzxbw (%rax), %ymm2
+
+vpmovzxdq %xmm0, %ymm2
+vpmovzxdq (%rax), %ymm2
+
+vpmovzxwd %xmm0, %ymm2
+vpmovzxwd (%rax), %ymm2
+
+vpmovzxwq %xmm0, %ymm2
+vpmovzxwq (%rax), %ymm2
+
+vpmuldq %ymm0, %ymm1, %ymm2
+vpmuldq (%rax), %ymm1, %ymm2
+
+vpmulhrsw %ymm0, %ymm1, %ymm2
+vpmulhrsw (%rax), %ymm1, %ymm2
+
+vpmulhuw %ymm0, %ymm1, %ymm2
+vpmulhuw (%rax), %ymm1, %ymm2
+
+vpmulhw %ymm0, %ymm1, %ymm2
+vpmulhw (%rax), %ymm1, %ymm2
+
+vpmulld %ymm0, %ymm1, %ymm2
+vpmulld (%rax), %ymm1, %ymm2
+
+vpmullw %ymm0, %ymm1, %ymm2
+vpmullw (%rax), %ymm1, %ymm2
+
+vpmuludq %ymm0, %ymm1, %ymm2
+vpmuludq (%rax), %ymm1, %ymm2
+
+vpor %ymm0, %ymm1, %ymm2
+vpor (%rax), %ymm1, %ymm2
+
+vpsadbw %ymm0, %ymm1, %ymm2
+vpsadbw (%rax), %ymm1, %ymm2
+
+vpshufb %ymm0, %ymm1, %ymm2
+vpshufb (%rax), %ymm1, %ymm2
+
+vpshufd $1, %ymm0, %ymm2
+vpshufd $1, (%rax), %ymm2
+
+vpshufhw $1, %ymm0, %ymm2
+vpshufhw $1, (%rax), %ymm2
+
+vpshuflw $1, %ymm0, %ymm2
+vpshuflw $1, (%rax), %ymm2
+
+vpsignb %ymm0, %ymm1, %ymm2
+vpsignb (%rax), %ymm1, %ymm2
+
+vpsignd %ymm0, %ymm1, %ymm2
+vpsignd (%rax), %ymm1, %ymm2
+
+vpsignw %ymm0, %ymm1, %ymm2
+vpsignw (%rax), %ymm1, %ymm2
+
+vpslld $1, %ymm0, %ymm2
+vpslld %xmm0, %ymm1, %ymm2
+vpslld (%rax), %ymm1, %ymm2
+
+vpslldq $1, %ymm1, %ymm2
+
+vpsllq $1, %ymm0, %ymm2
+vpsllq %xmm0, %ymm1, %ymm2
+vpsllq (%rax), %ymm1, %ymm2
+
+vpsllvd %xmm0, %xmm1, %xmm2
+vpsllvd (%rax), %xmm1, %xmm2
+
+vpsllvd %ymm0, %ymm1, %ymm2
+vpsllvd (%rax), %ymm1, %ymm2
+
+vpsllvq %xmm0, %xmm1, %xmm2
+vpsllvq (%rax), %xmm1, %xmm2
+
+vpsllvq %ymm0, %ymm1, %ymm2
+vpsllvq (%rax), %ymm1, %ymm2
+
+vpsllw $1, %ymm0, %ymm2
+vpsllw %xmm0, %ymm1, %ymm2
+vpsllw (%rax), %ymm1, %ymm2
+
+vpsrad $1, %ymm0, %ymm2
+vpsrad %xmm0, %ymm1, %ymm2
+vpsrad (%rax), %ymm1, %ymm2
+
+vpsravd %xmm0, %xmm1, %xmm2
+vpsravd (%rax), %xmm1, %xmm2
+
+vpsravd %ymm0, %ymm1, %ymm2
+vpsravd (%rax), %ymm1, %ymm2
+
+vpsraw $1, %ymm0, %ymm2
+vpsraw %xmm0, %ymm1, %ymm2
+vpsraw (%rax), %ymm1, %ymm2
+
+vpsrld $1, %ymm0, %ymm2
+vpsrld %xmm0, %ymm1, %ymm2
+vpsrld (%rax), %ymm1, %ymm2
+
+vpsrldq $1, %ymm1, %ymm2
+
+vpsrlq $1, %ymm0, %ymm2
+vpsrlq %xmm0, %ymm1, %ymm2
+vpsrlq (%rax), %ymm1, %ymm2
+
+vpsrlvd %xmm0, %xmm1, %xmm2
+vpsrlvd (%rax), %xmm1, %xmm2
+
+vpsrlvd %ymm0, %ymm1, %ymm2
+vpsrlvd (%rax), %ymm1, %ymm2
+
+vpsrlvq %xmm0, %xmm1, %xmm2
+vpsrlvq (%rax), %xmm1, %xmm2
+
+vpsrlvq %ymm0, %ymm1, %ymm2
+vpsrlvq (%rax), %ymm1, %ymm2
+
+vpsrlw $1, %ymm0, %ymm2
+vpsrlw %xmm0, %ymm1, %ymm2
+vpsrlw (%rax), %ymm1, %ymm2
+
+vpsubb %ymm0, %ymm1, %ymm2
+vpsubb (%rax), %ymm1, %ymm2
+
+vpsubd %ymm0, %ymm1, %ymm2
+vpsubd (%rax), %ymm1, %ymm2
+
+vpsubq %ymm0, %ymm1, %ymm2
+vpsubq (%rax), %ymm1, %ymm2
+
+vpsubsb %ymm0, %ymm1, %ymm2
+vpsubsb (%rax), %ymm1, %ymm2
+
+vpsubsw %ymm0, %ymm1, %ymm2
+vpsubsw (%rax), %ymm1, %ymm2
+
+vpsubusb %ymm0, %ymm1, %ymm2
+vpsubusb (%rax), %ymm1, %ymm2
+
+vpsubusw %ymm0, %ymm1, %ymm2
+vpsubusw (%rax), %ymm1, %ymm2
+
+vpsubw %ymm0, %ymm1, %ymm2
+vpsubw (%rax), %ymm1, %ymm2
+
+vpunpckhbw %ymm0, %ymm1, %ymm2
+vpunpckhbw (%rax), %ymm1, %ymm2
+
+vpunpckhdq %ymm0, %ymm1, %ymm2
+vpunpckhdq (%rax), %ymm1, %ymm2
+
+vpunpckhqdq %ymm0, %ymm1, %ymm2
+vpunpckhqdq (%rax), %ymm1, %ymm2
+
+vpunpckhwd %ymm0, %ymm1, %ymm2
+vpunpckhwd (%rax), %ymm1, %ymm2
+
+vpunpcklbw %ymm0, %ymm1, %ymm2
+vpunpcklbw (%rax), %ymm1, %ymm2
+
+vpunpckldq %ymm0, %ymm1, %ymm2
+vpunpckldq (%rax), %ymm1, %ymm2
+
+vpunpcklqdq %ymm0, %ymm1, %ymm2
+vpunpcklqdq (%rax), %ymm1, %ymm2
+
+vpunpcklwd %ymm0, %ymm1, %ymm2
+vpunpcklwd (%rax), %ymm1, %ymm2
+
+vpxor %ymm0, %ymm1, %ymm2
+vpxor (%rax), %ymm1, %ymm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 8 0.33 * vbroadcasti128 (%rax), %ymm0
+# CHECK-NEXT: 1 3 1.00 vbroadcastsd %xmm0, %ymm0
+# CHECK-NEXT: 1 3 1.00 vbroadcastss %xmm0, %ymm0
+# CHECK-NEXT: 1 3 1.00 vextracti128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vextracti128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 5 20 1.00 * vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 8 29 1.33 * vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 8 28 1.33 * vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 12 30 2.67 * vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 5 20 1.00 * vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 8 29 1.33 * vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 5 20 1.00 * vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 8 29 1.33 * vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 1 3 1.00 vinserti128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vinserti128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vmovntdqa (%rax), %ymm0
+# CHECK-NEXT: 2 4 1.00 vmpsadbw $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 3 12 1.00 * vmpsadbw $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpabsb %ymm0, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpabsb (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpabsd %ymm0, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpabsd (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpabsw %ymm0, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpabsw (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpackssdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpackssdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpacksswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpacksswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpackusdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpackusdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpackuswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpackuswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpaddb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpaddb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpaddq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpaddq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpaddsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpaddsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpaddusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpaddusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpaddusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpaddusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpalignr $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 1.00 * vpalignr $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpand %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpand (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpandn %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpandn (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpavgb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpavgb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpavgw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpavgw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpblendd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpblendd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpblendd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpblendd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 3 1.00 vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpblendw $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpblendw $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpbroadcastb %xmm0, %xmm0
+# CHECK-NEXT: 2 8 1.00 * vpbroadcastb (%rax), %xmm0
+# CHECK-NEXT: 1 3 1.00 vpbroadcastb %xmm0, %ymm0
+# CHECK-NEXT: 2 9 1.00 * vpbroadcastb (%rax), %ymm0
+# CHECK-NEXT: 1 1 1.00 vpbroadcastd %xmm0, %xmm0
+# CHECK-NEXT: 1 7 0.33 * vpbroadcastd (%rax), %xmm0
+# CHECK-NEXT: 1 3 1.00 vpbroadcastd %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.33 * vpbroadcastd (%rax), %ymm0
+# CHECK-NEXT: 1 1 1.00 vpbroadcastq %xmm0, %xmm0
+# CHECK-NEXT: 1 7 0.33 * vpbroadcastq (%rax), %xmm0
+# CHECK-NEXT: 1 3 1.00 vpbroadcastq %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.33 * vpbroadcastq (%rax), %ymm0
+# CHECK-NEXT: 1 1 1.00 vpbroadcastw %xmm0, %xmm0
+# CHECK-NEXT: 2 8 1.00 * vpbroadcastw (%rax), %xmm0
+# CHECK-NEXT: 1 3 1.00 vpbroadcastw %xmm0, %ymm0
+# CHECK-NEXT: 2 9 1.00 * vpbroadcastw (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.50 vpcmpeqb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpcmpeqb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpcmpeqd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpcmpeqq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpeqw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpcmpeqw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpcmpgtb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpcmpgtd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpcmpgtq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpcmpgtq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpcmpgtw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vperm2i128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vperm2i128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpermd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpermd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpermpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpermpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpermps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpermps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpermq $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpermq $1, (%rax), %ymm2
+# CHECK-NEXT: 8 28 1.33 * vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 12 30 2.67 * vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 5 20 1.00 * vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 8 29 1.33 * vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 5 20 1.00 * vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 8 29 1.33 * vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 5 20 1.00 * vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 8 29 1.33 * vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 3 2 1.00 vphaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vphaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 1.00 vphaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vphaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 1.00 vphaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vphaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 1.00 vphsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vphsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 1.00 vphsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vphsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 2 1.00 vphsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 4 10 1.00 * vphsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vpmaddubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 13 0.50 * vpmaddubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vpmaddwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 13 0.50 * vpmaddwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpmaskmovd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.33 * vpmaskmovd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 3 14 1.00 * * vpmaskmovd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 3 14 1.00 * * vpmaskmovd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 2 8 0.33 * vpmaskmovq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.33 * vpmaskmovq (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 3 14 1.00 * * vpmaskmovq %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 3 14 1.00 * * vpmaskmovq %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 1 0.50 vpmaxsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpmaxsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpmaxsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpmaxsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpmaxsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpmaxsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpmaxub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpmaxub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpmaxud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpmaxud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpmaxuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpmaxuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpminsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpminsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpminsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpminsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpminsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpminsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpminub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpminub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpminud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpminud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpminuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpminuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vpmovmskb %ymm0, %ecx
+# CHECK-NEXT: 1 3 1.00 vpmovsxbd %xmm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpmovsxbd (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmovsxbq %xmm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpmovsxbq (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmovsxbw %xmm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpmovsxbw (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmovsxdq %xmm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpmovsxdq (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmovsxwd %xmm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpmovsxwd (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmovsxwq %xmm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpmovsxwq (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmovzxbd %xmm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpmovzxbd (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmovzxbq %xmm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpmovzxbq (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmovzxbw %xmm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpmovzxbw (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmovzxdq %xmm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpmovzxdq (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmovzxwd %xmm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpmovzxwd (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmovzxwq %xmm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpmovzxwq (%rax), %ymm2
+# CHECK-NEXT: 1 5 0.50 vpmuldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 13 0.50 * vpmuldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vpmulhrsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 13 0.50 * vpmulhrsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vpmulhuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 13 0.50 * vpmulhuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vpmulhw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 13 0.50 * vpmulhw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 10 1.00 vpmulld %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 3 18 1.00 * vpmulld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vpmullw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 13 0.50 * vpmullw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vpmuludq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 13 0.50 * vpmuludq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpor (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpsadbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vpsadbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpshufb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufd $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpshufd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpshufhw $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpshuflw $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsignb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsignb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsignd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsignd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsignw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsignw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpslld $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 1.00 vpslld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpslld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpslldq $1, %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllq $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 1.00 vpsllq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsllq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsllvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsllvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsllvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsllvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllw $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 1.00 vpsllw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsllw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrad $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 1.00 vpsrad %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsrad (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsravd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsravd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsravd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsravd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsraw $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 1.00 vpsraw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsraw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrld $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 1.00 vpsrld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsrld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlq $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 1.00 vpsrlq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsrlq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsrlvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsrlvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpsrlvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsrlvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlw $1, %ymm0, %ymm2
+# CHECK-NEXT: 2 4 1.00 vpsrlw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsrlw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpsubb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpsubb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpsubq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpsubq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsubsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsubsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsubusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsubusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsubusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpsubusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpckhbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpckhdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpckhqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpckhwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpcklbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpckldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpcklqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.50 * vpunpcklwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.33 vpxor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 0.33 * vpxor (%rax), %ymm1, %ymm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 111.00 130.00 65.33 65.33 2.50 135.00 - 2.50 2.50 2.50 - 65.33 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vbroadcasti128 (%rax), %ymm0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vbroadcastsd %xmm0, %ymm0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vbroadcastss %xmm0, %ymm0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vextracti128 $1, %ymm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vextracti128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 1.33 0.83 0.67 0.67 - 0.83 - - - - - 0.67 - vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1.33 1.33 1.33 1.33 - 1.33 - - - - - 1.33 - vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 1.33 1.33 1.33 1.33 - 1.33 - - - - - 1.33 - vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1.33 1.33 2.67 2.67 - 1.33 - - - - - 2.67 - vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 1.33 0.83 0.67 0.67 - 0.83 - - - - - 0.67 - vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1.33 1.33 1.33 1.33 - 1.33 - - - - - 1.33 - vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 1.33 0.83 0.67 0.67 - 0.83 - - - - - 0.67 - vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1.33 1.33 1.33 1.33 - 1.33 - - - - - 1.33 - vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vinserti128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vinserti128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovntdqa (%rax), %ymm0
+# CHECK-NEXT: - 0.50 - - - 1.50 - - - - - - - vmpsadbw $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 1.50 - - - - - 0.33 - vmpsadbw $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpabsb %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpabsb (%rax), %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpabsd %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpabsd (%rax), %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpabsw %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpabsw (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpackssdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpackssdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpacksswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpacksswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpackusdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpackusdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpackuswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpackuswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpaddb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpaddb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpaddq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpaddq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpaddsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpaddsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpaddusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpaddusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpaddusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpaddusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpalignr $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpalignr $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpand %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpand (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpandn %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpandn (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpavgb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpavgb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpavgw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpavgw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpblendd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpblendd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpblendd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpblendd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1.00 1.00 - - - 1.00 - - - - - - - vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - 1.00 - - - - - 0.33 - vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpblendw $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpblendw $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpbroadcastb %xmm0, %xmm0
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpbroadcastb (%rax), %xmm0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpbroadcastb %xmm0, %ymm0
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpbroadcastb (%rax), %ymm0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpbroadcastd %xmm0, %xmm0
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vpbroadcastd (%rax), %xmm0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpbroadcastd %xmm0, %ymm0
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vpbroadcastd (%rax), %ymm0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpbroadcastq %xmm0, %xmm0
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vpbroadcastq (%rax), %xmm0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpbroadcastq %xmm0, %ymm0
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vpbroadcastq (%rax), %ymm0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpbroadcastw %xmm0, %xmm0
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpbroadcastw (%rax), %xmm0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpbroadcastw %xmm0, %ymm0
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpbroadcastw (%rax), %ymm0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpeqb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpeqb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpeqd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpeqd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpeqq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpeqq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpeqw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpeqw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpgtb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpgtb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpgtd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpgtd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpcmpgtq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpcmpgtq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpcmpgtw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpcmpgtw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vperm2i128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vperm2i128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpermd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpermd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpermpd $1, %ymm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpermpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpermps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpermps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpermq $1, %ymm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpermq $1, (%rax), %ymm2
+# CHECK-NEXT: 1.33 1.33 1.33 1.33 - 1.33 - - - - - 1.33 - vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1.33 1.33 2.67 2.67 - 1.33 - - - - - 2.67 - vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 1.33 0.83 0.67 0.67 - 0.83 - - - - - 0.67 - vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1.33 1.33 1.33 1.33 - 1.33 - - - - - 1.33 - vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 1.33 0.83 0.67 0.67 - 0.83 - - - - - 0.67 - vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1.33 1.33 1.33 1.33 - 1.33 - - - - - 1.33 - vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 1.33 0.83 0.67 0.67 - 0.83 - - - - - 0.67 - vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 1.33 1.33 1.33 1.33 - 1.33 - - - - - 1.33 - vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 0.33 1.33 - - - 1.33 - - - - - - - vphaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 1.33 0.33 0.33 - 1.33 - - - - - 0.33 - vphaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 1.50 - - - 1.00 - - - - - - - vphaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 1.50 0.33 0.33 - 1.00 - - - - - 0.33 - vphaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 1.33 - - - 1.33 - - - - - - - vphaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 1.33 0.33 0.33 - 1.33 - - - - - 0.33 - vphaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 1.33 - - - 1.33 - - - - - - - vphsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 1.33 0.33 0.33 - 1.33 - - - - - 0.33 - vphsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 1.50 - - - 1.00 - - - - - - - vphsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 1.50 0.33 0.33 - 1.00 - - - - - 0.33 - vphsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 1.33 - - - 1.33 - - - - - - - vphsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 1.33 0.33 0.33 - 1.33 - - - - - 0.33 - vphsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaddubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaddubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaddwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaddwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpmaskmovd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpmaskmovd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 1.00 - - - 0.50 - - 0.50 0.50 0.50 - - - vpmaskmovd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 1.00 - - - 0.50 - - 0.50 0.50 0.50 - - - vpmaskmovd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpmaskmovq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpmaskmovq (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 1.00 - - - 0.50 - - 0.50 0.50 0.50 - - - vpmaskmovq %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 1.00 - - - 0.50 - - 0.50 0.50 0.50 - - - vpmaskmovq %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaxsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaxsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaxsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaxsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaxsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaxsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaxub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaxub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaxud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaxud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmaxuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmaxuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpminsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpminsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpminsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpminsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpminsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpminsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpminub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpminub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpminud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpminud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpminuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpminuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vpmovmskb %ymm0, %ecx
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpmovsxbd %xmm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpmovsxbd (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpmovsxbq %xmm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpmovsxbq (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpmovsxbw %xmm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpmovsxbw (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpmovsxdq %xmm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpmovsxdq (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpmovsxwd %xmm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpmovsxwd (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpmovsxwq %xmm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpmovsxwq (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpmovzxbd %xmm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpmovzxbd (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpmovzxbq %xmm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpmovzxbq (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpmovzxbw %xmm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpmovzxbw (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpmovzxdq %xmm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpmovzxdq (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpmovzxwd %xmm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpmovzxwd (%rax), %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpmovzxwq %xmm0, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpmovzxwq (%rax), %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmuldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmuldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmulhrsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmulhrsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmulhuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmulhuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmulhw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmulhw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - vpmulld %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - vpmulld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmullw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmullw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpmuludq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpmuludq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpor (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsadbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - vpsadbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpshufb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpshufb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpshufd $1, %ymm0, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpshufd $1, (%rax), %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpshufhw $1, %ymm0, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpshufhw $1, (%rax), %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpshuflw $1, %ymm0, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpshuflw $1, (%rax), %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsignb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsignb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsignd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsignd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsignw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsignw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpslld $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vpslld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpslld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpslldq $1, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsllq $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vpsllq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsllq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsllvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsllvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsllvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsllvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsllvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsllvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsllvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsllvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsllw $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vpsllw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsllw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsrad $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vpsrad %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsrad (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsravd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsravd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsravd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsravd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsraw $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vpsraw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsraw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsrld $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vpsrld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsrld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpsrldq $1, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsrlq $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vpsrlq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsrlq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsrlvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsrlvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsrlvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsrlvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsrlvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsrlvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsrlvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsrlvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsrlw $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vpsrlw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsrlw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpsubb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpsubb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpsubq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpsubq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsubsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsubsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsubusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsubusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpsubusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vpsubusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpckhbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpckhbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpckhdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpckhdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpckhqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpckhqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpckhwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpckhwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpcklbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpcklbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpckldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpckldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpcklqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpcklqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vpunpcklwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vpunpcklwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vpxor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - vpxor (%rax), %ymm1, %ymm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s
new file mode 100644
index 0000000000000..4ed882a37a68e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s
@@ -0,0 +1,125 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+andn %eax, %ebx, %ecx
+andn (%rax), %ebx, %ecx
+
+andn %rax, %rbx, %rcx
+andn (%rax), %rbx, %rcx
+
+bextr %eax, %ebx, %ecx
+bextr %eax, (%rbx), %ecx
+
+bextr %rax, %rbx, %rcx
+bextr %rax, (%rbx), %rcx
+
+blsi %eax, %ecx
+blsi (%rax), %ecx
+
+blsi %rax, %rcx
+blsi (%rax), %rcx
+
+blsmsk %eax, %ecx
+blsmsk (%rax), %ecx
+
+blsmsk %rax, %rcx
+blsmsk (%rax), %rcx
+
+blsr %eax, %ecx
+blsr (%rax), %ecx
+
+blsr %rax, %rcx
+blsr (%rax), %rcx
+
+tzcnt %ax, %cx
+tzcnt (%rax), %cx
+
+tzcnt %eax, %ecx
+tzcnt (%rax), %ecx
+
+tzcnt %rax, %rcx
+tzcnt (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 2 0.33 andnl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 7 0.33 * andnl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 2 0.33 andnq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 7 0.33 * andnq (%rax), %rbx, %rcx
+# CHECK-NEXT: 2 6 1.00 bextrl %eax, %ebx, %ecx
+# CHECK-NEXT: 3 11 1.00 * bextrl %eax, (%rbx), %ecx
+# CHECK-NEXT: 2 6 1.00 bextrq %rax, %rbx, %rcx
+# CHECK-NEXT: 3 11 1.00 * bextrq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 2 0.33 blsil %eax, %ecx
+# CHECK-NEXT: 2 7 0.33 * blsil (%rax), %ecx
+# CHECK-NEXT: 1 2 0.33 blsiq %rax, %rcx
+# CHECK-NEXT: 2 7 0.33 * blsiq (%rax), %rcx
+# CHECK-NEXT: 1 2 0.33 blsmskl %eax, %ecx
+# CHECK-NEXT: 2 7 0.33 * blsmskl (%rax), %ecx
+# CHECK-NEXT: 1 2 0.33 blsmskq %rax, %rcx
+# CHECK-NEXT: 2 7 0.33 * blsmskq (%rax), %rcx
+# CHECK-NEXT: 1 2 0.33 blsrl %eax, %ecx
+# CHECK-NEXT: 2 7 0.33 * blsrl (%rax), %ecx
+# CHECK-NEXT: 1 2 0.33 blsrq %rax, %rcx
+# CHECK-NEXT: 2 7 0.33 * blsrq (%rax), %rcx
+# CHECK-NEXT: 1 3 1.00 tzcntw %ax, %cx
+# CHECK-NEXT: 2 8 1.00 * tzcntw (%rax), %cx
+# CHECK-NEXT: 1 3 1.00 tzcntl %eax, %ecx
+# CHECK-NEXT: 2 8 1.00 * tzcntl (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 tzcntq %rax, %rcx
+# CHECK-NEXT: 2 8 1.00 * tzcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 2.00 15.33 4.33 4.33 - 5.33 2.00 - - - 5.33 4.33 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - andnl %eax, %ebx, %ecx
+# CHECK-NEXT: - 0.33 0.33 0.33 - 0.33 - - - - 0.33 0.33 - andnl (%rax), %ebx, %ecx
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - andnq %rax, %rbx, %rcx
+# CHECK-NEXT: - 0.33 0.33 0.33 - 0.33 - - - - 0.33 0.33 - andnq (%rax), %rbx, %rcx
+# CHECK-NEXT: 0.50 1.00 - - - - 0.50 - - - - - - bextrl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.50 1.00 0.33 0.33 - - 0.50 - - - - 0.33 - bextrl %eax, (%rbx), %ecx
+# CHECK-NEXT: 0.50 1.00 - - - - 0.50 - - - - - - bextrq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.50 1.00 0.33 0.33 - - 0.50 - - - - 0.33 - bextrq %rax, (%rbx), %rcx
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - blsil %eax, %ecx
+# CHECK-NEXT: - 0.33 0.33 0.33 - 0.33 - - - - 0.33 0.33 - blsil (%rax), %ecx
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - blsiq %rax, %rcx
+# CHECK-NEXT: - 0.33 0.33 0.33 - 0.33 - - - - 0.33 0.33 - blsiq (%rax), %rcx
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - blsmskl %eax, %ecx
+# CHECK-NEXT: - 0.33 0.33 0.33 - 0.33 - - - - 0.33 0.33 - blsmskl (%rax), %ecx
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - blsmskq %rax, %rcx
+# CHECK-NEXT: - 0.33 0.33 0.33 - 0.33 - - - - 0.33 0.33 - blsmskq (%rax), %rcx
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - blsrl %eax, %ecx
+# CHECK-NEXT: - 0.33 0.33 0.33 - 0.33 - - - - 0.33 0.33 - blsrl (%rax), %ecx
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - blsrq %rax, %rcx
+# CHECK-NEXT: - 0.33 0.33 0.33 - 0.33 - - - - 0.33 0.33 - blsrq (%rax), %rcx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - tzcntw %ax, %cx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - tzcntw (%rax), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - tzcntl %eax, %ecx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - tzcntl (%rax), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - tzcntq %rax, %rcx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - tzcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s
new file mode 100644
index 0000000000000..559ca83906cb7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s
@@ -0,0 +1,146 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+bzhi %eax, %ebx, %ecx
+bzhi %eax, (%rbx), %ecx
+
+bzhi %rax, %rbx, %rcx
+bzhi %rax, (%rbx), %rcx
+
+mulx %eax, %ebx, %ecx
+mulx (%rax), %ebx, %ecx
+
+mulx %rax, %rbx, %rcx
+mulx (%rax), %rbx, %rcx
+
+pdep %eax, %ebx, %ecx
+pdep (%rax), %ebx, %ecx
+
+pdep %rax, %rbx, %rcx
+pdep (%rax), %rbx, %rcx
+
+pext %eax, %ebx, %ecx
+pext (%rax), %ebx, %ecx
+
+pext %rax, %rbx, %rcx
+pext (%rax), %rbx, %rcx
+
+rorx $1, %eax, %ecx
+rorx $1, (%rax), %ecx
+
+rorx $1, %rax, %rcx
+rorx $1, (%rax), %rcx
+
+sarx %eax, %ebx, %ecx
+sarx %eax, (%rbx), %ecx
+
+sarx %rax, %rbx, %rcx
+sarx %rax, (%rbx), %rcx
+
+shlx %eax, %ebx, %ecx
+shlx %eax, (%rbx), %ecx
+
+shlx %rax, %rbx, %rcx
+shlx %rax, (%rbx), %rcx
+
+shrx %eax, %ebx, %ecx
+shrx %eax, (%rbx), %ecx
+
+shrx %rax, %rbx, %rcx
+shrx %rax, (%rbx), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 bzhil %eax, %ebx, %ecx
+# CHECK-NEXT: 2 8 1.00 * bzhil %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 3 1.00 bzhiq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 8 1.00 * bzhiq %rax, (%rbx), %rcx
+# CHECK-NEXT: 3 4 1.00 mulxl %eax, %ebx, %ecx
+# CHECK-NEXT: 4 9 1.00 * mulxl (%rax), %ebx, %ecx
+# CHECK-NEXT: 2 4 1.00 mulxq %rax, %rbx, %rcx
+# CHECK-NEXT: 3 9 1.00 * mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 3 1.00 pdepl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 8 1.00 * pdepl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 3 1.00 pdepq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 8 1.00 * pdepq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 3 1.00 pextl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 8 1.00 * pextl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 3 1.00 pextq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 8 1.00 * pextq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 1 0.50 rorxl $1, %eax, %ecx
+# CHECK-NEXT: 2 6 0.50 * rorxl $1, (%rax), %ecx
+# CHECK-NEXT: 1 1 0.50 rorxq $1, %rax, %rcx
+# CHECK-NEXT: 2 6 0.50 * rorxq $1, (%rax), %rcx
+# CHECK-NEXT: 1 3 0.50 sarxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 8 0.50 * sarxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 3 0.50 sarxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 8 0.50 * sarxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 3 0.50 shlxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 8 0.50 * shlxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 3 0.50 shlxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 8 0.50 * shlxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 3 0.50 shrxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 8 0.50 * shrxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 3 0.50 shrxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 8 0.50 * shrxq %rax, (%rbx), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 9.40 16.40 5.33 5.33 - 2.40 9.40 - - - 0.40 5.33 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - bzhil %eax, %ebx, %ecx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - bzhil %eax, (%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - bzhiq %rax, %rbx, %rcx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - bzhiq %rax, (%rbx), %rcx
+# CHECK-NEXT: 0.70 1.20 - - - 0.20 0.70 - - - 0.20 - - mulxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.70 1.20 0.33 0.33 - 0.20 0.70 - - - 0.20 0.33 - mulxl (%rax), %ebx, %ecx
+# CHECK-NEXT: - 1.00 - - - 1.00 - - - - - - - mulxq %rax, %rbx, %rcx
+# CHECK-NEXT: - 1.00 0.33 0.33 - 1.00 - - - - - 0.33 - mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - pdepl %eax, %ebx, %ecx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - pdepl (%rax), %ebx, %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - pdepq %rax, %rbx, %rcx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - pdepq (%rax), %rbx, %rcx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - pextl %eax, %ebx, %ecx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - pextl (%rax), %ebx, %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - pextq %rax, %rbx, %rcx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - pextq (%rax), %rbx, %rcx
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - rorxl $1, %eax, %ecx
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - rorxl $1, (%rax), %ecx
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - rorxq $1, %rax, %rcx
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - rorxq $1, (%rax), %rcx
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sarxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - sarxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sarxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - sarxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shlxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - shlxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shlxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - shlxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shrxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - shrxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shrxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - shrxq %rax, (%rbx), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s
new file mode 100644
index 0000000000000..e61cc06951ae5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s
@@ -0,0 +1,38 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+clflushopt (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 3 2 0.50 * * U clflushopt (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 0.20 0.20 - - 0.50 0.20 0.20 0.50 0.50 0.50 0.20 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.20 0.20 - - 0.50 0.20 0.20 0.50 0.50 0.50 0.20 - - clflushopt (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s
new file mode 100644
index 0000000000000..d35eadcc3f9d0
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s
@@ -0,0 +1,38 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+clwb (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 3 5 0.50 * * U clwb (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 0.20 0.20 - - 0.50 0.20 0.20 0.50 0.50 0.50 0.20 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.20 0.20 - - 0.50 0.20 0.20 0.50 0.50 0.50 0.20 - - clwb (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s
new file mode 100644
index 0000000000000..87a0e070096c2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s
@@ -0,0 +1,328 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+cmovow %si, %di
+cmovnow %si, %di
+cmovbw %si, %di
+cmovaew %si, %di
+cmovew %si, %di
+cmovnew %si, %di
+cmovbew %si, %di
+cmovaw %si, %di
+cmovsw %si, %di
+cmovnsw %si, %di
+cmovpw %si, %di
+cmovnpw %si, %di
+cmovlw %si, %di
+cmovgew %si, %di
+cmovlew %si, %di
+cmovgw %si, %di
+
+cmovow (%rax), %di
+cmovnow (%rax), %di
+cmovbw (%rax), %di
+cmovaew (%rax), %di
+cmovew (%rax), %di
+cmovnew (%rax), %di
+cmovbew (%rax), %di
+cmovaw (%rax), %di
+cmovsw (%rax), %di
+cmovnsw (%rax), %di
+cmovpw (%rax), %di
+cmovnpw (%rax), %di
+cmovlw (%rax), %di
+cmovgew (%rax), %di
+cmovlew (%rax), %di
+cmovgw (%rax), %di
+
+cmovol %esi, %edi
+cmovnol %esi, %edi
+cmovbl %esi, %edi
+cmovael %esi, %edi
+cmovel %esi, %edi
+cmovnel %esi, %edi
+cmovbel %esi, %edi
+cmoval %esi, %edi
+cmovsl %esi, %edi
+cmovnsl %esi, %edi
+cmovpl %esi, %edi
+cmovnpl %esi, %edi
+cmovll %esi, %edi
+cmovgel %esi, %edi
+cmovlel %esi, %edi
+cmovgl %esi, %edi
+
+cmovol (%rax), %edi
+cmovnol (%rax), %edi
+cmovbl (%rax), %edi
+cmovael (%rax), %edi
+cmovel (%rax), %edi
+cmovnel (%rax), %edi
+cmovbel (%rax), %edi
+cmoval (%rax), %edi
+cmovsl (%rax), %edi
+cmovnsl (%rax), %edi
+cmovpl (%rax), %edi
+cmovnpl (%rax), %edi
+cmovll (%rax), %edi
+cmovgel (%rax), %edi
+cmovlel (%rax), %edi
+cmovgl (%rax), %edi
+
+cmovoq %rsi, %rdi
+cmovnoq %rsi, %rdi
+cmovbq %rsi, %rdi
+cmovaeq %rsi, %rdi
+cmoveq %rsi, %rdi
+cmovneq %rsi, %rdi
+cmovbeq %rsi, %rdi
+cmovaq %rsi, %rdi
+cmovsq %rsi, %rdi
+cmovnsq %rsi, %rdi
+cmovpq %rsi, %rdi
+cmovnpq %rsi, %rdi
+cmovlq %rsi, %rdi
+cmovgeq %rsi, %rdi
+cmovleq %rsi, %rdi
+cmovgq %rsi, %rdi
+
+cmovoq (%rax), %rdi
+cmovnoq (%rax), %rdi
+cmovbq (%rax), %rdi
+cmovaeq (%rax), %rdi
+cmoveq (%rax), %rdi
+cmovneq (%rax), %rdi
+cmovbeq (%rax), %rdi
+cmovaq (%rax), %rdi
+cmovsq (%rax), %rdi
+cmovnsq (%rax), %rdi
+cmovpq (%rax), %rdi
+cmovnpq (%rax), %rdi
+cmovlq (%rax), %rdi
+cmovgeq (%rax), %rdi
+cmovleq (%rax), %rdi
+cmovgq (%rax), %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 cmovow %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovnow %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovbw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovaew %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovew %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovnew %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovbew %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovaw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovsw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovnsw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovpw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovnpw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovlw %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovgew %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovlew %si, %di
+# CHECK-NEXT: 1 1 0.50 cmovgw %si, %di
+# CHECK-NEXT: 2 7 0.50 * cmovow (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovnow (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovbw (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovaew (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovew (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovnew (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovbew (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovaw (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovsw (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovnsw (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovpw (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovnpw (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovlw (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovgew (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovlew (%rax), %di
+# CHECK-NEXT: 2 7 0.50 * cmovgw (%rax), %di
+# CHECK-NEXT: 1 1 0.50 cmovol %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovnol %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovbl %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovael %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovel %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovnel %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovbel %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmoval %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovsl %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovnsl %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovpl %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovnpl %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovll %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovgel %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovlel %esi, %edi
+# CHECK-NEXT: 1 1 0.50 cmovgl %esi, %edi
+# CHECK-NEXT: 2 7 0.50 * cmovol (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovnol (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovbl (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovael (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovel (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovnel (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovbel (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmoval (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovsl (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovnsl (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovpl (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovnpl (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovll (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovgel (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovlel (%rax), %edi
+# CHECK-NEXT: 2 7 0.50 * cmovgl (%rax), %edi
+# CHECK-NEXT: 1 1 0.50 cmovoq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovnoq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovbq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovaeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmoveq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovneq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovbeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovaq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovsq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovnsq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovpq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovnpq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovlq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovgeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovleq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.50 cmovgq %rsi, %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovoq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovnoq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovbq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovaeq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmoveq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovneq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovbeq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovaq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovsq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovnsq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovpq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovnpq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovlq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovgeq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovleq (%rax), %rdi
+# CHECK-NEXT: 2 7 0.50 * cmovgq (%rax), %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 48.00 - 16.00 16.00 - - 48.00 - - - - 16.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovow %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnow %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovbw %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovaew %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovew %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnew %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovbew %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovaw %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovsw %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnsw %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovpw %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnpw %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovlw %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovgew %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovlew %si, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovgw %si, %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovow (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnow (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovbw (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovaew (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovew (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnew (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovbew (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovaw (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovsw (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnsw (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovpw (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnpw (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovlw (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovgew (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovlew (%rax), %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovgw (%rax), %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovol %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnol %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovbl %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovael %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovel %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnel %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovbel %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmoval %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovsl %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnsl %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovpl %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnpl %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovll %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovgel %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovlel %esi, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovgl %esi, %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovol (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnol (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovbl (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovael (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovel (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnel (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovbel (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmoval (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovsl (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnsl (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovpl (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnpl (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovll (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovgel (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovlel (%rax), %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovgl (%rax), %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovoq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnoq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovbq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovaeq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmoveq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovneq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovbeq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovaq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovsq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnsq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovpq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnpq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovlq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovgeq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovleq %rsi, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovgq %rsi, %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovoq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnoq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovbq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovaeq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmoveq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovneq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovbeq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovaq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovsq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnsq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovpq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnpq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovlq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovgeq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovleq (%rax), %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovgq (%rax), %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmpxchg.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmpxchg.s
new file mode 100644
index 0000000000000..93ef7797dfe36
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmpxchg.s
@@ -0,0 +1,47 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+cmpxchg8b (%rax)
+cmpxchg16b (%rax)
+lock cmpxchg8b (%rax)
+lock cmpxchg16b (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 16 25 3.50 * * cmpxchg8b (%rax)
+# CHECK-NEXT: 22 32 4.00 * * cmpxchg16b (%rax)
+# CHECK-NEXT: 16 25 3.50 * * lock cmpxchg8b (%rax)
+# CHECK-NEXT: 22 32 4.00 * * lock cmpxchg16b (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 21.40 10.40 1.33 1.33 2.00 10.40 17.40 2.00 2.00 2.00 4.40 1.33 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 4.30 2.80 0.33 0.33 0.50 0.80 4.30 0.50 0.50 0.50 0.80 0.33 - cmpxchg8b (%rax)
+# CHECK-NEXT: 6.40 2.40 0.33 0.33 0.50 4.40 4.40 0.50 0.50 0.50 1.40 0.33 - cmpxchg16b (%rax)
+# CHECK-NEXT: 4.30 2.80 0.33 0.33 0.50 0.80 4.30 0.50 0.50 0.50 0.80 0.33 - lock cmpxchg8b (%rax)
+# CHECK-NEXT: 6.40 2.40 0.33 0.33 0.50 4.40 4.40 0.50 0.50 0.50 1.40 0.33 - lock cmpxchg16b (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s
new file mode 100644
index 0000000000000..7e4eeebfdaca1
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+vcvtph2ps %xmm0, %xmm2
+vcvtph2ps (%rax), %xmm2
+
+vcvtph2ps %xmm0, %ymm2
+vcvtph2ps (%rax), %ymm2
+
+vcvtps2ph $0, %xmm0, %xmm2
+vcvtps2ph $0, %xmm0, (%rax)
+
+vcvtps2ph $0, %ymm0, %xmm2
+vcvtps2ph $0, %ymm0, (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 2 6 1.00 vcvtph2ps %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * vcvtph2ps (%rax), %xmm2
+# CHECK-NEXT: 2 8 1.00 vcvtph2ps %xmm0, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vcvtph2ps (%rax), %ymm2
+# CHECK-NEXT: 2 6 1.00 vcvtps2ph $0, %xmm0, %xmm2
+# CHECK-NEXT: 3 12 0.50 * vcvtps2ph $0, %xmm0, (%rax)
+# CHECK-NEXT: 2 8 1.00 vcvtps2ph $0, %ymm0, %xmm2
+# CHECK-NEXT: 3 12 0.50 * vcvtps2ph $0, %ymm0, (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 4.00 4.00 0.67 0.67 1.00 4.00 - 1.00 1.00 1.00 - 0.67 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtph2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtph2ps (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtph2ps %xmm0, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vcvtph2ps (%rax), %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtps2ph $0, %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - 0.50 - - 0.50 0.50 0.50 - - - vcvtps2ph $0, %xmm0, (%rax)
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - vcvtps2ph $0, %ymm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - 0.50 - - 0.50 0.50 0.50 - - - vcvtps2ph $0, %ymm0, (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s
new file mode 100644
index 0000000000000..63fc8dbaa44b2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s
@@ -0,0 +1,706 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+vfmadd132pd %xmm0, %xmm1, %xmm2
+vfmadd132pd (%rax), %xmm1, %xmm2
+
+vfmadd132pd %ymm0, %ymm1, %ymm2
+vfmadd132pd (%rax), %ymm1, %ymm2
+
+vfmadd213pd %xmm0, %xmm1, %xmm2
+vfmadd213pd (%rax), %xmm1, %xmm2
+
+vfmadd213pd %ymm0, %ymm1, %ymm2
+vfmadd213pd (%rax), %ymm1, %ymm2
+
+vfmadd231pd %xmm0, %xmm1, %xmm2
+vfmadd231pd (%rax), %xmm1, %xmm2
+
+vfmadd231pd %ymm0, %ymm1, %ymm2
+vfmadd231pd (%rax), %ymm1, %ymm2
+
+vfmadd132ps %xmm0, %xmm1, %xmm2
+vfmadd132ps (%rax), %xmm1, %xmm2
+
+vfmadd132ps %ymm0, %ymm1, %ymm2
+vfmadd132ps (%rax), %ymm1, %ymm2
+
+vfmadd213ps %xmm0, %xmm1, %xmm2
+vfmadd213ps (%rax), %xmm1, %xmm2
+
+vfmadd213ps %ymm0, %ymm1, %ymm2
+vfmadd213ps (%rax), %ymm1, %ymm2
+
+vfmadd231ps %xmm0, %xmm1, %xmm2
+vfmadd231ps (%rax), %xmm1, %xmm2
+
+vfmadd231ps %ymm0, %ymm1, %ymm2
+vfmadd231ps (%rax), %ymm1, %ymm2
+
+vfmadd132sd %xmm0, %xmm1, %xmm2
+vfmadd132sd (%rax), %xmm1, %xmm2
+
+vfmadd213sd %xmm0, %xmm1, %xmm2
+vfmadd213sd (%rax), %xmm1, %xmm2
+
+vfmadd231sd %xmm0, %xmm1, %xmm2
+vfmadd231sd (%rax), %xmm1, %xmm2
+
+vfmadd132ss %xmm0, %xmm1, %xmm2
+vfmadd132ss (%rax), %xmm1, %xmm2
+
+vfmadd213ss %xmm0, %xmm1, %xmm2
+vfmadd213ss (%rax), %xmm1, %xmm2
+
+vfmadd231ss %xmm0, %xmm1, %xmm2
+vfmadd231ss (%rax), %xmm1, %xmm2
+
+vfmaddsub132pd %xmm0, %xmm1, %xmm2
+vfmaddsub132pd (%rax), %xmm1, %xmm2
+
+vfmaddsub132pd %ymm0, %ymm1, %ymm2
+vfmaddsub132pd (%rax), %ymm1, %ymm2
+
+vfmaddsub213pd %xmm0, %xmm1, %xmm2
+vfmaddsub213pd (%rax), %xmm1, %xmm2
+
+vfmaddsub213pd %ymm0, %ymm1, %ymm2
+vfmaddsub213pd (%rax), %ymm1, %ymm2
+
+vfmaddsub231pd %xmm0, %xmm1, %xmm2
+vfmaddsub231pd (%rax), %xmm1, %xmm2
+
+vfmaddsub231pd %ymm0, %ymm1, %ymm2
+vfmaddsub231pd (%rax), %ymm1, %ymm2
+
+vfmaddsub132ps %xmm0, %xmm1, %xmm2
+vfmaddsub132ps (%rax), %xmm1, %xmm2
+
+vfmaddsub132ps %ymm0, %ymm1, %ymm2
+vfmaddsub132ps (%rax), %ymm1, %ymm2
+
+vfmaddsub213ps %xmm0, %xmm1, %xmm2
+vfmaddsub213ps (%rax), %xmm1, %xmm2
+
+vfmaddsub213ps %ymm0, %ymm1, %ymm2
+vfmaddsub213ps (%rax), %ymm1, %ymm2
+
+vfmaddsub231ps %xmm0, %xmm1, %xmm2
+vfmaddsub231ps (%rax), %xmm1, %xmm2
+
+vfmaddsub231ps %ymm0, %ymm1, %ymm2
+vfmaddsub231ps (%rax), %ymm1, %ymm2
+
+vfmsub132pd %xmm0, %xmm1, %xmm2
+vfmsub132pd (%rax), %xmm1, %xmm2
+
+vfmsub132pd %ymm0, %ymm1, %ymm2
+vfmsub132pd (%rax), %ymm1, %ymm2
+
+vfmsub213pd %xmm0, %xmm1, %xmm2
+vfmsub213pd (%rax), %xmm1, %xmm2
+
+vfmsub213pd %ymm0, %ymm1, %ymm2
+vfmsub213pd (%rax), %ymm1, %ymm2
+
+vfmsub231pd %xmm0, %xmm1, %xmm2
+vfmsub231pd (%rax), %xmm1, %xmm2
+
+vfmsub231pd %ymm0, %ymm1, %ymm2
+vfmsub231pd (%rax), %ymm1, %ymm2
+
+vfmsub132ps %xmm0, %xmm1, %xmm2
+vfmsub132ps (%rax), %xmm1, %xmm2
+
+vfmsub132ps %ymm0, %ymm1, %ymm2
+vfmsub132ps (%rax), %ymm1, %ymm2
+
+vfmsub213ps %xmm0, %xmm1, %xmm2
+vfmsub213ps (%rax), %xmm1, %xmm2
+
+vfmsub213ps %ymm0, %ymm1, %ymm2
+vfmsub213ps (%rax), %ymm1, %ymm2
+
+vfmsub231ps %xmm0, %xmm1, %xmm2
+vfmsub231ps (%rax), %xmm1, %xmm2
+
+vfmsub231ps %ymm0, %ymm1, %ymm2
+vfmsub231ps (%rax), %ymm1, %ymm2
+
+vfmsub132sd %xmm0, %xmm1, %xmm2
+vfmsub132sd (%rax), %xmm1, %xmm2
+
+vfmsub213sd %xmm0, %xmm1, %xmm2
+vfmsub213sd (%rax), %xmm1, %xmm2
+
+vfmsub231sd %xmm0, %xmm1, %xmm2
+vfmsub231sd (%rax), %xmm1, %xmm2
+
+vfmsub132ss %xmm0, %xmm1, %xmm2
+vfmsub132ss (%rax), %xmm1, %xmm2
+
+vfmsub213ss %xmm0, %xmm1, %xmm2
+vfmsub213ss (%rax), %xmm1, %xmm2
+
+vfmsub231ss %xmm0, %xmm1, %xmm2
+vfmsub231ss (%rax), %xmm1, %xmm2
+
+vfmsubadd132pd %xmm0, %xmm1, %xmm2
+vfmsubadd132pd (%rax), %xmm1, %xmm2
+
+vfmsubadd132pd %ymm0, %ymm1, %ymm2
+vfmsubadd132pd (%rax), %ymm1, %ymm2
+
+vfmsubadd213pd %xmm0, %xmm1, %xmm2
+vfmsubadd213pd (%rax), %xmm1, %xmm2
+
+vfmsubadd213pd %ymm0, %ymm1, %ymm2
+vfmsubadd213pd (%rax), %ymm1, %ymm2
+
+vfmsubadd231pd %xmm0, %xmm1, %xmm2
+vfmsubadd231pd (%rax), %xmm1, %xmm2
+
+vfmsubadd231pd %ymm0, %ymm1, %ymm2
+vfmsubadd231pd (%rax), %ymm1, %ymm2
+
+vfmsubadd132ps %xmm0, %xmm1, %xmm2
+vfmsubadd132ps (%rax), %xmm1, %xmm2
+
+vfmsubadd132ps %ymm0, %ymm1, %ymm2
+vfmsubadd132ps (%rax), %ymm1, %ymm2
+
+vfmsubadd213ps %xmm0, %xmm1, %xmm2
+vfmsubadd213ps (%rax), %xmm1, %xmm2
+
+vfmsubadd213ps %ymm0, %ymm1, %ymm2
+vfmsubadd213ps (%rax), %ymm1, %ymm2
+
+vfmsubadd231ps %xmm0, %xmm1, %xmm2
+vfmsubadd231ps (%rax), %xmm1, %xmm2
+
+vfmsubadd231ps %ymm0, %ymm1, %ymm2
+vfmsubadd231ps (%rax), %ymm1, %ymm2
+
+vfnmadd132pd %xmm0, %xmm1, %xmm2
+vfnmadd132pd (%rax), %xmm1, %xmm2
+
+vfnmadd132pd %ymm0, %ymm1, %ymm2
+vfnmadd132pd (%rax), %ymm1, %ymm2
+
+vfnmadd213pd %xmm0, %xmm1, %xmm2
+vfnmadd213pd (%rax), %xmm1, %xmm2
+
+vfnmadd213pd %ymm0, %ymm1, %ymm2
+vfnmadd213pd (%rax), %ymm1, %ymm2
+
+vfnmadd231pd %xmm0, %xmm1, %xmm2
+vfnmadd231pd (%rax), %xmm1, %xmm2
+
+vfnmadd231pd %ymm0, %ymm1, %ymm2
+vfnmadd231pd (%rax), %ymm1, %ymm2
+
+vfnmadd132ps %xmm0, %xmm1, %xmm2
+vfnmadd132ps (%rax), %xmm1, %xmm2
+
+vfnmadd132ps %ymm0, %ymm1, %ymm2
+vfnmadd132ps (%rax), %ymm1, %ymm2
+
+vfnmadd213ps %xmm0, %xmm1, %xmm2
+vfnmadd213ps (%rax), %xmm1, %xmm2
+
+vfnmadd213ps %ymm0, %ymm1, %ymm2
+vfnmadd213ps (%rax), %ymm1, %ymm2
+
+vfnmadd231ps %xmm0, %xmm1, %xmm2
+vfnmadd231ps (%rax), %xmm1, %xmm2
+
+vfnmadd231ps %ymm0, %ymm1, %ymm2
+vfnmadd231ps (%rax), %ymm1, %ymm2
+
+vfnmadd132sd %xmm0, %xmm1, %xmm2
+vfnmadd132sd (%rax), %xmm1, %xmm2
+
+vfnmadd213sd %xmm0, %xmm1, %xmm2
+vfnmadd213sd (%rax), %xmm1, %xmm2
+
+vfnmadd231sd %xmm0, %xmm1, %xmm2
+vfnmadd231sd (%rax), %xmm1, %xmm2
+
+vfnmadd132ss %xmm0, %xmm1, %xmm2
+vfnmadd132ss (%rax), %xmm1, %xmm2
+
+vfnmadd213ss %xmm0, %xmm1, %xmm2
+vfnmadd213ss (%rax), %xmm1, %xmm2
+
+vfnmadd231ss %xmm0, %xmm1, %xmm2
+vfnmadd231ss (%rax), %xmm1, %xmm2
+
+vfnmsub132pd %xmm0, %xmm1, %xmm2
+vfnmsub132pd (%rax), %xmm1, %xmm2
+
+vfnmsub132pd %ymm0, %ymm1, %ymm2
+vfnmsub132pd (%rax), %ymm1, %ymm2
+
+vfnmsub213pd %xmm0, %xmm1, %xmm2
+vfnmsub213pd (%rax), %xmm1, %xmm2
+
+vfnmsub213pd %ymm0, %ymm1, %ymm2
+vfnmsub213pd (%rax), %ymm1, %ymm2
+
+vfnmsub231pd %xmm0, %xmm1, %xmm2
+vfnmsub231pd (%rax), %xmm1, %xmm2
+
+vfnmsub231pd %ymm0, %ymm1, %ymm2
+vfnmsub231pd (%rax), %ymm1, %ymm2
+
+vfnmsub132ps %xmm0, %xmm1, %xmm2
+vfnmsub132ps (%rax), %xmm1, %xmm2
+
+vfnmsub132ps %ymm0, %ymm1, %ymm2
+vfnmsub132ps (%rax), %ymm1, %ymm2
+
+vfnmsub213ps %xmm0, %xmm1, %xmm2
+vfnmsub213ps (%rax), %xmm1, %xmm2
+
+vfnmsub213ps %ymm0, %ymm1, %ymm2
+vfnmsub213ps (%rax), %ymm1, %ymm2
+
+vfnmsub231ps %xmm0, %xmm1, %xmm2
+vfnmsub231ps (%rax), %xmm1, %xmm2
+
+vfnmsub231ps %ymm0, %ymm1, %ymm2
+vfnmsub231ps (%rax), %ymm1, %ymm2
+
+vfnmsub132sd %xmm0, %xmm1, %xmm2
+vfnmsub132sd (%rax), %xmm1, %xmm2
+
+vfnmsub213sd %xmm0, %xmm1, %xmm2
+vfnmsub213sd (%rax), %xmm1, %xmm2
+
+vfnmsub231sd %xmm0, %xmm1, %xmm2
+vfnmsub231sd (%rax), %xmm1, %xmm2
+
+vfnmsub132ss %xmm0, %xmm1, %xmm2
+vfnmsub132ss (%rax), %xmm1, %xmm2
+
+vfnmsub213ss %xmm0, %xmm1, %xmm2
+vfnmsub213ss (%rax), %xmm1, %xmm2
+
+vfnmsub231ss %xmm0, %xmm1, %xmm2
+vfnmsub231ss (%rax), %xmm1, %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.50 vfmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmaddsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmaddsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmaddsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmaddsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmaddsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmaddsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmaddsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmaddsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmaddsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmaddsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmaddsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmaddsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsubadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmsubadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsubadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmsubadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsubadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmsubadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsubadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmsubadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsubadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmsubadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfmsubadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfmsubadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfnmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfnmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfnmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfnmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfnmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfnmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfnmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfnmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfnmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfnmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfnmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vfnmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub231ss (%rax), %xmm1, %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 96.00 96.00 32.00 32.00 - - - - - - - 32.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmaddsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmaddsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmaddsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmaddsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmaddsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmaddsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmaddsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmaddsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmaddsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmaddsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmaddsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmaddsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmaddsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmaddsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmaddsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmaddsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmaddsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmaddsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmaddsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmaddsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmaddsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmaddsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmaddsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmaddsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsub231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsubadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsubadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsubadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsubadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsubadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsubadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsubadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsubadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsubadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsubadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsubadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsubadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsubadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsubadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsubadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsubadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsubadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsubadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsubadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsubadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsubadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsubadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfmsubadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfmsubadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vfnmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vfnmsub231ss (%rax), %xmm1, %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fsgsbase.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fsgsbase.s
new file mode 100644
index 0000000000000..e87f8a772af10
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fsgsbase.s
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+rdfsbase %eax
+rdfsbase %rax
+
+rdgsbase %eax
+rdgsbase %rax
+
+wrfsbase %edi
+wrfsbase %rdi
+
+wrgsbase %edi
+wrgsbase %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 * * U rdfsbasel %eax
+# CHECK-NEXT: 1 100 0.25 * * U rdfsbaseq %rax
+# CHECK-NEXT: 1 100 0.25 * * U rdgsbasel %eax
+# CHECK-NEXT: 1 100 0.25 * * U rdgsbaseq %rax
+# CHECK-NEXT: 1 100 0.25 * * U wrfsbasel %edi
+# CHECK-NEXT: 1 100 0.25 * * U wrfsbaseq %rdi
+# CHECK-NEXT: 1 100 0.25 * * U wrgsbasel %edi
+# CHECK-NEXT: 1 100 0.25 * * U wrgsbaseq %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 2.00 2.00 - - - 2.00 2.00 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - rdfsbasel %eax
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - rdfsbaseq %rax
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - rdgsbasel %eax
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - rdgsbaseq %rax
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - wrfsbasel %edi
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - wrfsbaseq %rdi
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - wrgsbasel %edi
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - wrgsbaseq %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s
new file mode 100644
index 0000000000000..762b6d3caef2b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s
@@ -0,0 +1,442 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+lea 0(), %cx
+lea 0(), %ecx
+lea 0(), %rcx
+lea (%eax), %cx
+lea (%eax), %ecx
+lea (%eax), %rcx
+lea (%rax), %cx
+lea (%rax), %ecx
+lea (%rax), %rcx
+lea (, %ebx), %cx
+lea (, %ebx), %ecx
+lea (, %ebx), %rcx
+lea (, %rbx), %cx
+lea (, %rbx), %ecx
+lea (, %rbx), %rcx
+lea (, %ebx, 1), %cx
+lea (, %ebx, 1), %ecx
+lea (, %ebx, 1), %rcx
+lea (, %rbx, 1), %cx
+lea (, %rbx, 1), %ecx
+lea (, %rbx, 1), %rcx
+lea (, %ebx, 2), %cx
+lea (, %ebx, 2), %ecx
+lea (, %ebx, 2), %rcx
+lea (, %rbx, 2), %cx
+lea (, %rbx, 2), %ecx
+lea (, %rbx, 2), %rcx
+lea (%eax, %ebx), %cx
+lea (%eax, %ebx), %ecx
+lea (%eax, %ebx), %rcx
+lea (%rax, %rbx), %cx
+lea (%rax, %rbx), %ecx
+lea (%rax, %rbx), %rcx
+lea (%eax, %ebx, 1), %cx
+lea (%eax, %ebx, 1), %ecx
+lea (%eax, %ebx, 1), %rcx
+lea (%rax, %rbx, 1), %cx
+lea (%rax, %rbx, 1), %ecx
+lea (%rax, %rbx, 1), %rcx
+lea (%eax, %ebx, 2), %cx
+lea (%eax, %ebx, 2), %ecx
+lea (%eax, %ebx, 2), %rcx
+lea (%rax, %rbx, 2), %cx
+lea (%rax, %rbx, 2), %ecx
+lea (%rax, %rbx, 2), %rcx
+
+lea -16(), %cx
+lea -16(), %ecx
+lea -16(), %rcx
+lea -16(%eax), %cx
+lea -16(%eax), %ecx
+lea -16(%eax), %rcx
+lea -16(%rax), %cx
+lea -16(%rax), %ecx
+lea -16(%rax), %rcx
+lea -16(, %ebx), %cx
+lea -16(, %ebx), %ecx
+lea -16(, %ebx), %rcx
+lea -16(, %rbx), %cx
+lea -16(, %rbx), %ecx
+lea -16(, %rbx), %rcx
+lea -16(, %ebx, 1), %cx
+lea -16(, %ebx, 1), %ecx
+lea -16(, %ebx, 1), %rcx
+lea -16(, %rbx, 1), %cx
+lea -16(, %rbx, 1), %ecx
+lea -16(, %rbx, 1), %rcx
+lea -16(, %ebx, 2), %cx
+lea -16(, %ebx, 2), %ecx
+lea -16(, %ebx, 2), %rcx
+lea -16(, %rbx, 2), %cx
+lea -16(, %rbx, 2), %ecx
+lea -16(, %rbx, 2), %rcx
+lea -16(%eax, %ebx), %cx
+lea -16(%eax, %ebx), %ecx
+lea -16(%eax, %ebx), %rcx
+lea -16(%rax, %rbx), %cx
+lea -16(%rax, %rbx), %ecx
+lea -16(%rax, %rbx), %rcx
+lea -16(%eax, %ebx, 1), %cx
+lea -16(%eax, %ebx, 1), %ecx
+lea -16(%eax, %ebx, 1), %rcx
+lea -16(%rax, %rbx, 1), %cx
+lea -16(%rax, %rbx, 1), %ecx
+lea -16(%rax, %rbx, 1), %rcx
+lea -16(%eax, %ebx, 2), %cx
+lea -16(%eax, %ebx, 2), %ecx
+lea -16(%eax, %ebx, 2), %rcx
+lea -16(%rax, %rbx, 2), %cx
+lea -16(%rax, %rbx, 2), %ecx
+lea -16(%rax, %rbx, 2), %rcx
+
+lea 1024(), %cx
+lea 1024(), %ecx
+lea 1024(), %rcx
+lea 1024(%eax), %cx
+lea 1024(%eax), %ecx
+lea 1024(%eax), %rcx
+lea 1024(%rax), %cx
+lea 1024(%rax), %ecx
+lea 1024(%rax), %rcx
+lea 1024(, %ebx), %cx
+lea 1024(, %ebx), %ecx
+lea 1024(, %ebx), %rcx
+lea 1024(, %rbx), %cx
+lea 1024(, %rbx), %ecx
+lea 1024(, %rbx), %rcx
+lea 1024(, %ebx, 1), %cx
+lea 1024(, %ebx, 1), %ecx
+lea 1024(, %ebx, 1), %rcx
+lea 1024(, %rbx, 1), %cx
+lea 1024(, %rbx, 1), %ecx
+lea 1024(, %rbx, 1), %rcx
+lea 1024(, %ebx, 2), %cx
+lea 1024(, %ebx, 2), %ecx
+lea 1024(, %ebx, 2), %rcx
+lea 1024(, %rbx, 2), %cx
+lea 1024(, %rbx, 2), %ecx
+lea 1024(, %rbx, 2), %rcx
+lea 1024(%eax, %ebx), %cx
+lea 1024(%eax, %ebx), %ecx
+lea 1024(%eax, %ebx), %rcx
+lea 1024(%rax, %rbx), %cx
+lea 1024(%rax, %rbx), %ecx
+lea 1024(%rax, %rbx), %rcx
+lea 1024(%eax, %ebx, 1), %cx
+lea 1024(%eax, %ebx, 1), %ecx
+lea 1024(%eax, %ebx, 1), %rcx
+lea 1024(%rax, %rbx, 1), %cx
+lea 1024(%rax, %rbx, 1), %ecx
+lea 1024(%rax, %rbx, 1), %rcx
+lea 1024(%eax, %ebx, 2), %cx
+lea 1024(%eax, %ebx, 2), %ecx
+lea 1024(%eax, %ebx, 2), %rcx
+lea 1024(%rax, %rbx, 2), %cx
+lea 1024(%rax, %rbx, 2), %ecx
+lea 1024(%rax, %rbx, 2), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 2 2 1.00 leaw 0, %cx
+# CHECK-NEXT: 1 1 1.00 leal 0, %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 0, %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%eax), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%eax), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%eax), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%rax), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%rax), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%rax), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (,%ebx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal (,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (,%rbx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal (,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%eax,%ebx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%eax,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%eax,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw (%rax,%rbx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal (%rax,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq (%rax,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16, %cx
+# CHECK-NEXT: 1 1 1.00 leal -16, %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16, %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%eax), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%eax), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%eax), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%rax), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%rax), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%rax), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(,%ebx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(,%rbx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%eax,%ebx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw -16(%rax,%rbx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal -16(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq -16(%rax,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024, %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024, %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024, %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%eax), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%eax), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%eax), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%rax), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%rax), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%rax), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(,%ebx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(,%rbx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%eax,%ebx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 1.00 leaw 1024(%rax,%rbx,2), %cx
+# CHECK-NEXT: 1 1 1.00 leal 1024(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 1.00 leaq 1024(%rax,%rbx,2), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 9.00 144.00 - - - 9.00 9.00 - - - 9.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 0, %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 0, %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 0, %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%eax), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%eax), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%eax), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%rax), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%rax), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%rax), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (,%ebx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (,%ebx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (,%ebx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (,%rbx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (,%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (,%rbx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (,%ebx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (,%ebx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (,%ebx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (,%rbx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (,%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (,%rbx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (,%ebx,2), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (,%ebx,2), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (,%ebx,2), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (,%rbx,2), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (,%rbx,2), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (,%rbx,2), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%eax,%ebx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%eax,%ebx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%rax,%rbx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%rax,%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%eax,%ebx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%eax,%ebx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%rax,%rbx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%rax,%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%eax,%ebx,2), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%eax,%ebx,2), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%eax,%ebx,2), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%rax,%rbx,2), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%rax,%rbx,2), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%rax,%rbx,2), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16, %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16, %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16, %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%eax), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%eax), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%eax), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%rax), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%rax), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%rax), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(,%ebx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(,%ebx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(,%rbx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(,%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(,%ebx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(,%ebx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(,%rbx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(,%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(,%ebx,2), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(,%ebx,2), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(,%ebx,2), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(,%rbx,2), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(,%rbx,2), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(,%rbx,2), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%eax,%ebx,2), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%eax,%ebx,2), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%rax,%rbx,2), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%rax,%rbx,2), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%rax,%rbx,2), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024, %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024, %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024, %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%eax), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%eax), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%eax), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%rax), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%rax), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%rax), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(,%ebx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(,%ebx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(,%rbx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(,%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(,%ebx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(,%ebx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(,%rbx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(,%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(,%ebx,2), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(,%ebx,2), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(,%ebx,2), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(,%rbx,2), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(,%rbx,2), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(,%rbx,2), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%eax,%ebx,2), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%eax,%ebx,2), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%rax,%rbx,2), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%rax,%rbx,2), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%rax,%rbx,2), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lzcnt.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lzcnt.s
new file mode 100644
index 0000000000000..68179d34d8a82
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lzcnt.s
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+lzcntw %cx, %cx
+lzcntw (%rax), %cx
+
+lzcntl %eax, %ecx
+lzcntl (%rax), %ecx
+
+lzcntq %rax, %rcx
+lzcntq (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 lzcntw %cx, %cx
+# CHECK-NEXT: 2 8 1.00 * lzcntw (%rax), %cx
+# CHECK-NEXT: 1 3 1.00 lzcntl %eax, %ecx
+# CHECK-NEXT: 2 8 1.00 * lzcntl (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 lzcntq %rax, %rcx
+# CHECK-NEXT: 2 8 1.00 * lzcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - 6.00 1.00 1.00 - - - - - - - 1.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - lzcntw %cx, %cx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - lzcntw (%rax), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - lzcntl %eax, %ecx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - lzcntl (%rax), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - lzcntq %rax, %rcx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - lzcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s
new file mode 100644
index 0000000000000..c62ea2963323d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s
@@ -0,0 +1,398 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+emms
+
+movd %eax, %mm2
+movd (%rax), %mm2
+
+movd %mm0, %ecx
+movd %mm0, (%rax)
+
+movq %rax, %mm2
+movq (%rax), %mm2
+
+movq %mm0, %rcx
+movq %mm0, (%rax)
+
+packsswb %mm0, %mm2
+packsswb (%rax), %mm2
+
+packssdw %mm0, %mm2
+packssdw (%rax), %mm2
+
+packuswb %mm0, %mm2
+packuswb (%rax), %mm2
+
+paddb %mm0, %mm2
+paddb (%rax), %mm2
+
+paddd %mm0, %mm2
+paddd (%rax), %mm2
+
+paddsb %mm0, %mm2
+paddsb (%rax), %mm2
+
+paddsw %mm0, %mm2
+paddsw (%rax), %mm2
+
+paddusb %mm0, %mm2
+paddusb (%rax), %mm2
+
+paddusw %mm0, %mm2
+paddusw (%rax), %mm2
+
+paddw %mm0, %mm2
+paddw (%rax), %mm2
+
+pand %mm0, %mm2
+pand (%rax), %mm2
+
+pandn %mm0, %mm2
+pandn (%rax), %mm2
+
+pcmpeqb %mm0, %mm2
+pcmpeqb (%rax), %mm2
+
+pcmpeqd %mm0, %mm2
+pcmpeqd (%rax), %mm2
+
+pcmpeqw %mm0, %mm2
+pcmpeqw (%rax), %mm2
+
+pcmpgtb %mm0, %mm2
+pcmpgtb (%rax), %mm2
+
+pcmpgtd %mm0, %mm2
+pcmpgtd (%rax), %mm2
+
+pcmpgtw %mm0, %mm2
+pcmpgtw (%rax), %mm2
+
+pmaddwd %mm0, %mm2
+pmaddwd (%rax), %mm2
+
+pmulhw %mm0, %mm2
+pmulhw (%rax), %mm2
+
+pmullw %mm0, %mm2
+pmullw (%rax), %mm2
+
+por %mm0, %mm2
+por (%rax), %mm2
+
+pslld $1, %mm2
+pslld %mm0, %mm2
+pslld (%rax), %mm2
+
+psllq $1, %mm2
+psllq %mm0, %mm2
+psllq (%rax), %mm2
+
+psllw $1, %mm2
+psllw %mm0, %mm2
+psllw (%rax), %mm2
+
+psrad $1, %mm2
+psrad %mm0, %mm2
+psrad (%rax), %mm2
+
+psraw $1, %mm2
+psraw %mm0, %mm2
+psraw (%rax), %mm2
+
+psrld $1, %mm2
+psrld %mm0, %mm2
+psrld (%rax), %mm2
+
+psrlq $1, %mm2
+psrlq %mm0, %mm2
+psrlq (%rax), %mm2
+
+psrlw $1, %mm2
+psrlw %mm0, %mm2
+psrlw (%rax), %mm2
+
+psubb %mm0, %mm2
+psubb (%rax), %mm2
+
+psubd %mm0, %mm2
+psubd (%rax), %mm2
+
+psubsb %mm0, %mm2
+psubsb (%rax), %mm2
+
+psubsw %mm0, %mm2
+psubsw (%rax), %mm2
+
+psubusb %mm0, %mm2
+psubusb (%rax), %mm2
+
+psubusw %mm0, %mm2
+psubusw (%rax), %mm2
+
+psubw %mm0, %mm2
+psubw (%rax), %mm2
+
+punpckhbw %mm0, %mm2
+punpckhbw (%rax), %mm2
+
+punpckhdq %mm0, %mm2
+punpckhdq (%rax), %mm2
+
+punpckhwd %mm0, %mm2
+punpckhwd (%rax), %mm2
+
+punpcklbw %mm0, %mm2
+punpcklbw (%rax), %mm2
+
+punpckldq %mm0, %mm2
+punpckldq (%rax), %mm2
+
+punpcklwd %mm0, %mm2
+punpcklwd (%rax), %mm2
+
+pxor %mm0, %mm2
+pxor (%rax), %mm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 10 10 4.50 * * U emms
+# CHECK-NEXT: 1 3 1.00 movd %eax, %mm2
+# CHECK-NEXT: 1 8 0.33 * movd (%rax), %mm2
+# CHECK-NEXT: 1 3 1.00 movd %mm0, %ecx
+# CHECK-NEXT: 2 18 0.50 * U movd %mm0, (%rax)
+# CHECK-NEXT: 1 3 1.00 movq %rax, %mm2
+# CHECK-NEXT: 1 8 0.33 * movq (%rax), %mm2
+# CHECK-NEXT: 1 3 1.00 movq %mm0, %rcx
+# CHECK-NEXT: 2 12 0.50 * movq %mm0, (%rax)
+# CHECK-NEXT: 2 4 2.00 packsswb %mm0, %mm2
+# CHECK-NEXT: 3 12 2.00 * packsswb (%rax), %mm2
+# CHECK-NEXT: 2 4 2.00 packssdw %mm0, %mm2
+# CHECK-NEXT: 3 12 2.00 * packssdw (%rax), %mm2
+# CHECK-NEXT: 2 4 2.00 packuswb %mm0, %mm2
+# CHECK-NEXT: 3 12 2.00 * packuswb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 paddb %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * paddb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 paddd %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * paddd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 paddsb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * paddsb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 paddsw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * paddsw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 paddusb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * paddusb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 paddusw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * paddusw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 paddw %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * paddw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pand %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * pand (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pandn %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * pandn (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpeqb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pcmpeqb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpeqd %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pcmpeqd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpeqw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pcmpeqw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpgtb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pcmpgtb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpgtd %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pcmpgtd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpgtw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pcmpgtw (%rax), %mm2
+# CHECK-NEXT: 1 5 1.00 pmaddwd %mm0, %mm2
+# CHECK-NEXT: 2 13 1.00 * pmaddwd (%rax), %mm2
+# CHECK-NEXT: 1 5 1.00 pmulhw %mm0, %mm2
+# CHECK-NEXT: 2 13 1.00 * pmulhw (%rax), %mm2
+# CHECK-NEXT: 1 5 1.00 pmullw %mm0, %mm2
+# CHECK-NEXT: 2 13 1.00 * pmullw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 por %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * por (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pslld $1, %mm2
+# CHECK-NEXT: 1 1 1.00 pslld %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pslld (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psllq $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psllq %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psllq (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psllw $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psllw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psllw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psrad $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psrad %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psrad (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psraw $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psraw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psraw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psrld $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psrld %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psrld (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psrlq $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psrlq %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psrlq (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psrlw $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psrlw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psrlw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psubb %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psubb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psubd %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psubd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psubsb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psubsb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psubsw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psubsw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psubusb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psubusb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psubusw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psubusw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psubw %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psubw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 punpckhbw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * punpckhbw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 punpckhdq %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * punpckhdq (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 punpckhwd %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * punpckhwd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 punpcklbw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * punpcklbw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 punpckldq %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * punpckldq (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 punpcklwd %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * punpcklwd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pxor %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * pxor (%rax), %mm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 75.50 - 15.33 15.33 1.00 40.00 0.50 1.00 1.00 1.00 - 15.33 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 5.50 - - - - 4.00 0.50 - - - - - - emms
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - movd %eax, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movd (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - movd %mm0, %ecx
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movd %mm0, (%rax)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - movq %rax, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movq (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - movq %mm0, %rcx
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movq %mm0, (%rax)
+# CHECK-NEXT: - - - - - 2.00 - - - - - - - packsswb %mm0, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 2.00 - - - - - 0.33 - packsswb (%rax), %mm2
+# CHECK-NEXT: - - - - - 2.00 - - - - - - - packssdw %mm0, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 2.00 - - - - - 0.33 - packssdw (%rax), %mm2
+# CHECK-NEXT: - - - - - 2.00 - - - - - - - packuswb %mm0, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 2.00 - - - - - 0.33 - packuswb (%rax), %mm2
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - paddb %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 0.50 - - - - - 0.33 - paddb (%rax), %mm2
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - paddd %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 0.50 - - - - - 0.33 - paddd (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - paddsb %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - paddsb (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - paddsw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - paddsw (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - paddusb %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - paddusb (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - paddusw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - paddusw (%rax), %mm2
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - paddw %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 0.50 - - - - - 0.33 - paddw (%rax), %mm2
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - pand %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 0.50 - - - - - 0.33 - pand (%rax), %mm2
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - pandn %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 0.50 - - - - - 0.33 - pandn (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pcmpeqb %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pcmpeqb (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pcmpeqd %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pcmpeqd (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pcmpeqw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pcmpeqw (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pcmpgtb %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pcmpgtb (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pcmpgtd %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pcmpgtd (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pcmpgtw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pcmpgtw (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pmaddwd %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pmaddwd (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pmulhw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pmulhw (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pmullw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pmullw (%rax), %mm2
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - por %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 0.50 - - - - - 0.33 - por (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pslld $1, %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pslld %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pslld (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psllq $1, %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psllq %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psllq (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psllw $1, %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psllw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psllw (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psrad $1, %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psrad %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psrad (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psraw $1, %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psraw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psraw (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psrld $1, %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psrld %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psrld (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psrlq $1, %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psrlq %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psrlq (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psrlw $1, %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psrlw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psrlw (%rax), %mm2
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - psubb %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 0.50 - - - - - 0.33 - psubb (%rax), %mm2
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - psubd %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 0.50 - - - - - 0.33 - psubd (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psubsb %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psubsb (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psubsw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psubsw (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psubusb %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psubusb (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psubusw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psubusw (%rax), %mm2
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - psubw %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 0.50 - - - - - 0.33 - psubw (%rax), %mm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - punpckhbw %mm0, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - punpckhbw (%rax), %mm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - punpckhdq %mm0, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - punpckhdq (%rax), %mm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - punpckhwd %mm0, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - punpckhwd (%rax), %mm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - punpcklbw %mm0, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - punpcklbw (%rax), %mm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - punpckldq %mm0, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - punpckldq (%rax), %mm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - punpcklwd %mm0, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - punpcklwd (%rax), %mm2
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - pxor %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 0.50 - - - - - 0.33 - pxor (%rax), %mm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-movbe.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-movbe.s
new file mode 100644
index 0000000000000..3aa3122609563
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-movbe.s
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+movbe %cx, (%rax)
+movbe (%rax), %cx
+
+movbe %ecx, (%rax)
+movbe (%rax), %ecx
+
+movbe %rcx, (%rax)
+movbe (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 3 12 0.50 * movbew %cx, (%rax)
+# CHECK-NEXT: 3 7 0.50 * movbew (%rax), %cx
+# CHECK-NEXT: 3 12 1.00 * movbel %ecx, (%rax)
+# CHECK-NEXT: 2 6 1.00 * movbel (%rax), %ecx
+# CHECK-NEXT: 4 12 1.00 * movbeq %rcx, (%rax)
+# CHECK-NEXT: 3 7 1.00 * movbeq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 2.20 4.20 1.00 1.00 1.50 0.20 2.20 1.50 1.50 1.50 0.20 1.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - movbew %cx, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 - 0.20 0.70 - - - 0.20 0.33 - movbew (%rax), %cx
+# CHECK-NEXT: - 1.00 - - 0.50 - - 0.50 0.50 0.50 - - - movbel %ecx, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - movbel (%rax), %ecx
+# CHECK-NEXT: 0.50 1.00 - - 0.50 - 0.50 0.50 0.50 0.50 - - - movbeq %rcx, (%rax)
+# CHECK-NEXT: 0.50 1.00 0.33 0.33 - - 0.50 - - - - 0.33 - movbeq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s
new file mode 100644
index 0000000000000..871035dbe34a6
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s
@@ -0,0 +1,41 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+pclmulqdq $11, %xmm0, %xmm2
+pclmulqdq $11, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 pclmulqdq $11, %xmm0, %xmm2
+# CHECK-NEXT: 2 10 1.00 * pclmulqdq $11, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - 0.33 0.33 - 2.00 - - - - - 0.33 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - pclmulqdq $11, %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - pclmulqdq $11, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-popcnt.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-popcnt.s
new file mode 100644
index 0000000000000..9428d9015e212
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-popcnt.s
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+popcntw %cx, %cx
+popcntw (%rax), %cx
+
+popcntl %eax, %ecx
+popcntl (%rax), %ecx
+
+popcntq %rax, %rcx
+popcntq (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 popcntw %cx, %cx
+# CHECK-NEXT: 2 8 1.00 * popcntw (%rax), %cx
+# CHECK-NEXT: 1 3 1.00 popcntl %eax, %ecx
+# CHECK-NEXT: 2 8 1.00 * popcntl (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 popcntq %rax, %rcx
+# CHECK-NEXT: 2 8 1.00 * popcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - 6.00 1.00 1.00 - - - - - - - 1.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - popcntw %cx, %cx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - popcntw (%rax), %cx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - popcntl %eax, %ecx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - popcntl (%rax), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - popcntq %rax, %rcx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - popcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-prefetchw.s
new file mode 100644
index 0000000000000..ff872dacaf326
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-prefetchw.s
@@ -0,0 +1,41 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+prefetch (%rax)
+prefetchw (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.33 * * prefetch (%rax)
+# CHECK-NEXT: 1 5 0.33 * * prefetchw (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - 0.67 0.67 - - - - - - - 0.67 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - prefetch (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - prefetchw (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdrand.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdrand.s
new file mode 100644
index 0000000000000..b4a2252310804
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdrand.s
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+rdrand %ax
+rdrand %eax
+rdrand %rax
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 25 1386 7.00 U rdrandw %ax
+# CHECK-NEXT: 25 100 7.00 U rdrandl %eax
+# CHECK-NEXT: 25 100 7.00 U rdrandq %rax
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 17.30 27.30 1.00 1.00 - 14.30 11.30 - - - 1.80 1.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 5.77 9.10 0.33 0.33 - 4.77 3.77 - - - 0.60 0.33 - rdrandw %ax
+# CHECK-NEXT: 5.77 9.10 0.33 0.33 - 4.77 3.77 - - - 0.60 0.33 - rdrandl %eax
+# CHECK-NEXT: 5.77 9.10 0.33 0.33 - 4.77 3.77 - - - 0.60 0.33 - rdrandq %rax
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdseed.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdseed.s
new file mode 100644
index 0000000000000..8b8aff25b5163
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdseed.s
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+rdseed %ax
+rdseed %eax
+rdseed %rax
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 25 1381 7.00 U rdseedw %ax
+# CHECK-NEXT: 25 100 7.00 U rdseedl %eax
+# CHECK-NEXT: 25 100 7.00 U rdseedq %rax
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 19.50 24.00 1.00 1.00 - 18.00 10.50 - - - - 1.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 6.50 8.00 0.33 0.33 - 6.00 3.50 - - - - 0.33 - rdseedw %ax
+# CHECK-NEXT: 6.50 8.00 0.33 0.33 - 6.00 3.50 - - - - 0.33 - rdseedl %eax
+# CHECK-NEXT: 6.50 8.00 0.33 0.33 - 6.00 3.50 - - - - 0.33 - rdseedq %rax
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s
new file mode 100644
index 0000000000000..b292826913d91
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s
@@ -0,0 +1,466 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+addps %xmm0, %xmm2
+addps (%rax), %xmm2
+
+addss %xmm0, %xmm2
+addss (%rax), %xmm2
+
+andnps %xmm0, %xmm2
+andnps (%rax), %xmm2
+
+andps %xmm0, %xmm2
+andps (%rax), %xmm2
+
+cmpps $0, %xmm0, %xmm2
+cmpps $0, (%rax), %xmm2
+
+cmpss $0, %xmm0, %xmm2
+cmpss $0, (%rax), %xmm2
+
+comiss %xmm0, %xmm1
+comiss (%rax), %xmm1
+
+cvtpi2ps %mm0, %xmm2
+cvtpi2ps (%rax), %xmm2
+
+cvtps2pi %xmm0, %mm2
+cvtps2pi (%rax), %mm2
+
+cvtsi2ss %ecx, %xmm2
+cvtsi2ss %rcx, %xmm2
+cvtsi2ss (%rax), %xmm2
+cvtsi2ss (%rax), %xmm2
+
+cvtss2si %xmm0, %ecx
+cvtss2si %xmm0, %rcx
+cvtss2si (%rax), %ecx
+cvtss2si (%rax), %rcx
+
+cvttps2pi %xmm0, %mm2
+cvttps2pi (%rax), %mm2
+
+cvttss2si %xmm0, %ecx
+cvttss2si %xmm0, %rcx
+cvttss2si (%rax), %ecx
+cvttss2si (%rax), %rcx
+
+divps %xmm0, %xmm2
+divps (%rax), %xmm2
+
+divss %xmm0, %xmm2
+divss (%rax), %xmm2
+
+ldmxcsr (%rax)
+
+maskmovq %mm0, %mm1
+
+maxps %xmm0, %xmm2
+maxps (%rax), %xmm2
+
+maxss %xmm0, %xmm2
+maxss (%rax), %xmm2
+
+minps %xmm0, %xmm2
+minps (%rax), %xmm2
+
+minss %xmm0, %xmm2
+minss (%rax), %xmm2
+
+movaps %xmm0, %xmm2
+movaps %xmm0, (%rax)
+movaps (%rax), %xmm2
+
+movhlps %xmm0, %xmm2
+movlhps %xmm0, %xmm2
+
+movhps %xmm0, (%rax)
+movhps (%rax), %xmm2
+
+movlps %xmm0, (%rax)
+movlps (%rax), %xmm2
+
+movmskps %xmm0, %rcx
+
+movntps %xmm0, (%rax)
+movntq %mm0, (%rax)
+
+movss %xmm0, %xmm2
+movss %xmm0, (%rax)
+movss (%rax), %xmm2
+
+movups %xmm0, %xmm2
+movups %xmm0, (%rax)
+movups (%rax), %xmm2
+
+mulps %xmm0, %xmm2
+mulps (%rax), %xmm2
+
+mulss %xmm0, %xmm2
+mulss (%rax), %xmm2
+
+orps %xmm0, %xmm2
+orps (%rax), %xmm2
+
+pavgb %mm0, %mm2
+pavgb (%rax), %mm2
+
+pavgw %mm0, %mm2
+pavgw (%rax), %mm2
+
+pextrw $1, %mm0, %rcx
+
+pinsrw $1, %rax, %mm2
+pinsrw $1, (%rax), %mm2
+
+pmaxsw %mm0, %mm2
+pmaxsw (%rax), %mm2
+
+pmaxub %mm0, %mm2
+pmaxub (%rax), %mm2
+
+pminsw %mm0, %mm2
+pminsw (%rax), %mm2
+
+pminub %mm0, %mm2
+pminub (%rax), %mm2
+
+pmovmskb %mm0, %rcx
+
+pmulhuw %mm0, %mm2
+pmulhuw (%rax), %mm2
+
+prefetcht0 (%rax)
+prefetcht1 (%rax)
+prefetcht2 (%rax)
+prefetchnta (%rax)
+
+psadbw %mm0, %mm2
+psadbw (%rax), %mm2
+
+pshufw $1, %mm0, %mm2
+pshufw $1, (%rax), %mm2
+
+rcpps %xmm0, %xmm2
+rcpps (%rax), %xmm2
+
+rcpss %xmm0, %xmm2
+rcpss (%rax), %xmm2
+
+rsqrtps %xmm0, %xmm2
+rsqrtps (%rax), %xmm2
+
+rsqrtss %xmm0, %xmm2
+rsqrtss (%rax), %xmm2
+
+sfence
+
+shufps $1, %xmm0, %xmm2
+shufps $1, (%rax), %xmm2
+
+sqrtps %xmm0, %xmm2
+sqrtps (%rax), %xmm2
+
+sqrtss %xmm0, %xmm2
+sqrtss (%rax), %xmm2
+
+stmxcsr (%rax)
+
+subps %xmm0, %xmm2
+subps (%rax), %xmm2
+
+subss %xmm0, %xmm2
+subss (%rax), %xmm2
+
+ucomiss %xmm0, %xmm1
+ucomiss (%rax), %xmm1
+
+unpckhps %xmm0, %xmm2
+unpckhps (%rax), %xmm2
+
+unpcklps %xmm0, %xmm2
+unpcklps (%rax), %xmm2
+
+xorps %xmm0, %xmm2
+xorps (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addps %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * addps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addss %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * addss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 andnps %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * andnps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 andps %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * andps (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cmpeqps %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cmpeqps (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cmpeqss %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cmpeqss (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 comiss %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * comiss (%rax), %xmm1
+# CHECK-NEXT: 2 7 1.00 cvtpi2ps %mm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtpi2ps (%rax), %xmm2
+# CHECK-NEXT: 2 9 1.00 cvtps2pi %xmm0, %mm2
+# CHECK-NEXT: 2 13 1.00 * cvtps2pi (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 cvtsi2ss %ecx, %xmm2
+# CHECK-NEXT: 3 8 2.00 cvtsi2ss %rcx, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 cvtss2si %xmm0, %ecx
+# CHECK-NEXT: 3 8 1.00 cvtss2si %xmm0, %rcx
+# CHECK-NEXT: 3 12 1.00 * cvtss2si (%rax), %ecx
+# CHECK-NEXT: 3 12 1.00 * cvtss2si (%rax), %rcx
+# CHECK-NEXT: 2 9 1.00 cvttps2pi %xmm0, %mm2
+# CHECK-NEXT: 2 13 1.00 * cvttps2pi (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 cvttss2si %xmm0, %ecx
+# CHECK-NEXT: 3 8 1.00 cvttss2si %xmm0, %rcx
+# CHECK-NEXT: 3 12 1.00 * cvttss2si (%rax), %ecx
+# CHECK-NEXT: 3 12 1.00 * cvttss2si (%rax), %rcx
+# CHECK-NEXT: 1 11 1.00 divps %xmm0, %xmm2
+# CHECK-NEXT: 2 18 1.00 * divps (%rax), %xmm2
+# CHECK-NEXT: 1 11 1.00 divss %xmm0, %xmm2
+# CHECK-NEXT: 2 18 1.00 * divss (%rax), %xmm2
+# CHECK-NEXT: 4 7 1.00 * * U ldmxcsr (%rax)
+# CHECK-NEXT: 4 12 2.00 * * U maskmovq %mm0, %mm1
+# CHECK-NEXT: 1 4 0.50 maxps %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * maxps (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 maxss %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * maxss (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 minps %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * minps (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 minss %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * minss (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 movaps %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movaps %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * movaps (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movhlps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 movlhps %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movhps %xmm0, (%rax)
+# CHECK-NEXT: 2 8 1.00 * movhps (%rax), %xmm2
+# CHECK-NEXT: 2 12 0.50 * movlps %xmm0, (%rax)
+# CHECK-NEXT: 2 8 0.50 * movlps (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 movmskps %xmm0, %ecx
+# CHECK-NEXT: 2 518 0.50 * movntps %xmm0, (%rax)
+# CHECK-NEXT: 2 511 0.50 * * U movntq %mm0, (%rax)
+# CHECK-NEXT: 1 1 0.33 movss %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movss %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * movss (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 movups %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movups %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * movups (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 mulps %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * mulps (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 mulss %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * mulss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 orps %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * orps (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 pavgb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pavgb (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pavgw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pavgw (%rax), %mm2
+# CHECK-NEXT: 2 4 1.00 pextrw $1, %mm0, %ecx
+# CHECK-NEXT: 2 4 2.00 pinsrw $1, %eax, %mm2
+# CHECK-NEXT: 2 9 1.00 * pinsrw $1, (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pmaxsw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pmaxsw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pmaxub %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pmaxub (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pminsw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pminsw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pminub %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pminub (%rax), %mm2
+# CHECK-NEXT: 1 3 1.00 pmovmskb %mm0, %ecx
+# CHECK-NEXT: 1 5 1.00 pmulhuw %mm0, %mm2
+# CHECK-NEXT: 2 13 1.00 * pmulhuw (%rax), %mm2
+# CHECK-NEXT: 1 0 0.33 * * prefetcht0 (%rax)
+# CHECK-NEXT: 1 0 0.33 * * prefetcht1 (%rax)
+# CHECK-NEXT: 1 0 0.33 * * prefetcht2 (%rax)
+# CHECK-NEXT: 1 0 0.33 * * prefetchnta (%rax)
+# CHECK-NEXT: 1 3 1.00 psadbw %mm0, %mm2
+# CHECK-NEXT: 2 11 1.00 * psadbw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pshufw $1, %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pshufw $1, (%rax), %mm2
+# CHECK-NEXT: 1 4 1.00 rcpps %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * rcpps (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 rcpss %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * rcpss (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 rsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * rsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 rsqrtss %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * rsqrtss (%rax), %xmm2
+# CHECK-NEXT: 2 2 0.50 * * U sfence
+# CHECK-NEXT: 1 1 0.50 shufps $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * shufps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 12 1.00 sqrtps %xmm0, %xmm2
+# CHECK-NEXT: 2 19 1.00 * sqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 12 1.00 sqrtss %xmm0, %xmm2
+# CHECK-NEXT: 2 19 1.00 * sqrtss (%rax), %xmm2
+# CHECK-NEXT: 4 12 1.00 * U stmxcsr (%rax)
+# CHECK-NEXT: 1 3 0.50 subps %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * subps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subss %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * subss (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 ucomiss %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * ucomiss (%rax), %xmm1
+# CHECK-NEXT: 1 1 1.00 unpckhps %xmm0, %xmm2
+# CHECK-NEXT: 2 8 1.00 * unpckhps (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 unpcklps %xmm0, %xmm2
+# CHECK-NEXT: 2 8 1.00 * unpcklps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 xorps %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * xorps (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 74.00 24.50 19.33 19.33 5.00 29.50 1.00 5.00 5.00 5.00 - 19.33 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - addps %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - addps (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - addss %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - addss (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - andnps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - andnps (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - andps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - andps (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cmpeqps %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cmpeqps (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cmpeqss %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cmpeqss (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - comiss %xmm0, %xmm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - comiss (%rax), %xmm1
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - cvtpi2ps %mm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtpi2ps (%rax), %xmm2
+# CHECK-NEXT: 1.33 0.33 - - - 0.33 - - - - - - - cvtps2pi %xmm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - cvtps2pi (%rax), %mm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvtsi2ss %ecx, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 2.00 - - - - - - - cvtsi2ss %rcx, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - cvtss2si %xmm0, %ecx
+# CHECK-NEXT: 1.50 0.50 - - - 1.00 - - - - - - - cvtss2si %xmm0, %rcx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtss2si (%rax), %ecx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtss2si (%rax), %rcx
+# CHECK-NEXT: 1.33 0.33 - - - 0.33 - - - - - - - cvttps2pi %xmm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - cvttps2pi (%rax), %mm2
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - cvttss2si %xmm0, %ecx
+# CHECK-NEXT: 1.50 0.50 - - - 1.00 - - - - - - - cvttss2si %xmm0, %rcx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvttss2si (%rax), %ecx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvttss2si (%rax), %rcx
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - divps %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - divps (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - divss %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - divss (%rax), %xmm2
+# CHECK-NEXT: 1.83 0.33 0.33 0.33 - 0.33 0.50 - - - - 0.33 - ldmxcsr (%rax)
+# CHECK-NEXT: 2.00 - - - 0.50 - - 0.50 0.50 0.50 - - - maskmovq %mm0, %mm1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - maxps %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - maxps (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - maxss %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - maxss (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - minps %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - minps (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - minss %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - minss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - movaps %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movaps %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movaps (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - movhlps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - movlhps %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movhps %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - movhps (%rax), %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movlps %xmm0, (%rax)
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - movlps (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - movmskps %xmm0, %ecx
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movntps %xmm0, (%rax)
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movntq %mm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - movss %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movss %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - movups %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movups %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movups (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mulps %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - mulps (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mulss %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - mulss (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - orps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - orps (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pavgb %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pavgb (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pavgw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pavgw (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - pextrw $1, %mm0, %ecx
+# CHECK-NEXT: - - - - - 2.00 - - - - - - - pinsrw $1, %eax, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - pinsrw $1, (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pmaxsw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pmaxsw (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pmaxub %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pmaxub (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pminsw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pminsw (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pminub %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pminub (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pmovmskb %mm0, %ecx
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pmulhuw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pmulhuw (%rax), %mm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - prefetcht0 (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - prefetcht1 (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - prefetcht2 (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - prefetchnta (%rax)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - psadbw %mm0, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - psadbw (%rax), %mm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - pshufw $1, %mm0, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - pshufw $1, (%rax), %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - rcpps %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - rcpps (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - rcpss %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - rcpss (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - rsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - rsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - rsqrtss %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - rsqrtss (%rax), %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - sfence
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - shufps $1, %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - shufps $1, (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - sqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - sqrtps (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - sqrtss %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - sqrtss (%rax), %xmm2
+# CHECK-NEXT: 1.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - stmxcsr (%rax)
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - subps %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - subps (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - subss %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - subss (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - ucomiss %xmm0, %xmm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - ucomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - unpckhps %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - unpckhps (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - unpcklps %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - unpcklps (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - xorps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - xorps (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s
new file mode 100644
index 0000000000000..964caa1d7f73c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s
@@ -0,0 +1,965 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+addpd %xmm0, %xmm2
+addpd (%rax), %xmm2
+
+addsd %xmm0, %xmm2
+addsd (%rax), %xmm2
+
+andnpd %xmm0, %xmm2
+andnpd (%rax), %xmm2
+
+andpd %xmm0, %xmm2
+andpd (%rax), %xmm2
+
+clflush (%rax)
+
+cmppd $0, %xmm0, %xmm2
+cmppd $0, (%rax), %xmm2
+
+cmpsd $0, %xmm0, %xmm2
+cmpsd $0, (%rax), %xmm2
+
+comisd %xmm0, %xmm1
+comisd (%rax), %xmm1
+
+cvtdq2pd %xmm0, %xmm2
+cvtdq2pd (%rax), %xmm2
+
+cvtdq2ps %xmm0, %xmm2
+cvtdq2ps (%rax), %xmm2
+
+cvtpd2dq %xmm0, %xmm2
+cvtpd2dq (%rax), %xmm2
+
+cvtpd2pi %xmm0, %mm2
+cvtpd2pi (%rax), %mm2
+
+cvtpd2ps %xmm0, %xmm2
+cvtpd2ps (%rax), %xmm2
+
+cvtpi2pd %mm0, %xmm2
+cvtpi2pd (%rax), %xmm2
+
+cvtps2dq %xmm0, %xmm2
+cvtps2dq (%rax), %xmm2
+
+cvtps2pd %xmm0, %xmm2
+cvtps2pd (%rax), %xmm2
+
+cvtsd2si %xmm0, %ecx
+cvtsd2si %xmm0, %rcx
+cvtsd2si (%rax), %ecx
+cvtsd2si (%rax), %rcx
+
+cvtsd2ss %xmm0, %xmm2
+cvtsd2ss (%rax), %xmm2
+
+cvtsi2sd %ecx, %xmm2
+cvtsi2sd %rcx, %xmm2
+cvtsi2sd (%rax), %xmm2
+cvtsi2sd (%rax), %xmm2
+
+cvtss2sd %xmm0, %xmm2
+cvtss2sd (%rax), %xmm2
+
+cvttpd2dq %xmm0, %xmm2
+cvttpd2dq (%rax), %xmm2
+
+cvttpd2pi %xmm0, %mm2
+cvttpd2pi (%rax), %mm2
+
+cvttps2dq %xmm0, %xmm2
+cvttps2dq (%rax), %xmm2
+
+cvttsd2si %xmm0, %ecx
+cvttsd2si %xmm0, %rcx
+cvttsd2si (%rax), %ecx
+cvttsd2si (%rax), %rcx
+
+divpd %xmm0, %xmm2
+divpd (%rax), %xmm2
+
+divsd %xmm0, %xmm2
+divsd (%rax), %xmm2
+
+lfence
+
+maskmovdqu %xmm0, %xmm1
+
+maxpd %xmm0, %xmm2
+maxpd (%rax), %xmm2
+
+maxsd %xmm0, %xmm2
+maxsd (%rax), %xmm2
+
+mfence
+
+minpd %xmm0, %xmm2
+minpd (%rax), %xmm2
+
+minsd %xmm0, %xmm2
+minsd (%rax), %xmm2
+
+movapd %xmm0, %xmm2
+movapd %xmm0, (%rax)
+movapd (%rax), %xmm2
+
+movd %eax, %xmm2
+movd (%rax), %xmm2
+
+movd %xmm0, %ecx
+movd %xmm0, (%rax)
+
+movdqa %xmm0, %xmm2
+movdqa %xmm0, (%rax)
+movdqa (%rax), %xmm2
+
+movdqu %xmm0, %xmm2
+movdqu %xmm0, (%rax)
+movdqu (%rax), %xmm2
+
+movdq2q %xmm0, %mm2
+
+movhpd %xmm0, (%rax)
+movhpd (%rax), %xmm2
+
+movlpd %xmm0, (%rax)
+movlpd (%rax), %xmm2
+
+movmskpd %xmm0, %rcx
+
+movntil %eax, (%rax)
+movntiq %rax, (%rax)
+
+movntdq %xmm0, (%rax)
+movntpd %xmm0, (%rax)
+
+movq %xmm0, %xmm2
+
+movq %rax, %xmm2
+movq (%rax), %xmm2
+
+movq %xmm0, %rcx
+movq %xmm0, (%rax)
+
+movq2dq %mm0, %xmm2
+
+movsd %xmm0, %xmm2
+movsd %xmm0, (%rax)
+movsd (%rax), %xmm2
+
+movupd %xmm0, %xmm2
+movupd %xmm0, (%rax)
+movupd (%rax), %xmm2
+
+mulpd %xmm0, %xmm2
+mulpd (%rax), %xmm2
+
+mulsd %xmm0, %xmm2
+mulsd (%rax), %xmm2
+
+orpd %xmm0, %xmm2
+orpd (%rax), %xmm2
+
+packssdw %xmm0, %xmm2
+packssdw (%rax), %xmm2
+
+packsswb %xmm0, %xmm2
+packsswb (%rax), %xmm2
+
+packuswb %xmm0, %xmm2
+packuswb (%rax), %xmm2
+
+paddb %xmm0, %xmm2
+paddb (%rax), %xmm2
+
+paddd %xmm0, %xmm2
+paddd (%rax), %xmm2
+
+paddq %mm0, %mm2
+paddq (%rax), %mm2
+
+paddq %xmm0, %xmm2
+paddq (%rax), %xmm2
+
+paddsb %xmm0, %xmm2
+paddsb (%rax), %xmm2
+
+paddsw %xmm0, %xmm2
+paddsw (%rax), %xmm2
+
+paddusb %xmm0, %xmm2
+paddusb (%rax), %xmm2
+
+paddusw %xmm0, %xmm2
+paddusw (%rax), %xmm2
+
+paddw %xmm0, %xmm2
+paddw (%rax), %xmm2
+
+pand %xmm0, %xmm2
+pand (%rax), %xmm2
+
+pandn %xmm0, %xmm2
+pandn (%rax), %xmm2
+
+pavgb %xmm0, %xmm2
+pavgb (%rax), %xmm2
+
+pavgw %xmm0, %xmm2
+pavgw (%rax), %xmm2
+
+pcmpeqb %xmm0, %xmm2
+pcmpeqb (%rax), %xmm2
+
+pcmpeqd %xmm0, %xmm2
+pcmpeqd (%rax), %xmm2
+
+pcmpeqw %xmm0, %xmm2
+pcmpeqw (%rax), %xmm2
+
+pcmpgtb %xmm0, %xmm2
+pcmpgtb (%rax), %xmm2
+
+pcmpgtd %xmm0, %xmm2
+pcmpgtd (%rax), %xmm2
+
+pcmpgtw %xmm0, %xmm2
+pcmpgtw (%rax), %xmm2
+
+pextrw $1, %xmm0, %rcx
+
+pinsrw $1, %rax, %xmm0
+pinsrw $1, (%rax), %xmm0
+
+pmaddwd %xmm0, %xmm2
+pmaddwd (%rax), %xmm2
+
+pmaxsw %xmm0, %xmm2
+pmaxsw (%rax), %xmm2
+
+pmaxub %xmm0, %xmm2
+pmaxub (%rax), %xmm2
+
+pminsw %xmm0, %xmm2
+pminsw (%rax), %xmm2
+
+pminub %xmm0, %xmm2
+pminub (%rax), %xmm2
+
+pmovmskb %xmm0, %rcx
+
+pmulhuw %xmm0, %xmm2
+pmulhuw (%rax), %xmm2
+
+pmulhw %xmm0, %xmm2
+pmulhw (%rax), %xmm2
+
+pmullw %xmm0, %xmm2
+pmullw (%rax), %xmm2
+
+pmuludq %mm0, %mm2
+pmuludq (%rax), %mm2
+
+pmuludq %xmm0, %xmm2
+pmuludq (%rax), %xmm2
+
+por %xmm0, %xmm2
+por (%rax), %xmm2
+
+psadbw %xmm0, %xmm2
+psadbw (%rax), %xmm2
+
+pshufd $1, %xmm0, %xmm2
+pshufd $1, (%rax), %xmm2
+
+pshufhw $1, %xmm0, %xmm2
+pshufhw $1, (%rax), %xmm2
+
+pshuflw $1, %xmm0, %xmm2
+pshuflw $1, (%rax), %xmm2
+
+pslld $1, %xmm2
+pslld %xmm0, %xmm2
+pslld (%rax), %xmm2
+
+pslldq $1, %xmm2
+
+psllq $1, %xmm2
+psllq %xmm0, %xmm2
+psllq (%rax), %xmm2
+
+psllw $1, %xmm2
+psllw %xmm0, %xmm2
+psllw (%rax), %xmm2
+
+psrad $1, %xmm2
+psrad %xmm0, %xmm2
+psrad (%rax), %xmm2
+
+psraw $1, %xmm2
+psraw %xmm0, %xmm2
+psraw (%rax), %xmm2
+
+psrld $1, %xmm2
+psrld %xmm0, %xmm2
+psrld (%rax), %xmm2
+
+psrldq $1, %xmm2
+
+psrlq $1, %xmm2
+psrlq %xmm0, %xmm2
+psrlq (%rax), %xmm2
+
+psrlw $1, %xmm2
+psrlw %xmm0, %xmm2
+psrlw (%rax), %xmm2
+
+psubb %xmm0, %xmm2
+psubb (%rax), %xmm2
+
+psubd %xmm0, %xmm2
+psubd (%rax), %xmm2
+
+psubq %mm0, %mm2
+psubq (%rax), %mm2
+
+psubq %xmm0, %xmm2
+psubq (%rax), %xmm2
+
+psubsb %xmm0, %xmm2
+psubsb (%rax), %xmm2
+
+psubsw %xmm0, %xmm2
+psubsw (%rax), %xmm2
+
+psubusb %xmm0, %xmm2
+psubusb (%rax), %xmm2
+
+psubusw %xmm0, %xmm2
+psubusw (%rax), %xmm2
+
+psubw %xmm0, %xmm2
+psubw (%rax), %xmm2
+
+punpckhbw %xmm0, %xmm2
+punpckhbw (%rax), %xmm2
+
+punpckhdq %xmm0, %xmm2
+punpckhdq (%rax), %xmm2
+
+punpckhqdq %xmm0, %xmm2
+punpckhqdq (%rax), %xmm2
+
+punpckhwd %xmm0, %xmm2
+punpckhwd (%rax), %xmm2
+
+punpcklbw %xmm0, %xmm2
+punpcklbw (%rax), %xmm2
+
+punpckldq %xmm0, %xmm2
+punpckldq (%rax), %xmm2
+
+punpcklqdq %xmm0, %xmm2
+punpcklqdq (%rax), %xmm2
+
+punpcklwd %xmm0, %xmm2
+punpcklwd (%rax), %xmm2
+
+pxor %xmm0, %xmm2
+pxor (%rax), %xmm2
+
+shufpd $1, %xmm0, %xmm2
+shufpd $1, (%rax), %xmm2
+
+sqrtpd %xmm0, %xmm2
+sqrtpd (%rax), %xmm2
+
+sqrtsd %xmm0, %xmm2
+sqrtsd (%rax), %xmm2
+
+subpd %xmm0, %xmm2
+subpd (%rax), %xmm2
+
+subsd %xmm0, %xmm2
+subsd (%rax), %xmm2
+
+ucomisd %xmm0, %xmm1
+ucomisd (%rax), %xmm1
+
+unpckhpd %xmm0, %xmm2
+unpckhpd (%rax), %xmm2
+
+unpcklpd %xmm0, %xmm2
+unpcklpd (%rax), %xmm2
+
+xorpd %xmm0, %xmm2
+xorpd (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addpd %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * addpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addsd %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * addsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 andnpd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * andnpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 andpd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * andpd (%rax), %xmm2
+# CHECK-NEXT: 4 2 0.50 * * U clflush (%rax)
+# CHECK-NEXT: 1 4 0.50 cmpeqpd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cmpeqpd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cmpeqsd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cmpeqsd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 comisd %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * comisd (%rax), %xmm1
+# CHECK-NEXT: 2 5 1.00 cvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 2 5 1.00 cvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 3 12 1.00 * cvtpd2dq (%rax), %xmm2
+# CHECK-NEXT: 2 8 1.00 cvtpd2pi %xmm0, %mm2
+# CHECK-NEXT: 3 24 1.00 * cvtpd2pi (%rax), %mm2
+# CHECK-NEXT: 2 5 1.00 cvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 3 12 1.00 * cvtpd2ps (%rax), %xmm2
+# CHECK-NEXT: 2 6 1.00 cvtpi2pd %mm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtpi2pd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 5 1.00 cvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 cvtsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 7 1.00 cvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 3 26 1.00 * cvtsd2si (%rax), %ecx
+# CHECK-NEXT: 3 12 1.00 * cvtsd2si (%rax), %rcx
+# CHECK-NEXT: 2 5 1.00 cvtsd2ss %xmm0, %xmm2
+# CHECK-NEXT: 3 12 1.00 * cvtsd2ss (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 cvtsi2sd %ecx, %xmm2
+# CHECK-NEXT: 2 7 1.00 cvtsi2sd %rcx, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 2 5 1.00 cvtss2sd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvtss2sd (%rax), %xmm2
+# CHECK-NEXT: 2 5 1.00 cvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 3 12 1.00 * cvttpd2dq (%rax), %xmm2
+# CHECK-NEXT: 2 8 1.00 cvttpd2pi %xmm0, %mm2
+# CHECK-NEXT: 3 24 1.00 * cvttpd2pi (%rax), %mm2
+# CHECK-NEXT: 1 4 0.50 cvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * cvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 cvttsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 7 1.00 cvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 3 26 1.00 * cvttsd2si (%rax), %ecx
+# CHECK-NEXT: 3 12 1.00 * cvttsd2si (%rax), %rcx
+# CHECK-NEXT: 1 14 1.00 divpd %xmm0, %xmm2
+# CHECK-NEXT: 2 20 1.00 * divpd (%rax), %xmm2
+# CHECK-NEXT: 1 14 1.00 divsd %xmm0, %xmm2
+# CHECK-NEXT: 2 20 1.00 * divsd (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 * * U lfence
+# CHECK-NEXT: 2 1 1.00 * * U maskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 1 4 0.50 maxpd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * maxpd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 maxsd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * maxsd (%rax), %xmm2
+# CHECK-NEXT: 2 3 0.50 * * U mfence
+# CHECK-NEXT: 1 4 0.50 minpd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * minpd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 minsd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * minsd (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 movapd %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movapd %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * movapd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 movd %eax, %xmm2
+# CHECK-NEXT: 1 7 0.33 * movd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 movd %xmm0, %ecx
+# CHECK-NEXT: 2 12 0.50 * movd %xmm0, (%rax)
+# CHECK-NEXT: 0 1 0.00 movdqa %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movdqa %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * movdqa (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 movdqu %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movdqu %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * movdqu (%rax), %xmm2
+# CHECK-NEXT: 2 3 0.67 movdq2q %xmm0, %mm2
+# CHECK-NEXT: 2 12 0.50 * movhpd %xmm0, (%rax)
+# CHECK-NEXT: 2 8 1.00 * movhpd (%rax), %xmm2
+# CHECK-NEXT: 2 12 0.50 * movlpd %xmm0, (%rax)
+# CHECK-NEXT: 2 8 0.50 * movlpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 movmskpd %xmm0, %ecx
+# CHECK-NEXT: 2 518 0.50 * movntil %eax, (%rax)
+# CHECK-NEXT: 2 512 0.50 * movntiq %rax, (%rax)
+# CHECK-NEXT: 2 512 0.50 * movntdq %xmm0, (%rax)
+# CHECK-NEXT: 2 518 0.50 * movntpd %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.33 movq %xmm0, %xmm2
+# CHECK-NEXT: 1 3 1.00 movq %rax, %xmm2
+# CHECK-NEXT: 1 7 0.33 * movq (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 movq %xmm0, %rcx
+# CHECK-NEXT: 2 12 0.50 * movq %xmm0, (%rax)
+# CHECK-NEXT: 2 3 1.00 movq2dq %mm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 movsd %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movsd %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * movsd (%rax), %xmm2
+# CHECK-NEXT: 0 1 0.00 movupd %xmm0, %xmm2
+# CHECK-NEXT: 2 12 0.50 * movupd %xmm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * movupd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 mulpd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * mulpd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 mulsd %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * mulsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 orpd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * orpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 packssdw %xmm0, %xmm2
+# CHECK-NEXT: 2 10 1.00 * packssdw (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 packsswb %xmm0, %xmm2
+# CHECK-NEXT: 2 10 1.00 * packsswb (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 packuswb %xmm0, %xmm2
+# CHECK-NEXT: 2 10 1.00 * packuswb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 paddb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * paddb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 paddd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * paddd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddq %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * paddq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.33 paddq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * paddq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddsb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * paddsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddsw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * paddsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddusb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * paddusb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 paddusw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * paddusw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 paddw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * paddw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 pand %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * pand (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 pandn %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * pandn (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pavgb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pavgb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pavgw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pavgw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpeqb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pcmpeqb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpeqd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pcmpeqd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpeqw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pcmpeqw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpgtb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pcmpgtb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpgtd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pcmpgtd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpgtw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pcmpgtw (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 pextrw $1, %xmm0, %ecx
+# CHECK-NEXT: 2 4 1.00 pinsrw $1, %eax, %xmm0
+# CHECK-NEXT: 2 8 0.50 * pinsrw $1, (%rax), %xmm0
+# CHECK-NEXT: 1 5 0.50 pmaddwd %xmm0, %xmm2
+# CHECK-NEXT: 2 13 0.50 * pmaddwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmaxsw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmaxsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmaxub %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmaxub (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pminsw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pminsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pminub %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pminub (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 pmovmskb %xmm0, %ecx
+# CHECK-NEXT: 1 5 0.50 pmulhuw %xmm0, %xmm2
+# CHECK-NEXT: 2 13 0.50 * pmulhuw (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 pmulhw %xmm0, %xmm2
+# CHECK-NEXT: 2 13 0.50 * pmulhw (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 pmullw %xmm0, %xmm2
+# CHECK-NEXT: 2 13 0.50 * pmullw (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.00 pmuludq %mm0, %mm2
+# CHECK-NEXT: 2 13 1.00 * pmuludq (%rax), %mm2
+# CHECK-NEXT: 1 5 0.50 pmuludq %xmm0, %xmm2
+# CHECK-NEXT: 2 13 0.50 * pmuludq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 por %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * por (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 psadbw %xmm0, %xmm2
+# CHECK-NEXT: 2 10 1.00 * psadbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pshufd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pslld $1, %xmm2
+# CHECK-NEXT: 2 2 0.67 pslld %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pslld (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pslldq $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psllq $1, %xmm2
+# CHECK-NEXT: 2 2 0.67 psllq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psllq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psllw $1, %xmm2
+# CHECK-NEXT: 2 2 0.67 psllw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psllw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrad $1, %xmm2
+# CHECK-NEXT: 2 2 0.67 psrad %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psrad (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psraw $1, %xmm2
+# CHECK-NEXT: 2 2 0.67 psraw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psraw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrld $1, %xmm2
+# CHECK-NEXT: 2 2 0.67 psrld %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psrld (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrldq $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psrlq $1, %xmm2
+# CHECK-NEXT: 2 2 0.67 psrlq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psrlq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrlw $1, %xmm2
+# CHECK-NEXT: 2 2 0.67 psrlw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psrlw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 psubb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * psubb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 psubd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * psubd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubq %mm0, %mm2
+# CHECK-NEXT: 2 9 0.50 * psubq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.33 psubq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * psubq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubsb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psubsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubsw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psubsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubusb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psubusb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psubusw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psubusw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 psubw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * psubw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhbw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpckhbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpckhdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhqdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpckhqdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhwd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpckhwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklbw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpcklbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckldq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpckldq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklqdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpcklqdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklwd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * punpcklwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 pxor %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * pxor (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 shufpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * shufpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 18 1.00 sqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 2 24 1.00 * sqrtpd (%rax), %xmm2
+# CHECK-NEXT: 1 18 1.00 sqrtsd %xmm0, %xmm2
+# CHECK-NEXT: 2 24 1.00 * sqrtsd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subpd %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * subpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subsd %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * subsd (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 ucomisd %xmm0, %xmm1
+# CHECK-NEXT: 2 8 1.00 * ucomisd (%rax), %xmm1
+# CHECK-NEXT: 1 1 1.00 unpckhpd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 1.00 * unpckhpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 unpcklpd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 1.00 * unpcklpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 xorpd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * xorpd (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 107.70 99.20 39.33 39.33 8.50 71.70 1.20 7.83 7.50 7.50 0.20 39.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - addpd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - addpd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - addsd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - addsd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - andnpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - andnpd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - andpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - andpd (%rax), %xmm2
+# CHECK-NEXT: 0.70 0.20 - - 0.50 0.20 0.70 0.50 0.50 0.50 0.20 - - clflush (%rax)
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cmpeqpd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cmpeqpd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cmpeqsd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cmpeqsd (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - comisd %xmm0, %xmm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - comisd (%rax), %xmm1
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - cvtpd2dq (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvtpd2pi %xmm0, %mm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - cvtpd2pi (%rax), %mm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - cvtpd2ps (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvtpi2pd %mm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtpi2pd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - cvtsd2si %xmm0, %ecx
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - cvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtsd2si (%rax), %ecx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtsd2si (%rax), %rcx
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvtsd2ss %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - cvtsd2ss (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvtsi2sd %ecx, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvtsi2sd %rcx, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvtss2sd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvtss2sd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - cvttpd2dq (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - 1.00 - - - - - - - cvttpd2pi %xmm0, %mm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - 1.00 - - - - - 0.33 - cvttpd2pi (%rax), %mm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - cvttsd2si %xmm0, %ecx
+# CHECK-NEXT: 1.50 0.50 - - - - - - - - - - - cvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvttsd2si (%rax), %ecx
+# CHECK-NEXT: 1.50 0.50 0.33 0.33 - - - - - - - 0.33 - cvttsd2si (%rax), %rcx
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - divpd %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - divpd (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - divsd %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - divsd (%rax), %xmm2
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - lfence
+# CHECK-NEXT: - - 0.33 0.33 1.00 - - 0.33 - - - - - maskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - maxpd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - maxpd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - maxsd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - maxsd (%rax), %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - mfence
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - minpd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - minpd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - minsd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - minsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - movapd %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movapd %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movapd (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - movd %eax, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movd (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - movd %xmm0, %ecx
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - movdqa %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movdqa %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - movdqu %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movdqu %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movdqu (%rax), %xmm2
+# CHECK-NEXT: 0.83 0.33 - - - 0.83 - - - - - - - movdq2q %xmm0, %mm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movhpd %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - movhpd (%rax), %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movlpd %xmm0, (%rax)
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - movlpd (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - movmskpd %xmm0, %ecx
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movntil %eax, (%rax)
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movntiq %rax, (%rax)
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movntdq %xmm0, (%rax)
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movntpd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - movq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - movq %rax, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movq (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - movq %xmm0, %rcx
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movq %xmm0, (%rax)
+# CHECK-NEXT: 1.33 0.33 - - - 0.33 - - - - - - - movq2dq %mm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - movsd %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movsd %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - movupd %xmm0, %xmm2
+# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movupd %xmm0, (%rax)
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movupd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mulpd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - mulpd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mulsd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - mulsd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - orpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - orpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - packssdw %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - packssdw (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - packsswb %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - packsswb (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - packuswb %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - packuswb (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - paddb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - paddb (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - paddd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - paddd (%rax), %xmm2
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - paddq %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 0.50 - - - - - 0.33 - paddq (%rax), %mm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - paddq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - paddq (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - paddsb %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - paddsb (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - paddsw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - paddsw (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - paddusb %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - paddusb (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - paddusw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - paddusw (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - paddw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - paddw (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - pand %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - pand (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - pandn %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - pandn (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pavgb %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pavgb (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pavgw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pavgw (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pcmpeqb %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pcmpeqb (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pcmpeqd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pcmpeqd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pcmpeqw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pcmpeqw (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pcmpgtb %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pcmpgtb (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pcmpgtd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pcmpgtd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pcmpgtw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pcmpgtw (%rax), %xmm2
+# CHECK-NEXT: 1.00 0.50 - - - 0.50 - - - - - - - pextrw $1, %xmm0, %ecx
+# CHECK-NEXT: - 0.50 - - - 1.50 - - - - - - - pinsrw $1, %eax, %xmm0
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pinsrw $1, (%rax), %xmm0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmaddwd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmaddwd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmaxsw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmaxsw (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmaxub %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmaxub (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pminsw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pminsw (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pminub %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pminub (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pmovmskb %xmm0, %ecx
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmulhuw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmulhuw (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmulhw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmulhw (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmullw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmullw (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pmuludq %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pmuludq (%rax), %mm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmuludq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmuludq (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - por %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - por (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - psadbw %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - psadbw (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pshufd $1, (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pslld $1, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - pslld %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pslld (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pslldq $1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psllq $1, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - psllq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psllq (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psllw $1, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - psllw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psllw (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psrad $1, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - psrad %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psrad (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psraw $1, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - psraw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psraw (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psrld $1, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - psrld %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psrld (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - psrldq $1, %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psrlq $1, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - psrlq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psrlq (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psrlw $1, %xmm2
+# CHECK-NEXT: 0.50 1.00 - - - 0.50 - - - - - - - psrlw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psrlw (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - psubb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - psubb (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - psubd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - psubd (%rax), %xmm2
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - psubq %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 0.50 - - - - - 0.33 - psubq (%rax), %mm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - psubq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - psubq (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psubsb %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psubsb (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psubsw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psubsw (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psubusb %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psubusb (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psubusw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psubusw (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - psubw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - psubw (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - punpckhbw %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - punpckhbw (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - punpckhdq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - punpckhdq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - punpckhqdq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - punpckhqdq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - punpckhwd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - punpckhwd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - punpcklbw %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - punpcklbw (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - punpckldq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - punpckldq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - punpcklqdq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - punpcklqdq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - punpcklwd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - punpcklwd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - pxor %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - pxor (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - shufpd $1, %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - shufpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - sqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - sqrtpd (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - sqrtsd %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - sqrtsd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - subpd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - subpd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - subsd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - subsd (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - ucomisd %xmm0, %xmm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - ucomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - unpckhpd %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - unpckhpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - unpcklpd %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - unpcklpd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - xorpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - xorpd (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s
new file mode 100644
index 0000000000000..15baea9604c74
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s
@@ -0,0 +1,109 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+addsubpd %xmm0, %xmm2
+addsubpd (%rax), %xmm2
+
+addsubps %xmm0, %xmm2
+addsubps (%rax), %xmm2
+
+haddpd %xmm0, %xmm2
+haddpd (%rax), %xmm2
+
+haddps %xmm0, %xmm2
+haddps (%rax), %xmm2
+
+hsubpd %xmm0, %xmm2
+hsubpd (%rax), %xmm2
+
+hsubps %xmm0, %xmm2
+hsubps (%rax), %xmm2
+
+lddqu (%rax), %xmm2
+
+monitor
+
+movddup %xmm0, %xmm2
+movddup (%rax), %xmm2
+
+movshdup %xmm0, %xmm2
+movshdup (%rax), %xmm2
+
+movsldup %xmm0, %xmm2
+movsldup (%rax), %xmm2
+
+mwait
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addsubpd %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * addsubpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addsubps %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * addsubps (%rax), %xmm2
+# CHECK-NEXT: 3 6 2.00 haddpd %xmm0, %xmm2
+# CHECK-NEXT: 4 12 2.00 * haddpd (%rax), %xmm2
+# CHECK-NEXT: 3 6 2.00 haddps %xmm0, %xmm2
+# CHECK-NEXT: 4 12 2.00 * haddps (%rax), %xmm2
+# CHECK-NEXT: 3 6 2.00 hsubpd %xmm0, %xmm2
+# CHECK-NEXT: 4 12 2.00 * hsubpd (%rax), %xmm2
+# CHECK-NEXT: 3 6 2.00 hsubps %xmm0, %xmm2
+# CHECK-NEXT: 4 12 2.00 * hsubps (%rax), %xmm2
+# CHECK-NEXT: 1 7 0.33 * lddqu (%rax), %xmm2
+# CHECK-NEXT: 1 100 0.25 U monitor
+# CHECK-NEXT: 1 1 1.00 movddup %xmm0, %xmm2
+# CHECK-NEXT: 1 7 0.33 * movddup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movshdup %xmm0, %xmm2
+# CHECK-NEXT: 1 7 0.33 * movshdup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movsldup %xmm0, %xmm2
+# CHECK-NEXT: 1 7 0.33 * movsldup (%rax), %xmm2
+# CHECK-NEXT: 10 20 2.50 * * U mwait
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 2.00 9.00 3.33 3.33 - 27.00 4.00 - - - - 3.33 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - addsubpd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - addsubpd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - addsubps %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - addsubps (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 2.50 - - - - - - - haddpd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 2.50 - - - - - 0.33 - haddpd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 2.50 - - - - - - - haddps %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 2.50 - - - - - 0.33 - haddps (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 2.50 - - - - - - - hsubpd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 2.50 - - - - - 0.33 - hsubpd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 2.50 - - - - - - - hsubps %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 2.50 - - - - - 0.33 - hsubps (%rax), %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - lddqu (%rax), %xmm2
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - monitor
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - movddup %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movddup (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - movshdup %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movshdup (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - movsldup %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movsldup (%rax), %xmm2
+# CHECK-NEXT: 1.75 1.75 - - - 2.75 3.75 - - - - - - mwait
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s
new file mode 100644
index 0000000000000..ffe9150cc5916
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s
@@ -0,0 +1,371 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+blendpd $11, %xmm0, %xmm2
+blendpd $11, (%rax), %xmm2
+
+blendps $11, %xmm0, %xmm2
+blendps $11, (%rax), %xmm2
+
+blendvpd %xmm0, %xmm2
+blendvpd (%rax), %xmm2
+
+blendvps %xmm0, %xmm2
+blendvps (%rax), %xmm2
+
+dppd $22, %xmm0, %xmm2
+dppd $22, (%rax), %xmm2
+
+dpps $22, %xmm0, %xmm2
+dpps $22, (%rax), %xmm2
+
+extractps $1, %xmm0, %rcx
+extractps $1, %xmm0, (%rax)
+
+insertps $1, %xmm0, %xmm2
+insertps $1, (%rax), %xmm2
+
+movntdqa (%rax), %xmm2
+
+mpsadbw $1, %xmm0, %xmm2
+mpsadbw $1, (%rax), %xmm2
+
+packusdw %xmm0, %xmm2
+packusdw (%rax), %xmm2
+
+pblendvb %xmm0, %xmm2
+pblendvb (%rax), %xmm2
+
+pblendw $11, %xmm0, %xmm2
+pblendw $11, (%rax), %xmm2
+
+pcmpeqq %xmm0, %xmm2
+pcmpeqq (%rax), %xmm2
+
+pextrb $1, %xmm0, %ecx
+pextrb $1, %xmm0, (%rax)
+
+pextrd $1, %xmm0, %ecx
+pextrd $1, %xmm0, (%rax)
+
+pextrq $1, %xmm0, %rcx
+pextrq $1, %xmm0, (%rax)
+
+pextrw $1, %xmm0, (%rax)
+
+phminposuw %xmm0, %xmm2
+phminposuw (%rax), %xmm2
+
+pinsrb $1, %eax, %xmm1
+pinsrb $1, (%rax), %xmm1
+
+pinsrd $1, %eax, %xmm1
+pinsrd $1, (%rax), %xmm1
+
+pinsrq $1, %rax, %xmm1
+pinsrq $1, (%rax), %xmm1
+
+pmaxsb %xmm0, %xmm2
+pmaxsb (%rax), %xmm2
+
+pmaxsd %xmm0, %xmm2
+pmaxsd (%rax), %xmm2
+
+pmaxud %xmm0, %xmm2
+pmaxud (%rax), %xmm2
+
+pmaxuw %xmm0, %xmm2
+pmaxuw (%rax), %xmm2
+
+pminsb %xmm0, %xmm2
+pminsb (%rax), %xmm2
+
+pminsd %xmm0, %xmm2
+pminsd (%rax), %xmm2
+
+pminud %xmm0, %xmm2
+pminud (%rax), %xmm2
+
+pminuw %xmm0, %xmm2
+pminuw (%rax), %xmm2
+
+pmovsxbd %xmm0, %xmm2
+pmovsxbd (%rax), %xmm2
+
+pmovsxbq %xmm0, %xmm2
+pmovsxbq (%rax), %xmm2
+
+pmovsxbw %xmm0, %xmm2
+pmovsxbw (%rax), %xmm2
+
+pmovsxdq %xmm0, %xmm2
+pmovsxdq (%rax), %xmm2
+
+pmovsxwd %xmm0, %xmm2
+pmovsxwd (%rax), %xmm2
+
+pmovsxwq %xmm0, %xmm2
+pmovsxwq (%rax), %xmm2
+
+pmovzxbd %xmm0, %xmm2
+pmovzxbd (%rax), %xmm2
+
+pmovzxbq %xmm0, %xmm2
+pmovzxbq (%rax), %xmm2
+
+pmovzxbw %xmm0, %xmm2
+pmovzxbw (%rax), %xmm2
+
+pmovzxdq %xmm0, %xmm2
+pmovzxdq (%rax), %xmm2
+
+pmovzxwd %xmm0, %xmm2
+pmovzxwd (%rax), %xmm2
+
+pmovzxwq %xmm0, %xmm2
+pmovzxwq (%rax), %xmm2
+
+pmuldq %xmm0, %xmm2
+pmuldq (%rax), %xmm2
+
+pmulld %xmm0, %xmm2
+pmulld (%rax), %xmm2
+
+ptest %xmm0, %xmm1
+ptest (%rax), %xmm1
+
+roundpd $1, %xmm0, %xmm2
+roundpd $1, (%rax), %xmm2
+
+roundps $1, %xmm0, %xmm2
+roundps $1, (%rax), %xmm2
+
+roundsd $1, %xmm0, %xmm2
+roundsd $1, (%rax), %xmm2
+
+roundss $1, %xmm0, %xmm2
+roundss $1, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.33 blendpd $11, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * blendpd $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 blendps $11, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * blendps $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 blendvpd %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * blendvpd %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * blendvps %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 3 9 1.00 dppd $22, %xmm0, %xmm2
+# CHECK-NEXT: 4 16 1.00 * dppd $22, (%rax), %xmm2
+# CHECK-NEXT: 6 14 1.67 dpps $22, %xmm0, %xmm2
+# CHECK-NEXT: 7 21 1.67 * dpps $22, (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 extractps $1, %xmm0, %ecx
+# CHECK-NEXT: 3 12 1.00 * extractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 1 1.00 insertps $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 1.00 * insertps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 7 0.33 * movntdqa (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 mpsadbw $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 11 1.00 * mpsadbw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 packusdw %xmm0, %xmm2
+# CHECK-NEXT: 2 10 1.00 * packusdw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 pblendvb %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * pblendvb %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pblendw $11, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pblendw $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpeqq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pcmpeqq (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 pextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 3 19 0.50 * pextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 4 1.00 pextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 3 12 0.50 * pextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 4 1.00 pextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 3 12 0.50 * pextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 19 0.50 * pextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 4 1.00 phminposuw %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * phminposuw (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 pinsrb $1, %eax, %xmm1
+# CHECK-NEXT: 2 8 0.50 * pinsrb $1, (%rax), %xmm1
+# CHECK-NEXT: 2 4 1.00 pinsrd $1, %eax, %xmm1
+# CHECK-NEXT: 2 8 0.50 * pinsrd $1, (%rax), %xmm1
+# CHECK-NEXT: 2 4 1.00 pinsrq $1, %rax, %xmm1
+# CHECK-NEXT: 2 8 0.50 * pinsrq $1, (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 pmaxsb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmaxsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmaxsd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmaxsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmaxud %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmaxud (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmaxuw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmaxuw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pminsb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pminsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pminsd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pminsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pminud %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pminud (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pminuw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pminuw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovsxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovsxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovsxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovsxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovsxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovsxwq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovzxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovzxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovzxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovzxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovzxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 pmuldq %xmm0, %xmm2
+# CHECK-NEXT: 2 13 0.50 * pmuldq (%rax), %xmm2
+# CHECK-NEXT: 2 10 1.00 pmulld %xmm0, %xmm2
+# CHECK-NEXT: 3 18 1.00 * pmulld (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 ptest %xmm0, %xmm1
+# CHECK-NEXT: 3 9 1.00 * ptest (%rax), %xmm1
+# CHECK-NEXT: 2 8 1.00 roundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 15 1.00 * roundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 2 8 1.00 roundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 15 1.00 * roundps $1, (%rax), %xmm2
+# CHECK-NEXT: 2 8 1.00 roundsd $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 15 1.00 * roundsd $1, (%rax), %xmm2
+# CHECK-NEXT: 2 8 1.00 roundss $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 15 1.00 * roundss $1, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 36.33 50.83 14.67 14.67 2.50 41.83 1.00 2.50 2.50 2.50 - 14.67 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - blendpd $11, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - blendpd $11, (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - blendps $11, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - blendps $11, (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - blendvpd %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - blendvpd %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - blendvps %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 1.00 1.50 - - - 0.50 - - - - - - - dppd $22, %xmm0, %xmm2
+# CHECK-NEXT: 1.00 1.50 0.33 0.33 - 0.50 - - - - - 0.33 - dppd $22, (%rax), %xmm2
+# CHECK-NEXT: 1.50 2.00 - - - 2.00 0.50 - - - - - - dpps $22, %xmm0, %xmm2
+# CHECK-NEXT: 1.50 2.00 0.33 0.33 - 2.00 0.50 - - - - 0.33 - dpps $22, (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - extractps $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - 0.50 1.00 - 0.50 0.50 0.50 - - - extractps $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - insertps $1, %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - insertps $1, (%rax), %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movntdqa (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 1.50 - - - - - - - mpsadbw $1, %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 1.50 - - - - - 0.33 - mpsadbw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - packusdw %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - packusdw (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - pblendvb %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 - 0.33 - - - - - 0.33 - pblendvb %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pblendw $11, %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pblendw $11, (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pcmpeqq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pcmpeqq (%rax), %xmm2
+# CHECK-NEXT: 1.00 0.50 - - - 0.50 - - - - - - - pextrb $1, %xmm0, %ecx
+# CHECK-NEXT: - 0.50 - - 0.50 0.50 - 0.50 0.50 0.50 - - - pextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 1.00 0.50 - - - 0.50 - - - - - - - pextrd $1, %xmm0, %ecx
+# CHECK-NEXT: - 0.50 - - 0.50 0.50 - 0.50 0.50 0.50 - - - pextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 1.00 0.50 - - - 0.50 - - - - - - - pextrq $1, %xmm0, %rcx
+# CHECK-NEXT: - 0.50 - - 0.50 0.50 - 0.50 0.50 0.50 - - - pextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: - 0.50 - - 0.50 0.50 - 0.50 0.50 0.50 - - - pextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - phminposuw %xmm0, %xmm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - phminposuw (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 1.50 - - - - - - - pinsrb $1, %eax, %xmm1
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pinsrb $1, (%rax), %xmm1
+# CHECK-NEXT: - 0.50 - - - 1.50 - - - - - - - pinsrd $1, %eax, %xmm1
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pinsrd $1, (%rax), %xmm1
+# CHECK-NEXT: - 0.50 - - - 1.50 - - - - - - - pinsrq $1, %rax, %xmm1
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pinsrq $1, (%rax), %xmm1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmaxsb %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmaxsb (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmaxsd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmaxsd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmaxud %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmaxud (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmaxuw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmaxuw (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pminsb %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pminsb (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pminsd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pminsd (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pminud %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pminud (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pminuw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pminuw (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pmovsxbd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pmovsxbq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pmovsxbw (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pmovsxdq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pmovsxwd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pmovsxwq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pmovzxbd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pmovzxbq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pmovzxbw (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pmovzxdq (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pmovzxwd (%rax), %xmm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmuldq %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmuldq (%rax), %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - pmulld %xmm0, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - pmulld (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - ptest %xmm0, %xmm1
+# CHECK-NEXT: 1.00 - 0.33 0.33 - 1.00 - - - - - 0.33 - ptest (%rax), %xmm1
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - roundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - roundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - roundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - roundps $1, (%rax), %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - roundsd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - roundsd $1, (%rax), %xmm2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - roundss $1, %xmm0, %xmm2
+# CHECK-NEXT: 1.00 1.00 0.33 0.33 - - - - - - - 0.33 - roundss $1, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s
new file mode 100644
index 0000000000000..cb5b34e9b6468
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s
@@ -0,0 +1,104 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+crc32b %al, %ecx
+crc32b (%rax), %ecx
+
+crc32l %eax, %ecx
+crc32l (%rax), %ecx
+
+crc32w %ax, %ecx
+crc32w (%rax), %ecx
+
+crc32b %al, %rcx
+crc32b (%rax), %rcx
+
+crc32q %rax, %rcx
+crc32q (%rax), %rcx
+
+pcmpestri $1, %xmm0, %xmm2
+pcmpestri $1, (%rax), %xmm2
+
+pcmpestrm $1, %xmm0, %xmm2
+pcmpestrm $1, (%rax), %xmm2
+
+pcmpistri $1, %xmm0, %xmm2
+pcmpistri $1, (%rax), %xmm2
+
+pcmpistrm $1, %xmm0, %xmm2
+pcmpistrm $1, (%rax), %xmm2
+
+pcmpgtq %xmm0, %xmm2
+pcmpgtq (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 crc32b %al, %ecx
+# CHECK-NEXT: 2 8 1.00 * crc32b (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 crc32l %eax, %ecx
+# CHECK-NEXT: 2 8 1.00 * crc32l (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 crc32w %ax, %ecx
+# CHECK-NEXT: 2 8 1.00 * crc32w (%rax), %ecx
+# CHECK-NEXT: 1 3 1.00 crc32b %al, %rcx
+# CHECK-NEXT: 2 8 1.00 * crc32b (%rax), %rcx
+# CHECK-NEXT: 1 3 1.00 crc32q %rax, %rcx
+# CHECK-NEXT: 2 8 1.00 * crc32q (%rax), %rcx
+# CHECK-NEXT: 8 16 3.00 pcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 31 3.00 * pcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: 9 16 3.00 pcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 9 17 3.00 * pcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: 3 11 3.00 pcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 4 31 3.00 * pcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: 3 11 3.00 pcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 4 16 3.00 * pcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 pcmpgtq %xmm0, %xmm2
+# CHECK-NEXT: 2 10 1.00 * pcmpgtq (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 28.67 16.67 3.33 3.33 - 8.67 2.00 - - - - 3.33 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - crc32b %al, %ecx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - crc32b (%rax), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - crc32l %eax, %ecx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - crc32l (%rax), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - crc32w %ax, %ecx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - crc32w (%rax), %ecx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - crc32b %al, %rcx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - crc32b (%rax), %rcx
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - crc32q %rax, %rcx
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - crc32q (%rax), %rcx
+# CHECK-NEXT: 4.17 1.67 - - - 1.67 0.50 - - - - - - pcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 3.83 1.33 0.33 0.33 - 1.33 0.50 - - - - 0.33 - pcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: 4.50 2.00 - - - 2.00 0.50 - - - - - - pcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 4.17 1.67 0.33 0.33 - 1.67 0.50 - - - - 0.33 - pcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: 3.00 - - - - - - - - - - - - pcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 3.00 - 0.33 0.33 - - - - - - - 0.33 - pcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: 3.00 - - - - - - - - - - - - pcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 3.00 - 0.33 0.33 - - - - - - - 0.33 - pcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - pcmpgtq %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - pcmpgtq (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s
new file mode 100644
index 0000000000000..33ec9b0fa64d2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s
@@ -0,0 +1,258 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+pabsb %mm0, %mm2
+pabsb (%rax), %mm2
+
+pabsb %xmm0, %xmm2
+pabsb (%rax), %xmm2
+
+pabsd %mm0, %mm2
+pabsd (%rax), %mm2
+
+pabsd %xmm0, %xmm2
+pabsd (%rax), %xmm2
+
+pabsw %mm0, %mm2
+pabsw (%rax), %mm2
+
+pabsw %xmm0, %xmm2
+pabsw (%rax), %xmm2
+
+palignr $1, %mm0, %mm2
+palignr $1, (%rax), %mm2
+
+palignr $1, %xmm0, %xmm2
+palignr $1, (%rax), %xmm2
+
+phaddd %mm0, %mm2
+phaddd (%rax), %mm2
+
+phaddd %xmm0, %xmm2
+phaddd (%rax), %xmm2
+
+phaddsw %mm0, %mm2
+phaddsw (%rax), %mm2
+
+phaddsw %xmm0, %xmm2
+phaddsw (%rax), %xmm2
+
+phaddw %mm0, %mm2
+phaddw (%rax), %mm2
+
+phaddw %xmm0, %xmm2
+phaddw (%rax), %xmm2
+
+phsubd %mm0, %mm2
+phsubd (%rax), %mm2
+
+phsubd %xmm0, %xmm2
+phsubd (%rax), %xmm2
+
+phsubsw %mm0, %mm2
+phsubsw (%rax), %mm2
+
+phsubsw %xmm0, %xmm2
+phsubsw (%rax), %xmm2
+
+phsubw %mm0, %mm2
+phsubw (%rax), %mm2
+
+phsubw %xmm0, %xmm2
+phsubw (%rax), %xmm2
+
+pmaddubsw %mm0, %mm2
+pmaddubsw (%rax), %mm2
+
+pmaddubsw %xmm0, %xmm2
+pmaddubsw (%rax), %xmm2
+
+pmulhrsw %mm0, %mm2
+pmulhrsw (%rax), %mm2
+
+pmulhrsw %xmm0, %xmm2
+pmulhrsw (%rax), %xmm2
+
+pshufb %mm0, %mm2
+pshufb (%rax), %mm2
+
+pshufb %xmm0, %xmm2
+pshufb (%rax), %xmm2
+
+psignb %mm0, %mm2
+psignb (%rax), %mm2
+
+psignb %xmm0, %xmm2
+psignb (%rax), %xmm2
+
+psignd %mm0, %mm2
+psignd (%rax), %mm2
+
+psignd %xmm0, %xmm2
+psignd (%rax), %xmm2
+
+psignw %mm0, %mm2
+psignw (%rax), %mm2
+
+psignw %xmm0, %xmm2
+psignw (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 pabsb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pabsb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pabsb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pabsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 pabsd %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pabsd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pabsd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pabsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 pabsw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * pabsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pabsw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pabsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 palignr $1, %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * palignr $1, (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 palignr $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 1.00 * palignr $1, (%rax), %xmm2
+# CHECK-NEXT: 3 3 2.00 phaddd %mm0, %mm2
+# CHECK-NEXT: 4 11 2.00 * phaddd (%rax), %mm2
+# CHECK-NEXT: 3 2 1.00 phaddd %xmm0, %xmm2
+# CHECK-NEXT: 4 9 1.00 * phaddd (%rax), %xmm2
+# CHECK-NEXT: 3 3 2.00 phaddsw %mm0, %mm2
+# CHECK-NEXT: 4 11 2.00 * phaddsw (%rax), %mm2
+# CHECK-NEXT: 3 2 1.00 phaddsw %xmm0, %xmm2
+# CHECK-NEXT: 4 9 1.00 * phaddsw (%rax), %xmm2
+# CHECK-NEXT: 3 3 2.00 phaddw %mm0, %mm2
+# CHECK-NEXT: 4 11 2.00 * phaddw (%rax), %mm2
+# CHECK-NEXT: 3 2 1.00 phaddw %xmm0, %xmm2
+# CHECK-NEXT: 4 9 1.00 * phaddw (%rax), %xmm2
+# CHECK-NEXT: 3 3 2.00 phsubd %mm0, %mm2
+# CHECK-NEXT: 4 11 2.00 * phsubd (%rax), %mm2
+# CHECK-NEXT: 3 2 1.00 phsubd %xmm0, %xmm2
+# CHECK-NEXT: 4 9 1.00 * phsubd (%rax), %xmm2
+# CHECK-NEXT: 3 3 2.00 phsubsw %mm0, %mm2
+# CHECK-NEXT: 4 11 2.00 * phsubsw (%rax), %mm2
+# CHECK-NEXT: 3 2 1.00 phsubsw %xmm0, %xmm2
+# CHECK-NEXT: 4 9 1.00 * phsubsw (%rax), %xmm2
+# CHECK-NEXT: 3 3 2.00 phsubw %mm0, %mm2
+# CHECK-NEXT: 4 11 2.00 * phsubw (%rax), %mm2
+# CHECK-NEXT: 3 2 1.00 phsubw %xmm0, %xmm2
+# CHECK-NEXT: 4 9 1.00 * phsubw (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.00 pmaddubsw %mm0, %mm2
+# CHECK-NEXT: 2 13 1.00 * pmaddubsw (%rax), %mm2
+# CHECK-NEXT: 1 5 0.50 pmaddubsw %xmm0, %xmm2
+# CHECK-NEXT: 2 13 0.50 * pmaddubsw (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.00 pmulhrsw %mm0, %mm2
+# CHECK-NEXT: 2 13 1.00 * pmulhrsw (%rax), %mm2
+# CHECK-NEXT: 1 5 0.50 pmulhrsw %xmm0, %xmm2
+# CHECK-NEXT: 2 13 0.50 * pmulhrsw (%rax), %xmm2
+# CHECK-NEXT: 2 3 1.00 pshufb %mm0, %mm2
+# CHECK-NEXT: 3 11 1.00 * pshufb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pshufb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * pshufb (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 psignb %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psignb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psignb %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psignb (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 psignd %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psignd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psignd %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psignd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 psignw %mm0, %mm2
+# CHECK-NEXT: 2 9 1.00 * psignw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psignw %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * psignw (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 38.67 25.67 10.67 10.67 - 49.67 - - - - - 10.67 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pabsb %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pabsb (%rax), %mm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pabsb %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pabsb (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pabsd %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pabsd (%rax), %mm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pabsd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pabsd (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pabsw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pabsw (%rax), %mm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pabsw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pabsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - palignr $1, %mm0, %mm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - palignr $1, (%rax), %mm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - palignr $1, %xmm0, %xmm2
+# CHECK-NEXT: - - 0.33 0.33 - 1.00 - - - - - 0.33 - palignr $1, (%rax), %xmm2
+# CHECK-NEXT: 0.50 - - - - 2.50 - - - - - - - phaddd %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 2.50 - - - - - 0.33 - phaddd (%rax), %mm2
+# CHECK-NEXT: 0.33 1.33 - - - 1.33 - - - - - - - phaddd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 1.33 0.33 0.33 - 1.33 - - - - - 0.33 - phaddd (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - 2.00 - - - - - - - phaddsw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - 2.00 - - - - - 0.33 - phaddsw (%rax), %mm2
+# CHECK-NEXT: 0.50 1.50 - - - 1.00 - - - - - - - phaddsw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 1.50 0.33 0.33 - 1.00 - - - - - 0.33 - phaddsw (%rax), %xmm2
+# CHECK-NEXT: 0.50 - - - - 2.50 - - - - - - - phaddw %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 2.50 - - - - - 0.33 - phaddw (%rax), %mm2
+# CHECK-NEXT: 0.33 1.33 - - - 1.33 - - - - - - - phaddw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 1.33 0.33 0.33 - 1.33 - - - - - 0.33 - phaddw (%rax), %xmm2
+# CHECK-NEXT: 0.50 - - - - 2.50 - - - - - - - phsubd %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 2.50 - - - - - 0.33 - phsubd (%rax), %mm2
+# CHECK-NEXT: 0.33 1.33 - - - 1.33 - - - - - - - phsubd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 1.33 0.33 0.33 - 1.33 - - - - - 0.33 - phsubd (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - 2.00 - - - - - - - phsubsw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - 2.00 - - - - - 0.33 - phsubsw (%rax), %mm2
+# CHECK-NEXT: 0.50 1.50 - - - 1.00 - - - - - - - phsubsw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 1.50 0.33 0.33 - 1.00 - - - - - 0.33 - phsubsw (%rax), %xmm2
+# CHECK-NEXT: 0.50 - - - - 2.50 - - - - - - - phsubw %mm0, %mm2
+# CHECK-NEXT: 0.50 - 0.33 0.33 - 2.50 - - - - - 0.33 - phsubw (%rax), %mm2
+# CHECK-NEXT: 0.33 1.33 - - - 1.33 - - - - - - - phsubw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 1.33 0.33 0.33 - 1.33 - - - - - 0.33 - phsubw (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pmaddubsw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pmaddubsw (%rax), %mm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmaddubsw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmaddubsw (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pmulhrsw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - pmulhrsw (%rax), %mm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pmulhrsw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - pmulhrsw (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - pshufb %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - 1.00 - - - - - 0.33 - pshufb (%rax), %mm2
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - pshufb %xmm0, %xmm2
+# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - pshufb (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psignb %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psignb (%rax), %mm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psignb %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psignb (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psignd %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psignd (%rax), %mm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psignd %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psignd (%rax), %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psignw %mm0, %mm2
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - psignw (%rax), %mm2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - psignw %xmm0, %xmm2
+# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - psignw (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_32.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_32.s
new file mode 100644
index 0000000000000..559ae7e957a29
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_32.s
@@ -0,0 +1,83 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+aaa
+
+aad
+aad $7
+
+aam
+aam $7
+
+aas
+
+bound %bx, (%eax)
+bound %ebx, (%eax)
+
+daa
+
+das
+
+into
+
+leave
+
+salc
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 aaa
+# CHECK-NEXT: 1 100 0.25 aad
+# CHECK-NEXT: 1 100 0.25 aad $7
+# CHECK-NEXT: 1 100 0.25 aam
+# CHECK-NEXT: 1 100 0.25 aam $7
+# CHECK-NEXT: 1 100 0.25 aas
+# CHECK-NEXT: 1 100 0.25 U bound %bx, (%eax)
+# CHECK-NEXT: 1 100 0.25 U bound %ebx, (%eax)
+# CHECK-NEXT: 1 100 0.25 daa
+# CHECK-NEXT: 1 100 0.25 das
+# CHECK-NEXT: 1 100 0.25 U into
+# CHECK-NEXT: 4 6 0.60 * leave
+# CHECK-NEXT: 1 1 0.25 U salc
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 3.60 3.60 0.33 0.33 - 3.60 3.60 - - - 0.60 0.33 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - aaa
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - aad
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - aad $7
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - aam
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - aam $7
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - aas
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - bound %bx, (%eax)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - bound %ebx, (%eax)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - daa
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - das
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - into
+# CHECK-NEXT: 0.60 0.60 0.33 0.33 - 0.60 0.60 - - - 0.60 0.33 - leave
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - salc
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
new file mode 100644
index 0000000000000..6640968ecd14c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
@@ -0,0 +1,2874 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+adcb $0, %al
+adcb $0, %dil
+adcb $0, (%rax)
+lock adcb $0, (%rax)
+adcb $7, %al
+adcb $7, %dil
+adcb $7, (%rax)
+lock adcb $7, (%rax)
+adcb %sil, %dil
+adcb %sil, (%rax)
+lock adcb %sil, (%rax)
+adcb (%rax), %dil
+
+adcw $0, %ax
+adcw $0, %di
+adcw $0, (%rax)
+lock adcw $0, (%rax)
+adcw $511, %ax
+adcw $511, %di
+adcw $511, (%rax)
+lock adcw $511, (%rax)
+adcw $7, %di
+adcw $7, (%rax)
+lock adcw $7, (%rax)
+adcw %si, %di
+adcw %si, (%rax)
+lock adcw %si, (%rax)
+adcw (%rax), %di
+
+adcl $0, %eax
+adcl $0, %edi
+adcl $0, (%rax)
+lock adcl $0, (%rax)
+adcl $665536, %eax
+adcl $665536, %edi
+adcl $665536, (%rax)
+lock adcl $665536, (%rax)
+adcl $7, %edi
+adcl $7, (%rax)
+lock adcl $7, (%rax)
+adcl %esi, %edi
+adcl %esi, (%rax)
+lock adcl %esi, (%rax)
+adcl (%rax), %edi
+
+adcq $0, %rax
+adcq $0, %rdi
+adcq $0, (%rax)
+lock adcq $0, (%rax)
+adcq $665536, %rax
+adcq $665536, %rdi
+adcq $665536, (%rax)
+lock adcq $665536, (%rax)
+adcq $7, %rdi
+adcq $7, (%rax)
+lock adcq $7, (%rax)
+adcq %rsi, %rdi
+adcq %rsi, (%rax)
+lock adcq %rsi, (%rax)
+adcq (%rax), %rdi
+
+addb $7, %al
+addb $7, %dil
+addb $7, (%rax)
+lock addb $7, (%rax)
+addb %sil, %dil
+addb %sil, (%rax)
+lock addb %sil, (%rax)
+addb (%rax), %dil
+
+addw $511, %ax
+addw $511, %di
+addw $511, (%rax)
+lock addw $511, (%rax)
+addw $7, %di
+addw $7, (%rax)
+lock addw $7, (%rax)
+addw %si, %di
+addw %si, (%rax)
+lock addw %si, (%rax)
+addw (%rax), %di
+
+addl $665536, %eax
+addl $665536, %edi
+addl $665536, (%rax)
+lock addl $665536, (%rax)
+addl $7, %edi
+addl $7, (%rax)
+lock addl $7, (%rax)
+addl %esi, %edi
+addl %esi, (%rax)
+lock addl %esi, (%rax)
+addl (%rax), %edi
+
+addq $665536, %rax
+addq $665536, %rdi
+addq $665536, (%rax)
+lock addq $665536, (%rax)
+addq $7, %rdi
+addq $7, (%rax)
+lock addq $7, (%rax)
+addq %rsi, %rdi
+addq %rsi, (%rax)
+lock addq %rsi, (%rax)
+addq (%rax), %rdi
+
+andb $7, %al
+andb $7, %dil
+andb $7, (%rax)
+lock andb $7, (%rax)
+andb %sil, %dil
+andb %sil, (%rax)
+lock andb %sil, (%rax)
+andb (%rax), %dil
+
+andw $511, %ax
+andw $511, %di
+andw $511, (%rax)
+lock andw $511, (%rax)
+andw $7, %di
+andw $7, (%rax)
+lock andw $7, (%rax)
+andw %si, %di
+andw %si, (%rax)
+lock andw %si, (%rax)
+andw (%rax), %di
+
+andl $665536, %eax
+andl $665536, %edi
+andl $665536, (%rax)
+lock andl $665536, (%rax)
+andl $7, %edi
+andl $7, (%rax)
+lock andl $7, (%rax)
+andl %esi, %edi
+andl %esi, (%rax)
+lock andl %esi, (%rax)
+andl (%rax), %edi
+
+andq $665536, %rax
+andq $665536, %rdi
+andq $665536, (%rax)
+lock andq $665536, (%rax)
+andq $7, %rdi
+andq $7, (%rax)
+lock andq $7, (%rax)
+andq %rsi, %rdi
+andq %rsi, (%rax)
+lock andq %rsi, (%rax)
+andq (%rax), %rdi
+
+bsfw %si, %di
+bsrw %si, %di
+bsfw (%rax), %di
+bsrw (%rax), %di
+
+bsfl %esi, %edi
+bsrl %esi, %edi
+bsfl (%rax), %edi
+bsrl (%rax), %edi
+
+bsfq %rsi, %rdi
+bsrq %rsi, %rdi
+bsfq (%rax), %rdi
+bsrq (%rax), %rdi
+
+bswap %eax
+bswap %rax
+
+btw %si, %di
+btcw %si, %di
+btrw %si, %di
+btsw %si, %di
+btw %si, (%rax)
+btcw %si, (%rax)
+btrw %si, (%rax)
+btsw %si, (%rax)
+lock btcw %si, (%rax)
+lock btrw %si, (%rax)
+lock btsw %si, (%rax)
+btw $7, %di
+btcw $7, %di
+btrw $7, %di
+btsw $7, %di
+btw $7, (%rax)
+btcw $7, (%rax)
+btrw $7, (%rax)
+btsw $7, (%rax)
+lock btcw $7, (%rax)
+lock btrw $7, (%rax)
+lock btsw $7, (%rax)
+
+btl %esi, %edi
+btcl %esi, %edi
+btrl %esi, %edi
+btsl %esi, %edi
+btl %esi, (%rax)
+btcl %esi, (%rax)
+btrl %esi, (%rax)
+btsl %esi, (%rax)
+lock btcl %esi, (%rax)
+lock btrl %esi, (%rax)
+lock btsl %esi, (%rax)
+btl $7, %edi
+btcl $7, %edi
+btrl $7, %edi
+btsl $7, %edi
+btl $7, (%rax)
+btcl $7, (%rax)
+btrl $7, (%rax)
+btsl $7, (%rax)
+lock btcl $7, (%rax)
+lock btrl $7, (%rax)
+lock btsl $7, (%rax)
+
+btq %rsi, %rdi
+btcq %rsi, %rdi
+btrq %rsi, %rdi
+btsq %rsi, %rdi
+btq %rsi, (%rax)
+btcq %rsi, (%rax)
+btrq %rsi, (%rax)
+btsq %rsi, (%rax)
+lock btcq %rsi, (%rax)
+lock btrq %rsi, (%rax)
+lock btsq %rsi, (%rax)
+btq $7, %rdi
+btcq $7, %rdi
+btrq $7, %rdi
+btsq $7, %rdi
+btq $7, (%rax)
+btcq $7, (%rax)
+btrq $7, (%rax)
+btsq $7, (%rax)
+lock btcq $7, (%rax)
+lock btrq $7, (%rax)
+lock btsq $7, (%rax)
+
+cbw
+cwde
+cdqe
+cwd
+cdq
+cqo
+
+clc
+cld
+cmc
+
+cmpb $7, %al
+cmpb $7, %dil
+cmpb $7, (%rax)
+cmpb %sil, %dil
+cmpb %sil, (%rax)
+cmpb (%rax), %dil
+
+cmpw $511, %ax
+cmpw $511, %di
+cmpw $511, (%rax)
+cmpw $7, %di
+cmpw $7, (%rax)
+cmpw %si, %di
+cmpw %si, (%rax)
+cmpw (%rax), %di
+
+cmpl $665536, %eax
+cmpl $665536, %edi
+cmpl $665536, (%rax)
+cmpl $7, %edi
+cmpl $7, (%rax)
+cmpl %esi, %edi
+cmpl %esi, (%rax)
+cmpl (%rax), %edi
+
+cmpq $665536, %rax
+cmpq $665536, %rdi
+cmpq $665536, (%rax)
+cmpq $7, %rdi
+cmpq $7, (%rax)
+cmpq %rsi, %rdi
+cmpq %rsi, (%rax)
+cmpq (%rax), %rdi
+
+cmpsb
+cmpsw
+cmpsl
+cmpsq
+
+cmpxchgb %cl, %bl
+cmpxchgb %cl, (%rbx)
+lock cmpxchgb %cl, (%rbx)
+
+cmpxchgw %cx, %bx
+cmpxchgw %cx, (%rbx)
+lock cmpxchgw %cx, (%rbx)
+
+cmpxchgl %ecx, %ebx
+cmpxchgl %ecx, (%rbx)
+lock cmpxchgl %ecx, (%rbx)
+
+cmpxchgq %rcx, %rbx
+cmpxchgq %rcx, (%rbx)
+lock cmpxchgq %rcx, (%rbx)
+
+cpuid
+
+decb %dil
+decb (%rax)
+lock decb (%rax)
+decw %di
+decw (%rax)
+lock decw (%rax)
+decl %edi
+decl (%rax)
+lock decl (%rax)
+decq %rdi
+decq (%rax)
+lock decq (%rax)
+
+divb %dil
+divb (%rax)
+divw %si
+divw (%rax)
+divl %edx
+divl (%rax)
+divq %rcx
+divq (%rax)
+
+enter $7, $4095
+
+idivb %dil
+idivb (%rax)
+idivw %si
+idivw (%rax)
+idivl %edx
+idivl (%rax)
+idivq %rcx
+idivq (%rax)
+
+imulb %dil
+imulb (%rax)
+
+imulw %di
+imulw (%rax)
+imulw %si, %di
+imulw (%rax), %di
+imulw $511, %si, %di
+imulw $511, (%rax), %di
+imulw $7, %si, %di
+imulw $7, (%rax), %di
+
+imull %edi
+imull (%rax)
+imull %esi, %edi
+imull (%rax), %edi
+imull $665536, %esi, %edi
+imull $665536, (%rax), %edi
+imull $7, %esi, %edi
+imull $7, (%rax), %edi
+
+imulq %rdi
+imulq (%rax)
+imulq %rsi, %rdi
+imulq (%rax), %rdi
+imulq $665536, %rsi, %rdi
+imulq $665536, (%rax), %rdi
+imulq $7, %rsi, %rdi
+imulq $7, (%rax), %rdi
+
+inb $7, %al
+inb %dx, %al
+inw $7, %ax
+inw %dx, %ax
+inl $7, %eax
+inl %dx, %eax
+
+incb %dil
+incb (%rax)
+lock incb (%rax)
+incw %di
+incw (%rax)
+lock incw (%rax)
+incl %edi
+incl (%rax)
+lock incl (%rax)
+incq %rdi
+incq (%rax)
+lock incq (%rax)
+
+insb
+insw
+insl
+
+int $7
+
+invlpg (%rax)
+invlpga %rax, %ecx
+
+lahf
+
+leave
+
+lodsb
+lodsw
+lodsl
+lodsq
+
+movsb
+movsw
+movsl
+movsq
+
+movsbw %al, %di
+movzbw %al, %di
+movsbw (%rax), %di
+movzbw (%rax), %di
+movsbl %al, %edi
+movzbl %al, %edi
+movsbl (%rax), %edi
+movzbl (%rax), %edi
+movsbq %al, %rdi
+movzbq %al, %rdi
+movsbq (%rax), %rdi
+movzbq (%rax), %rdi
+
+movswl %ax, %edi
+movzwl %ax, %edi
+movswl (%rax), %edi
+movzwl (%rax), %edi
+movswq %ax, %rdi
+movzwq %ax, %rdi
+movswq (%rax), %rdi
+movzwq (%rax), %rdi
+
+movslq %eax, %rdi
+movslq (%rax), %rdi
+
+mulb %dil
+mulb (%rax)
+mulw %si
+mulw (%rax)
+mull %edx
+mull (%rax)
+mulq %rcx
+mulq (%rax)
+
+negb %dil
+negb (%r8)
+lock negb (%r8)
+negw %si
+negw (%r9)
+lock negw (%r9)
+negl %edx
+negl (%rax)
+lock negl (%rax)
+negq %rcx
+negq (%r10)
+lock negq (%r10)
+
+nop
+nopw %di
+nopw (%rcx)
+nopl %esi
+nopl (%r8)
+nopq %rdx
+nopq (%r9)
+
+notb %dil
+notb (%r8)
+lock notb (%r8)
+notw %si
+notw (%r9)
+lock notw (%r9)
+notl %edx
+notl (%rax)
+lock notl (%rax)
+notq %rcx
+notq (%r10)
+lock notq (%r10)
+
+orb $7, %al
+orb $7, %dil
+orb $7, (%rax)
+lock orb $7, (%rax)
+orb %sil, %dil
+orb %sil, (%rax)
+lock orb %sil, (%rax)
+orb (%rax), %dil
+
+orw $511, %ax
+orw $511, %di
+orw $511, (%rax)
+lock orw $511, (%rax)
+orw $7, %di
+orw $7, (%rax)
+lock orw $7, (%rax)
+orw %si, %di
+orw %si, (%rax)
+lock orw %si, (%rax)
+orw (%rax), %di
+
+orl $665536, %eax
+orl $665536, %edi
+orl $665536, (%rax)
+lock orl $665536, (%rax)
+orl $7, %edi
+orl $7, (%rax)
+lock orl $7, (%rax)
+orl %esi, %edi
+orl %esi, (%rax)
+lock orl %esi, (%rax)
+orl (%rax), %edi
+
+orq $665536, %rax
+orq $665536, %rdi
+orq $665536, (%rax)
+lock orq $665536, (%rax)
+orq $7, %rdi
+orq $7, (%rax)
+lock orq $7, (%rax)
+orq %rsi, %rdi
+orq %rsi, (%rax)
+lock orq %rsi, (%rax)
+orq (%rax), %rdi
+
+outb %al, $7
+outb %al, %dx
+outw %ax, $7
+outw %ax, %dx
+outl %eax, $7
+outl %eax, %dx
+
+outsb
+outsw
+outsl
+
+pause
+
+rclb %dil
+rcrb %dil
+rclb (%rax)
+rcrb (%rax)
+rclb $7, %dil
+rcrb $7, %dil
+rclb $7, (%rax)
+rcrb $7, (%rax)
+rclb %cl, %dil
+rcrb %cl, %dil
+rclb %cl, (%rax)
+rcrb %cl, (%rax)
+
+rclw %di
+rcrw %di
+rclw (%rax)
+rcrw (%rax)
+rclw $7, %di
+rcrw $7, %di
+rclw $7, (%rax)
+rcrw $7, (%rax)
+rclw %cl, %di
+rcrw %cl, %di
+rclw %cl, (%rax)
+rcrw %cl, (%rax)
+
+rcll %edi
+rcrl %edi
+rcll (%rax)
+rcrl (%rax)
+rcll $7, %edi
+rcrl $7, %edi
+rcll $7, (%rax)
+rcrl $7, (%rax)
+rcll %cl, %edi
+rcrl %cl, %edi
+rcll %cl, (%rax)
+rcrl %cl, (%rax)
+
+rclq %rdi
+rcrq %rdi
+rclq (%rax)
+rcrq (%rax)
+rclq $7, %rdi
+rcrq $7, %rdi
+rclq $7, (%rax)
+rcrq $7, (%rax)
+rclq %cl, %rdi
+rcrq %cl, %rdi
+rclq %cl, (%rax)
+rcrq %cl, (%rax)
+
+rdmsr
+rdpmc
+rdtsc
+rdtscp
+
+rolb %dil
+rorb %dil
+rolb (%rax)
+rorb (%rax)
+rolb $7, %dil
+rorb $7, %dil
+rolb $7, (%rax)
+rorb $7, (%rax)
+rolb %cl, %dil
+rorb %cl, %dil
+rolb %cl, (%rax)
+rorb %cl, (%rax)
+
+rolw %di
+rorw %di
+rolw (%rax)
+rorw (%rax)
+rolw $7, %di
+rorw $7, %di
+rolw $7, (%rax)
+rorw $7, (%rax)
+rolw %cl, %di
+rorw %cl, %di
+rolw %cl, (%rax)
+rorw %cl, (%rax)
+
+roll %edi
+rorl %edi
+roll (%rax)
+rorl (%rax)
+roll $7, %edi
+rorl $7, %edi
+roll $7, (%rax)
+rorl $7, (%rax)
+roll %cl, %edi
+rorl %cl, %edi
+roll %cl, (%rax)
+rorl %cl, (%rax)
+
+rolq %rdi
+rorq %rdi
+rolq (%rax)
+rorq (%rax)
+rolq $7, %rdi
+rorq $7, %rdi
+rolq $7, (%rax)
+rorq $7, (%rax)
+rolq %cl, %rdi
+rorq %cl, %rdi
+rolq %cl, (%rax)
+rorq %cl, (%rax)
+
+sahf
+
+sarb %dil
+shlb %dil
+shrb %dil
+sarb (%rax)
+shlb (%rax)
+shrb (%rax)
+sarb $7, %dil
+shlb $7, %dil
+shrb $7, %dil
+sarb $7, (%rax)
+shlb $7, (%rax)
+shrb $7, (%rax)
+sarb %cl, %dil
+shlb %cl, %dil
+shrb %cl, %dil
+sarb %cl, (%rax)
+shlb %cl, (%rax)
+shrb %cl, (%rax)
+
+sarw %di
+shlw %di
+shrw %di
+sarw (%rax)
+shlw (%rax)
+shrw (%rax)
+sarw $7, %di
+shlw $7, %di
+shrw $7, %di
+sarw $7, (%rax)
+shlw $7, (%rax)
+shrw $7, (%rax)
+sarw %cl, %di
+shlw %cl, %di
+shrw %cl, %di
+sarw %cl, (%rax)
+shlw %cl, (%rax)
+shrw %cl, (%rax)
+
+sarl %edi
+shll %edi
+shrl %edi
+sarl (%rax)
+shll (%rax)
+shrl (%rax)
+sarl $7, %edi
+shll $7, %edi
+shrl $7, %edi
+sarl $7, (%rax)
+shll $7, (%rax)
+shrl $7, (%rax)
+sarl %cl, %edi
+shll %cl, %edi
+shrl %cl, %edi
+sarl %cl, (%rax)
+shll %cl, (%rax)
+shrl %cl, (%rax)
+
+sarq %rdi
+shlq %rdi
+shrq %rdi
+sarq (%rax)
+shlq (%rax)
+shrq (%rax)
+sarq $7, %rdi
+shlq $7, %rdi
+shrq $7, %rdi
+sarq $7, (%rax)
+shlq $7, (%rax)
+shrq $7, (%rax)
+sarq %cl, %rdi
+shlq %cl, %rdi
+shrq %cl, %rdi
+sarq %cl, (%rax)
+shlq %cl, (%rax)
+shrq %cl, (%rax)
+
+sbbb $0, %al
+sbbb $0, %dil
+sbbb $0, (%rax)
+lock sbbb $0, (%rax)
+sbbb $7, %al
+sbbb $7, %dil
+sbbb $7, (%rax)
+lock sbbb $7, (%rax)
+sbbb %sil, %dil
+sbbb %sil, (%rax)
+lock sbbb %sil, (%rax)
+sbbb (%rax), %dil
+
+sbbw $0, %ax
+sbbw $0, %di
+sbbw $0, (%rax)
+lock sbbw $0, (%rax)
+sbbw $511, %ax
+sbbw $511, %di
+sbbw $511, (%rax)
+lock sbbw $511, (%rax)
+sbbw $7, %di
+sbbw $7, (%rax)
+lock sbbw $7, (%rax)
+sbbw %si, %di
+sbbw %si, (%rax)
+lock sbbw %si, (%rax)
+sbbw (%rax), %di
+
+sbbl $0, %eax
+sbbl $0, %edi
+sbbl $0, (%rax)
+lock sbbl $0, (%rax)
+sbbl $665536, %eax
+sbbl $665536, %edi
+sbbl $665536, (%rax)
+lock sbbl $665536, (%rax)
+sbbl $7, %edi
+sbbl $7, (%rax)
+lock sbbl $7, (%rax)
+sbbl %esi, %edi
+sbbl %esi, (%rax)
+lock sbbl %esi, (%rax)
+sbbl (%rax), %edi
+
+sbbq $0, %rax
+sbbq $0, %rdi
+sbbq $0, (%rax)
+lock sbbq $0, (%rax)
+sbbq $665536, %rax
+sbbq $665536, %rdi
+sbbq $665536, (%rax)
+lock sbbq $665536, (%rax)
+sbbq $7, %rdi
+sbbq $7, (%rax)
+lock sbbq $7, (%rax)
+sbbq %rsi, %rdi
+sbbq %rsi, (%rax)
+lock sbbq %rsi, (%rax)
+sbbq (%rax), %rdi
+
+scasb
+scasw
+scasl
+scasq
+
+seto %al
+seto (%rax)
+setno %al
+setno (%rax)
+setb %al
+setb (%rax)
+setnb %al
+setnb (%rax)
+setz %al
+setz (%rax)
+setnz %al
+setnz (%rax)
+seta %al
+seta (%rax)
+setna %al
+setna (%rax)
+sets %al
+sets (%rax)
+setns %al
+setns (%rax)
+setp %al
+setp (%rax)
+setnp %al
+setnp (%rax)
+setl %al
+setl (%rax)
+setnl %al
+setnl (%rax)
+setg %al
+setg (%rax)
+setng %al
+setng (%rax)
+
+shldw %cl, %si, %di
+shrdw %cl, %si, %di
+shldw %cl, %si, (%rax)
+shrdw %cl, %si, (%rax)
+shldw $7, %si, %di
+shrdw $7, %si, %di
+shldw $7, %si, (%rax)
+shrdw $7, %si, (%rax)
+
+shldl %cl, %esi, %edi
+shrdl %cl, %esi, %edi
+shldl %cl, %esi, (%rax)
+shrdl %cl, %esi, (%rax)
+shldl $7, %esi, %edi
+shrdl $7, %esi, %edi
+shldl $7, %esi, (%rax)
+shrdl $7, %esi, (%rax)
+
+shldq %cl, %rsi, %rdi
+shrdq %cl, %rsi, %rdi
+shldq %cl, %rsi, (%rax)
+shrdq %cl, %rsi, (%rax)
+shldq $7, %rsi, %rdi
+shrdq $7, %rsi, %rdi
+shldq $7, %rsi, (%rax)
+shrdq $7, %rsi, (%rax)
+
+stc
+std
+
+stosb
+stosw
+stosl
+stosq
+
+subb $7, %al
+subb $7, %dil
+subb $7, (%rax)
+lock subb $7, (%rax)
+subb %sil, %dil
+subb %sil, (%rax)
+lock subb %sil, (%rax)
+subb (%rax), %dil
+
+subw $511, %ax
+subw $511, %di
+subw $511, (%rax)
+lock subw $511, (%rax)
+subw $7, %di
+subw $7, (%rax)
+lock subw $7, (%rax)
+subw %si, %di
+subw %si, (%rax)
+lock subw %si, (%rax)
+subw (%rax), %di
+
+subl $665536, %eax
+subl $665536, %edi
+subl $665536, (%rax)
+lock subl $665536, (%rax)
+subl $7, %edi
+subl $7, (%rax)
+lock subl $7, (%rax)
+subl %esi, %edi
+subl %esi, (%rax)
+lock subl %esi, (%rax)
+subl (%rax), %edi
+
+subq $665536, %rax
+subq $665536, %rdi
+subq $665536, (%rax)
+lock subq $665536, (%rax)
+subq $7, %rdi
+subq $7, (%rax)
+lock subq $7, (%rax)
+subq %rsi, %rdi
+subq %rsi, (%rax)
+lock subq %rsi, (%rax)
+subq (%rax), %rdi
+
+testb $7, %al
+testb $7, %dil
+testb $7, (%rax)
+testb %sil, %dil
+testb %sil, (%rax)
+
+testw $511, %ax
+testw $511, %di
+testw $511, (%rax)
+testw $7, %di
+testw $7, (%rax)
+testw %si, %di
+testw %si, (%rax)
+
+testl $665536, %eax
+testl $665536, %edi
+testl $665536, (%rax)
+testl $7, %edi
+testl $7, (%rax)
+testl %esi, %edi
+testl %esi, (%rax)
+
+testq $665536, %rax
+testq $665536, %rdi
+testq $665536, (%rax)
+testq $7, %rdi
+testq $7, (%rax)
+testq %rsi, %rdi
+testq %rsi, (%rax)
+
+ud2
+
+wrmsr
+
+xaddb %bl, %cl
+xaddb %bl, (%rcx)
+lock xaddb %bl, (%rcx)
+
+xaddw %bx, %cx
+xaddw %ax, (%rbx)
+lock xaddw %ax, (%rbx)
+
+xaddl %ebx, %ecx
+xaddl %eax, (%rbx)
+lock xaddl %eax, (%rbx)
+
+xaddq %rbx, %rcx
+xaddq %rax, (%rbx)
+lock xaddq %rax, (%rbx)
+
+xchgb %bl, %cl
+xchgb %bl, (%rbx)
+lock xchgb %bl, (%rbx)
+
+xchgw %ax, %bx
+xchgw %bx, %cx
+xchgw %ax, (%rbx)
+lock xchgw %ax, (%rbx)
+
+xchgl %eax, %ebx
+xchgl %ebx, %ecx
+xchgl %eax, (%rbx)
+lock xchgl %eax, (%rbx)
+
+xchgq %rax, %rbx
+xchgq %rbx, %rcx
+xchgq %rax, (%rbx)
+lock xchgq %rax, (%rbx)
+
+xlatb
+
+xorb $7, %al
+xorb $7, %dil
+xorb $7, (%rax)
+lock xorb $7, (%rax)
+xorb %sil, %dil
+xorb %sil, (%rax)
+lock xorb %sil, (%rax)
+xorb (%rax), %dil
+
+xorw $511, %ax
+xorw $511, %di
+xorw $511, (%rax)
+lock xorw $511, (%rax)
+xorw $7, %di
+xorw $7, (%rax)
+lock xorw $7, (%rax)
+xorw %si, %di
+xorw %si, (%rax)
+lock xorw %si, (%rax)
+xorw (%rax), %di
+
+xorl $665536, %eax
+xorl $665536, %edi
+xorl $665536, (%rax)
+lock xorl $665536, (%rax)
+xorl $7, %edi
+xorl $7, (%rax)
+lock xorl $7, (%rax)
+xorl %esi, %edi
+xorl %esi, (%rax)
+lock xorl %esi, (%rax)
+xorl (%rax), %edi
+
+xorq $665536, %rax
+xorq $665536, %rdi
+xorq $665536, (%rax)
+lock xorq $665536, (%rax)
+xorq $7, %rdi
+xorq $7, (%rax)
+lock xorq $7, (%rax)
+xorq %rsi, %rdi
+xorq %rsi, (%rax)
+lock xorq %rsi, (%rax)
+xorq (%rax), %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 adcb $0, %al
+# CHECK-NEXT: 1 1 0.50 adcb $0, %dil
+# CHECK-NEXT: 5 13 0.50 * * adcb $0, (%rax)
+# CHECK-NEXT: 5 13 0.50 * * lock adcb $0, (%rax)
+# CHECK-NEXT: 1 1 0.50 adcb $7, %al
+# CHECK-NEXT: 1 1 0.50 adcb $7, %dil
+# CHECK-NEXT: 5 13 0.50 * * adcb $7, (%rax)
+# CHECK-NEXT: 5 13 0.50 * * lock adcb $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 adcb %sil, %dil
+# CHECK-NEXT: 6 13 0.60 * * adcb %sil, (%rax)
+# CHECK-NEXT: 6 13 0.60 * * lock adcb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.50 * adcb (%rax), %dil
+# CHECK-NEXT: 1 1 0.50 adcw $0, %ax
+# CHECK-NEXT: 1 1 0.50 adcw $0, %di
+# CHECK-NEXT: 5 12 0.50 * * adcw $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcw $0, (%rax)
+# CHECK-NEXT: 1 1 0.50 adcw $511, %ax
+# CHECK-NEXT: 1 1 0.50 adcw $511, %di
+# CHECK-NEXT: 5 12 0.50 * * adcw $511, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcw $511, (%rax)
+# CHECK-NEXT: 1 1 0.50 adcw $7, %di
+# CHECK-NEXT: 5 12 0.50 * * adcw $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcw $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 adcw %si, %di
+# CHECK-NEXT: 6 12 0.60 * * adcw %si, (%rax)
+# CHECK-NEXT: 6 12 0.60 * * lock adcw %si, (%rax)
+# CHECK-NEXT: 2 6 0.50 * adcw (%rax), %di
+# CHECK-NEXT: 1 1 0.50 adcl $0, %eax
+# CHECK-NEXT: 1 1 0.50 adcl $0, %edi
+# CHECK-NEXT: 5 12 0.50 * * adcl $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcl $0, (%rax)
+# CHECK-NEXT: 1 1 0.50 adcl $665536, %eax
+# CHECK-NEXT: 1 1 0.50 adcl $665536, %edi
+# CHECK-NEXT: 5 12 0.50 * * adcl $665536, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.50 adcl $7, %edi
+# CHECK-NEXT: 5 12 0.50 * * adcl $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcl $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 adcl %esi, %edi
+# CHECK-NEXT: 6 12 0.60 * * adcl %esi, (%rax)
+# CHECK-NEXT: 6 12 0.60 * * lock adcl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.50 * adcl (%rax), %edi
+# CHECK-NEXT: 1 1 0.50 adcq $0, %rax
+# CHECK-NEXT: 1 1 0.50 adcq $0, %rdi
+# CHECK-NEXT: 5 12 0.50 * * adcq $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcq $0, (%rax)
+# CHECK-NEXT: 1 1 0.50 adcq $665536, %rax
+# CHECK-NEXT: 1 1 0.50 adcq $665536, %rdi
+# CHECK-NEXT: 5 12 0.50 * * adcq $665536, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.50 adcq $7, %rdi
+# CHECK-NEXT: 5 12 0.50 * * adcq $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock adcq $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 adcq %rsi, %rdi
+# CHECK-NEXT: 6 12 0.60 * * adcq %rsi, (%rax)
+# CHECK-NEXT: 6 12 0.60 * * lock adcq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.50 * adcq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.20 addb $7, %al
+# CHECK-NEXT: 1 1 0.20 addb $7, %dil
+# CHECK-NEXT: 4 13 0.50 * * addb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock addb $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 addb %sil, %dil
+# CHECK-NEXT: 4 13 0.50 * * addb %sil, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock addb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * addb (%rax), %dil
+# CHECK-NEXT: 1 1 0.20 addw $511, %ax
+# CHECK-NEXT: 1 1 0.20 addw $511, %di
+# CHECK-NEXT: 4 12 0.50 * * addw $511, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock addw $511, (%rax)
+# CHECK-NEXT: 1 1 0.20 addw $7, %di
+# CHECK-NEXT: 4 12 0.50 * * addw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock addw $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 addw %si, %di
+# CHECK-NEXT: 4 12 0.50 * * addw %si, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock addw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * addw (%rax), %di
+# CHECK-NEXT: 1 1 0.20 addl $665536, %eax
+# CHECK-NEXT: 1 1 0.20 addl $665536, %edi
+# CHECK-NEXT: 4 12 0.50 * * addl $665536, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock addl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 addl $7, %edi
+# CHECK-NEXT: 4 12 0.50 * * addl $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock addl $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 addl %esi, %edi
+# CHECK-NEXT: 4 12 0.50 * * addl %esi, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock addl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * addl (%rax), %edi
+# CHECK-NEXT: 1 1 0.20 addq $665536, %rax
+# CHECK-NEXT: 1 1 0.20 addq $665536, %rdi
+# CHECK-NEXT: 4 12 0.50 * * addq $665536, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock addq $665536, (%rax)
+# CHECK-NEXT: 0 1 0.00 addq $7, %rdi
+# CHECK-NEXT: 4 12 0.50 * * addq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock addq $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 addq %rsi, %rdi
+# CHECK-NEXT: 4 12 0.50 * * addq %rsi, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock addq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * addq (%rax), %rdi
+# CHECK-NEXT: 1 2 0.20 andb $7, %al
+# CHECK-NEXT: 1 2 0.20 andb $7, %dil
+# CHECK-NEXT: 4 13 0.50 * * andb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock andb $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 andb %sil, %dil
+# CHECK-NEXT: 4 13 0.50 * * andb %sil, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock andb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * andb (%rax), %dil
+# CHECK-NEXT: 1 1 0.20 andw $511, %ax
+# CHECK-NEXT: 1 1 0.20 andw $511, %di
+# CHECK-NEXT: 4 12 0.50 * * andw $511, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock andw $511, (%rax)
+# CHECK-NEXT: 1 2 0.20 andw $7, %di
+# CHECK-NEXT: 4 12 0.50 * * andw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock andw $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 andw %si, %di
+# CHECK-NEXT: 4 12 0.50 * * andw %si, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock andw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * andw (%rax), %di
+# CHECK-NEXT: 1 2 0.20 andl $665536, %eax
+# CHECK-NEXT: 1 2 0.20 andl $665536, %edi
+# CHECK-NEXT: 4 12 0.50 * * andl $665536, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock andl $665536, (%rax)
+# CHECK-NEXT: 1 2 0.20 andl $7, %edi
+# CHECK-NEXT: 4 12 0.50 * * andl $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock andl $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 andl %esi, %edi
+# CHECK-NEXT: 4 12 0.50 * * andl %esi, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock andl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * andl (%rax), %edi
+# CHECK-NEXT: 1 2 0.20 andq $665536, %rax
+# CHECK-NEXT: 1 2 0.20 andq $665536, %rdi
+# CHECK-NEXT: 4 12 0.50 * * andq $665536, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock andq $665536, (%rax)
+# CHECK-NEXT: 1 2 0.20 andq $7, %rdi
+# CHECK-NEXT: 4 12 0.50 * * andq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock andq $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 andq %rsi, %rdi
+# CHECK-NEXT: 4 12 0.50 * * andq %rsi, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock andq %rsi, (%rax)
+# CHECK-NEXT: 2 7 0.33 * andq (%rax), %rdi
+# CHECK-NEXT: 1 3 1.00 bsfw %si, %di
+# CHECK-NEXT: 1 3 1.00 bsrw %si, %di
+# CHECK-NEXT: 2 8 1.00 * bsfw (%rax), %di
+# CHECK-NEXT: 2 8 1.00 * bsrw (%rax), %di
+# CHECK-NEXT: 1 3 1.00 bsfl %esi, %edi
+# CHECK-NEXT: 1 3 1.00 bsrl %esi, %edi
+# CHECK-NEXT: 2 8 1.00 * bsfl (%rax), %edi
+# CHECK-NEXT: 2 8 1.00 * bsrl (%rax), %edi
+# CHECK-NEXT: 1 3 1.00 bsfq %rsi, %rdi
+# CHECK-NEXT: 1 3 1.00 bsrq %rsi, %rdi
+# CHECK-NEXT: 2 8 1.00 * bsfq (%rax), %rdi
+# CHECK-NEXT: 2 8 1.00 * bsrq (%rax), %rdi
+# CHECK-NEXT: 1 1 1.00 bswapl %eax
+# CHECK-NEXT: 2 2 1.00 bswapq %rax
+# CHECK-NEXT: 1 1 1.00 btw %si, %di
+# CHECK-NEXT: 1 1 1.00 btcw %si, %di
+# CHECK-NEXT: 1 1 1.00 btrw %si, %di
+# CHECK-NEXT: 1 1 1.00 btsw %si, %di
+# CHECK-NEXT: 10 11 1.80 * btw %si, (%rax)
+# CHECK-NEXT: 11 18 1.60 * * btcw %si, (%rax)
+# CHECK-NEXT: 11 18 1.60 * * btrw %si, (%rax)
+# CHECK-NEXT: 11 18 1.60 * * btsw %si, (%rax)
+# CHECK-NEXT: 11 18 1.60 * * lock btcw %si, (%rax)
+# CHECK-NEXT: 11 18 1.60 * * lock btrw %si, (%rax)
+# CHECK-NEXT: 11 18 1.60 * * lock btsw %si, (%rax)
+# CHECK-NEXT: 1 1 1.00 btw $7, %di
+# CHECK-NEXT: 1 1 1.00 btcw $7, %di
+# CHECK-NEXT: 1 1 1.00 btrw $7, %di
+# CHECK-NEXT: 1 1 1.00 btsw $7, %di
+# CHECK-NEXT: 2 6 1.00 * btw $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * btcw $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * btrw $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * btsw $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * lock btcw $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * lock btrw $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * lock btsw $7, (%rax)
+# CHECK-NEXT: 1 1 1.00 btl %esi, %edi
+# CHECK-NEXT: 1 1 1.00 btcl %esi, %edi
+# CHECK-NEXT: 1 1 1.00 btrl %esi, %edi
+# CHECK-NEXT: 1 1 1.00 btsl %esi, %edi
+# CHECK-NEXT: 10 11 1.80 * btl %esi, (%rax)
+# CHECK-NEXT: 11 18 1.60 * * btcl %esi, (%rax)
+# CHECK-NEXT: 11 18 1.60 * * btrl %esi, (%rax)
+# CHECK-NEXT: 11 18 1.60 * * btsl %esi, (%rax)
+# CHECK-NEXT: 11 18 1.60 * * lock btcl %esi, (%rax)
+# CHECK-NEXT: 11 18 1.60 * * lock btrl %esi, (%rax)
+# CHECK-NEXT: 11 18 1.60 * * lock btsl %esi, (%rax)
+# CHECK-NEXT: 1 1 1.00 btl $7, %edi
+# CHECK-NEXT: 1 1 1.00 btcl $7, %edi
+# CHECK-NEXT: 1 1 1.00 btrl $7, %edi
+# CHECK-NEXT: 1 1 1.00 btsl $7, %edi
+# CHECK-NEXT: 2 6 1.00 * btl $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * btcl $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * btrl $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * btsl $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * lock btcl $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * lock btrl $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * lock btsl $7, (%rax)
+# CHECK-NEXT: 1 3 1.00 btq %rsi, %rdi
+# CHECK-NEXT: 1 3 1.00 btcq %rsi, %rdi
+# CHECK-NEXT: 1 3 1.00 btrq %rsi, %rdi
+# CHECK-NEXT: 1 3 1.00 btsq %rsi, %rdi
+# CHECK-NEXT: 9 10 1.60 * btq %rsi, (%rax)
+# CHECK-NEXT: 10 17 1.40 * * btcq %rsi, (%rax)
+# CHECK-NEXT: 10 17 1.40 * * btrq %rsi, (%rax)
+# CHECK-NEXT: 10 17 1.40 * * btsq %rsi, (%rax)
+# CHECK-NEXT: 10 17 1.40 * * lock btcq %rsi, (%rax)
+# CHECK-NEXT: 10 17 1.40 * * lock btrq %rsi, (%rax)
+# CHECK-NEXT: 10 17 1.40 * * lock btsq %rsi, (%rax)
+# CHECK-NEXT: 1 1 1.00 btq $7, %rdi
+# CHECK-NEXT: 1 1 1.00 btcq $7, %rdi
+# CHECK-NEXT: 1 1 1.00 btrq $7, %rdi
+# CHECK-NEXT: 1 1 1.00 btsq $7, %rdi
+# CHECK-NEXT: 2 6 1.00 * btq $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * btcq $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * btrq $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * btsq $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * lock btcq $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * lock btrq $7, (%rax)
+# CHECK-NEXT: 4 12 1.00 * * lock btsq $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 cbtw
+# CHECK-NEXT: 1 1 0.50 cwtl
+# CHECK-NEXT: 1 1 0.50 cltq
+# CHECK-NEXT: 2 2 0.50 cwtd
+# CHECK-NEXT: 1 1 0.50 cltd
+# CHECK-NEXT: 1 1 0.50 cqto
+# CHECK-NEXT: 0 1 0.00 U clc
+# CHECK-NEXT: 2 3 0.50 U cld
+# CHECK-NEXT: 1 1 0.20 U cmc
+# CHECK-NEXT: 1 1 0.20 cmpb $7, %al
+# CHECK-NEXT: 1 1 0.20 cmpb $7, %dil
+# CHECK-NEXT: 2 6 0.33 * cmpb $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 cmpb %sil, %dil
+# CHECK-NEXT: 2 6 0.33 * cmpb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * cmpb (%rax), %dil
+# CHECK-NEXT: 1 1 0.20 cmpw $511, %ax
+# CHECK-NEXT: 1 1 0.20 cmpw $511, %di
+# CHECK-NEXT: 2 6 0.33 * cmpw $511, (%rax)
+# CHECK-NEXT: 1 1 0.20 cmpw $7, %di
+# CHECK-NEXT: 2 6 0.33 * cmpw $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 cmpw %si, %di
+# CHECK-NEXT: 2 6 0.33 * cmpw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * cmpw (%rax), %di
+# CHECK-NEXT: 1 1 0.20 cmpl $665536, %eax
+# CHECK-NEXT: 1 1 0.20 cmpl $665536, %edi
+# CHECK-NEXT: 2 6 0.33 * cmpl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 cmpl $7, %edi
+# CHECK-NEXT: 2 6 0.33 * cmpl $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 cmpl %esi, %edi
+# CHECK-NEXT: 2 6 0.33 * cmpl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * cmpl (%rax), %edi
+# CHECK-NEXT: 1 1 0.20 cmpq $665536, %rax
+# CHECK-NEXT: 1 1 0.20 cmpq $665536, %rdi
+# CHECK-NEXT: 2 6 0.33 * cmpq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 cmpq $7, %rdi
+# CHECK-NEXT: 2 6 0.33 * cmpq $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 cmpq %rsi, %rdi
+# CHECK-NEXT: 2 6 0.33 * cmpq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * cmpq (%rax), %rdi
+# CHECK-NEXT: 7 6 1.00 U cmpsb %es:(%rdi), (%rsi)
+# CHECK-NEXT: 7 6 1.00 U cmpsw %es:(%rdi), (%rsi)
+# CHECK-NEXT: 7 6 1.00 U cmpsl %es:(%rdi), (%rsi)
+# CHECK-NEXT: 7 6 1.00 U cmpsq %es:(%rdi), (%rsi)
+# CHECK-NEXT: 5 3 1.00 cmpxchgb %cl, %bl
+# CHECK-NEXT: 6 13 1.00 * * cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 6 13 1.00 * * lock cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 5 3 1.00 cmpxchgw %cx, %bx
+# CHECK-NEXT: 6 12 1.00 * * cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: 6 12 1.00 * * lock cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: 5 3 1.00 cmpxchgl %ecx, %ebx
+# CHECK-NEXT: 6 12 1.00 * * cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: 6 12 1.00 * * lock cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: 5 3 1.00 cmpxchgq %rcx, %rbx
+# CHECK-NEXT: 6 12 1.00 * * cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: 6 12 1.00 * * lock cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: 26 18 6.00 U cpuid
+# CHECK-NEXT: 1 1 0.20 decb %dil
+# CHECK-NEXT: 4 13 0.50 * * decb (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock decb (%rax)
+# CHECK-NEXT: 1 1 0.20 decw %di
+# CHECK-NEXT: 4 12 0.50 * * decw (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock decw (%rax)
+# CHECK-NEXT: 1 1 0.20 decl %edi
+# CHECK-NEXT: 4 12 0.50 * * decl (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock decl (%rax)
+# CHECK-NEXT: 0 1 0.00 decq %rdi
+# CHECK-NEXT: 4 12 0.50 * * decq (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock decq (%rax)
+# CHECK-NEXT: 3 17 3.00 U divb %dil
+# CHECK-NEXT: 3 22 3.00 * U divb (%rax)
+# CHECK-NEXT: 4 16 3.00 U divw %si
+# CHECK-NEXT: 5 20 3.00 * U divw (%rax)
+# CHECK-NEXT: 4 15 3.00 U divl %edx
+# CHECK-NEXT: 5 19 3.00 * U divl (%rax)
+# CHECK-NEXT: 3 18 3.00 U divq %rcx
+# CHECK-NEXT: 4 23 3.00 * U divq (%rax)
+# CHECK-NEXT: 57 126 11.50 U enter $7, $4095
+# CHECK-NEXT: 3 17 3.00 U idivb %dil
+# CHECK-NEXT: 3 22 3.00 * U idivb (%rax)
+# CHECK-NEXT: 4 16 3.00 U idivw %si
+# CHECK-NEXT: 5 20 3.00 * U idivw (%rax)
+# CHECK-NEXT: 4 15 3.00 U idivl %edx
+# CHECK-NEXT: 5 19 3.00 * U idivl (%rax)
+# CHECK-NEXT: 3 18 3.00 U idivq %rcx
+# CHECK-NEXT: 4 23 3.00 * U idivq (%rax)
+# CHECK-NEXT: 1 3 1.00 imulb %dil
+# CHECK-NEXT: 2 8 1.00 * imulb (%rax)
+# CHECK-NEXT: 4 5 1.00 imulw %di
+# CHECK-NEXT: 5 10 1.00 * imulw (%rax)
+# CHECK-NEXT: 1 3 1.00 imulw %si, %di
+# CHECK-NEXT: 2 8 1.00 * imulw (%rax), %di
+# CHECK-NEXT: 2 4 1.00 imulw $511, %si, %di
+# CHECK-NEXT: 3 9 1.00 * imulw $511, (%rax), %di
+# CHECK-NEXT: 2 4 1.00 imulw $7, %si, %di
+# CHECK-NEXT: 3 9 1.00 * imulw $7, (%rax), %di
+# CHECK-NEXT: 3 4 1.00 imull %edi
+# CHECK-NEXT: 4 9 1.00 * imull (%rax)
+# CHECK-NEXT: 1 3 1.00 imull %esi, %edi
+# CHECK-NEXT: 2 8 1.00 * imull (%rax), %edi
+# CHECK-NEXT: 1 3 1.00 imull $665536, %esi, %edi
+# CHECK-NEXT: 2 8 1.00 * imull $665536, (%rax), %edi
+# CHECK-NEXT: 1 3 1.00 imull $7, %esi, %edi
+# CHECK-NEXT: 2 8 1.00 * imull $7, (%rax), %edi
+# CHECK-NEXT: 2 4 1.00 imulq %rdi
+# CHECK-NEXT: 3 9 1.00 * imulq (%rax)
+# CHECK-NEXT: 1 3 1.00 imulq %rsi, %rdi
+# CHECK-NEXT: 2 8 1.00 * imulq (%rax), %rdi
+# CHECK-NEXT: 1 3 1.00 imulq $665536, %rsi, %rdi
+# CHECK-NEXT: 2 8 1.00 * imulq $665536, (%rax), %rdi
+# CHECK-NEXT: 1 3 1.00 imulq $7, %rsi, %rdi
+# CHECK-NEXT: 2 8 1.00 * imulq $7, (%rax), %rdi
+# CHECK-NEXT: 87 35 20.00 U inb $7, %al
+# CHECK-NEXT: 86 35 20.00 U inb %dx, %al
+# CHECK-NEXT: 87 35 21.00 U inw $7, %ax
+# CHECK-NEXT: 87 35 20.00 U inw %dx, %ax
+# CHECK-NEXT: 94 35 21.00 U inl $7, %eax
+# CHECK-NEXT: 99 1 21.00 U inl %dx, %eax
+# CHECK-NEXT: 1 1 0.20 incb %dil
+# CHECK-NEXT: 4 13 0.50 * * incb (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock incb (%rax)
+# CHECK-NEXT: 1 1 0.20 incw %di
+# CHECK-NEXT: 4 12 0.50 * * incw (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock incw (%rax)
+# CHECK-NEXT: 1 1 0.20 incl %edi
+# CHECK-NEXT: 4 12 0.50 * * incl (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock incl (%rax)
+# CHECK-NEXT: 0 1 0.00 incq %rdi
+# CHECK-NEXT: 4 12 0.50 * * incq (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock incq (%rax)
+# CHECK-NEXT: 83 20 19.00 U insb %dx, %es:(%rdi)
+# CHECK-NEXT: 86 20 19.00 U insw %dx, %es:(%rdi)
+# CHECK-NEXT: 92 20 21.00 U insl %dx, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * * U int $7
+# CHECK-NEXT: 42 100 7.00 U invlpg (%rax)
+# CHECK-NEXT: 1 100 0.25 U invlpga
+# CHECK-NEXT: 1 3 0.50 lahf
+# CHECK-NEXT: 3 6 0.40 * leave
+# CHECK-NEXT: 4 6 0.60 U lodsb (%rsi), %al
+# CHECK-NEXT: 4 6 0.60 U lodsw (%rsi), %ax
+# CHECK-NEXT: 3 5 0.40 U lodsl (%rsi), %eax
+# CHECK-NEXT: 3 5 0.40 U lodsq (%rsi), %rax
+# CHECK-NEXT: 7 8 0.80 U movsb (%rsi), %es:(%rdi)
+# CHECK-NEXT: 7 7 0.80 U movsw (%rsi), %es:(%rdi)
+# CHECK-NEXT: 7 7 0.80 U movsl (%rsi), %es:(%rdi)
+# CHECK-NEXT: 7 7 0.80 U movsq (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 1 0.33 movsbw %al, %di
+# CHECK-NEXT: 1 1 0.20 movzbw %al, %di
+# CHECK-NEXT: 2 6 0.33 * movsbw (%rax), %di
+# CHECK-NEXT: 2 6 0.33 * movzbw (%rax), %di
+# CHECK-NEXT: 1 1 0.33 movsbl %al, %edi
+# CHECK-NEXT: 1 0 0.20 movzbl %al, %edi
+# CHECK-NEXT: 1 6 0.33 * movsbl (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * movzbl (%rax), %edi
+# CHECK-NEXT: 1 1 0.33 movsbq %al, %rdi
+# CHECK-NEXT: 1 0 0.20 movzbq %al, %rdi
+# CHECK-NEXT: 1 6 0.33 * movsbq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * movzbq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.33 movswl %ax, %edi
+# CHECK-NEXT: 1 1 0.20 movzwl %ax, %edi
+# CHECK-NEXT: 1 6 0.33 * movswl (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * movzwl (%rax), %edi
+# CHECK-NEXT: 1 1 0.33 movswq %ax, %rdi
+# CHECK-NEXT: 1 1 0.20 movzwq %ax, %rdi
+# CHECK-NEXT: 1 6 0.33 * movswq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * movzwq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.33 movslq %eax, %rdi
+# CHECK-NEXT: 1 6 0.33 * movslq (%rax), %rdi
+# CHECK-NEXT: 1 3 1.00 mulb %dil
+# CHECK-NEXT: 2 8 1.00 * mulb (%rax)
+# CHECK-NEXT: 4 5 1.00 mulw %si
+# CHECK-NEXT: 5 10 1.00 * mulw (%rax)
+# CHECK-NEXT: 3 4 1.00 mull %edx
+# CHECK-NEXT: 4 9 1.00 * mull (%rax)
+# CHECK-NEXT: 2 4 1.00 mulq %rcx
+# CHECK-NEXT: 3 9 1.00 * mulq (%rax)
+# CHECK-NEXT: 1 1 0.20 negb %dil
+# CHECK-NEXT: 4 13 0.50 * * negb (%r8)
+# CHECK-NEXT: 4 13 0.50 * * lock negb (%r8)
+# CHECK-NEXT: 1 1 0.20 negw %si
+# CHECK-NEXT: 4 12 0.50 * * negw (%r9)
+# CHECK-NEXT: 4 12 0.50 * * lock negw (%r9)
+# CHECK-NEXT: 1 1 0.20 negl %edx
+# CHECK-NEXT: 4 12 0.50 * * negl (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock negl (%rax)
+# CHECK-NEXT: 1 1 0.20 negq %rcx
+# CHECK-NEXT: 4 12 0.50 * * negq (%r10)
+# CHECK-NEXT: 4 12 0.50 * * lock negq (%r10)
+# CHECK-NEXT: 0 1 0.00 nop
+# CHECK-NEXT: 0 1 0.00 nopw %di
+# CHECK-NEXT: 0 1 0.00 nopw (%rcx)
+# CHECK-NEXT: 0 1 0.00 nopl %esi
+# CHECK-NEXT: 0 1 0.00 nopl (%r8)
+# CHECK-NEXT: 0 1 0.00 nopq %rdx
+# CHECK-NEXT: 0 1 0.00 nopq (%r9)
+# CHECK-NEXT: 1 1 0.20 notb %dil
+# CHECK-NEXT: 4 13 0.50 * * notb (%r8)
+# CHECK-NEXT: 4 13 0.50 * * lock notb (%r8)
+# CHECK-NEXT: 1 1 0.20 notw %si
+# CHECK-NEXT: 4 12 0.50 * * notw (%r9)
+# CHECK-NEXT: 4 12 0.50 * * lock notw (%r9)
+# CHECK-NEXT: 1 1 0.20 notl %edx
+# CHECK-NEXT: 4 12 0.50 * * notl (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock notl (%rax)
+# CHECK-NEXT: 1 1 0.20 notq %rcx
+# CHECK-NEXT: 4 12 0.50 * * notq (%r10)
+# CHECK-NEXT: 4 12 0.50 * * lock notq (%r10)
+# CHECK-NEXT: 1 2 0.20 orb $7, %al
+# CHECK-NEXT: 1 2 0.20 orb $7, %dil
+# CHECK-NEXT: 4 13 0.50 * * orb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock orb $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 orb %sil, %dil
+# CHECK-NEXT: 4 13 0.50 * * orb %sil, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock orb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * orb (%rax), %dil
+# CHECK-NEXT: 1 1 0.20 orw $511, %ax
+# CHECK-NEXT: 1 1 0.20 orw $511, %di
+# CHECK-NEXT: 4 12 0.50 * * orw $511, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock orw $511, (%rax)
+# CHECK-NEXT: 1 2 0.20 orw $7, %di
+# CHECK-NEXT: 4 12 0.50 * * orw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock orw $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 orw %si, %di
+# CHECK-NEXT: 4 12 0.50 * * orw %si, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock orw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * orw (%rax), %di
+# CHECK-NEXT: 1 2 0.20 orl $665536, %eax
+# CHECK-NEXT: 1 2 0.20 orl $665536, %edi
+# CHECK-NEXT: 4 12 0.50 * * orl $665536, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock orl $665536, (%rax)
+# CHECK-NEXT: 1 2 0.20 orl $7, %edi
+# CHECK-NEXT: 4 12 0.50 * * orl $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock orl $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 orl %esi, %edi
+# CHECK-NEXT: 4 12 0.50 * * orl %esi, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock orl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * orl (%rax), %edi
+# CHECK-NEXT: 1 2 0.20 orq $665536, %rax
+# CHECK-NEXT: 1 2 0.20 orq $665536, %rdi
+# CHECK-NEXT: 4 12 0.50 * * orq $665536, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock orq $665536, (%rax)
+# CHECK-NEXT: 1 2 0.20 orq $7, %rdi
+# CHECK-NEXT: 4 12 0.50 * * orq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock orq $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 orq %rsi, %rdi
+# CHECK-NEXT: 4 12 0.50 * * orq %rsi, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock orq %rsi, (%rax)
+# CHECK-NEXT: 2 7 0.33 * orq (%rax), %rdi
+# CHECK-NEXT: 73 35 15.33 U outb %al, $7
+# CHECK-NEXT: 73 35 15.50 U outb %al, %dx
+# CHECK-NEXT: 79 35 17.00 U outw %ax, $7
+# CHECK-NEXT: 79 35 16.50 U outw %ax, %dx
+# CHECK-NEXT: 85 35 18.33 U outl %eax, $7
+# CHECK-NEXT: 85 35 18.00 U outl %eax, %dx
+# CHECK-NEXT: 80 100 17.00 U outsb (%rsi), %dx
+# CHECK-NEXT: 83 100 18.00 U outsw (%rsi), %dx
+# CHECK-NEXT: 89 100 20.00 U outsl (%rsi), %dx
+# CHECK-NEXT: 2 4 1.00 * * U pause
+# CHECK-NEXT: 3 2 1.00 rclb %dil
+# CHECK-NEXT: 3 2 1.00 rcrb %dil
+# CHECK-NEXT: 6 13 1.00 * rclb (%rax)
+# CHECK-NEXT: 6 13 1.00 * rcrb (%rax)
+# CHECK-NEXT: 3 2 1.00 rclb $7, %dil
+# CHECK-NEXT: 3 2 1.00 rcrb $7, %dil
+# CHECK-NEXT: 6 13 1.00 * rclb $7, (%rax)
+# CHECK-NEXT: 6 13 1.00 * rcrb $7, (%rax)
+# CHECK-NEXT: 9 7 2.50 rclb %cl, %dil
+# CHECK-NEXT: 10 9 3.00 rcrb %cl, %dil
+# CHECK-NEXT: 11 20 2.50 * rclb %cl, (%rax)
+# CHECK-NEXT: 12 20 3.00 * rcrb %cl, (%rax)
+# CHECK-NEXT: 3 2 1.00 rclw %di
+# CHECK-NEXT: 3 2 1.00 rcrw %di
+# CHECK-NEXT: 6 12 1.00 * rclw (%rax)
+# CHECK-NEXT: 6 12 1.00 * rcrw (%rax)
+# CHECK-NEXT: 3 2 1.00 rclw $7, %di
+# CHECK-NEXT: 3 2 1.00 rcrw $7, %di
+# CHECK-NEXT: 6 12 1.00 * rclw $7, (%rax)
+# CHECK-NEXT: 6 12 1.00 * rcrw $7, (%rax)
+# CHECK-NEXT: 7 8 2.00 rclw %cl, %di
+# CHECK-NEXT: 7 8 2.00 rcrw %cl, %di
+# CHECK-NEXT: 10 19 2.00 * rclw %cl, (%rax)
+# CHECK-NEXT: 10 19 2.00 * rcrw %cl, (%rax)
+# CHECK-NEXT: 3 2 1.00 rcll %edi
+# CHECK-NEXT: 3 2 1.00 rcrl %edi
+# CHECK-NEXT: 6 12 1.00 * rcll (%rax)
+# CHECK-NEXT: 6 12 1.00 * rcrl (%rax)
+# CHECK-NEXT: 3 2 1.00 rcll $7, %edi
+# CHECK-NEXT: 3 2 1.00 rcrl $7, %edi
+# CHECK-NEXT: 6 12 1.00 * rcll $7, (%rax)
+# CHECK-NEXT: 6 12 1.00 * rcrl $7, (%rax)
+# CHECK-NEXT: 7 8 2.00 rcll %cl, %edi
+# CHECK-NEXT: 7 8 2.00 rcrl %cl, %edi
+# CHECK-NEXT: 10 19 2.00 * rcll %cl, (%rax)
+# CHECK-NEXT: 10 19 2.00 * rcrl %cl, (%rax)
+# CHECK-NEXT: 3 2 1.00 rclq %rdi
+# CHECK-NEXT: 3 2 1.00 rcrq %rdi
+# CHECK-NEXT: 6 12 1.00 * rclq (%rax)
+# CHECK-NEXT: 6 12 1.00 * rcrq (%rax)
+# CHECK-NEXT: 3 2 1.00 rclq $7, %rdi
+# CHECK-NEXT: 3 2 1.00 rcrq $7, %rdi
+# CHECK-NEXT: 6 12 1.00 * rclq $7, (%rax)
+# CHECK-NEXT: 6 12 1.00 * rcrq $7, (%rax)
+# CHECK-NEXT: 7 8 2.00 rclq %cl, %rdi
+# CHECK-NEXT: 7 8 2.00 rcrq %cl, %rdi
+# CHECK-NEXT: 10 19 2.00 * rclq %cl, (%rax)
+# CHECK-NEXT: 10 19 2.00 * rcrq %cl, (%rax)
+# CHECK-NEXT: 54 100 13.25 U rdmsr
+# CHECK-NEXT: 18 100 3.60 U rdpmc
+# CHECK-NEXT: 15 18 3.00 U rdtsc
+# CHECK-NEXT: 21 42 5.25 U rdtscp
+# CHECK-NEXT: 2 1 1.00 rolb %dil
+# CHECK-NEXT: 2 1 1.00 rorb %dil
+# CHECK-NEXT: 5 13 1.00 * * rolb (%rax)
+# CHECK-NEXT: 5 13 1.00 * * rorb (%rax)
+# CHECK-NEXT: 2 1 1.00 rolb $7, %dil
+# CHECK-NEXT: 2 1 1.00 rorb $7, %dil
+# CHECK-NEXT: 5 13 1.00 * * rolb $7, (%rax)
+# CHECK-NEXT: 5 13 1.00 * * rorb $7, (%rax)
+# CHECK-NEXT: 2 2 1.00 rolb %cl, %dil
+# CHECK-NEXT: 2 2 1.00 rorb %cl, %dil
+# CHECK-NEXT: 5 13 1.00 * * rolb %cl, (%rax)
+# CHECK-NEXT: 5 13 1.00 * * rorb %cl, (%rax)
+# CHECK-NEXT: 2 1 1.00 rolw %di
+# CHECK-NEXT: 2 1 1.00 rorw %di
+# CHECK-NEXT: 5 12 1.00 * * rolw (%rax)
+# CHECK-NEXT: 5 12 1.00 * * rorw (%rax)
+# CHECK-NEXT: 2 1 1.00 rolw $7, %di
+# CHECK-NEXT: 2 1 1.00 rorw $7, %di
+# CHECK-NEXT: 5 12 1.00 * * rolw $7, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * rorw $7, (%rax)
+# CHECK-NEXT: 2 2 1.00 rolw %cl, %di
+# CHECK-NEXT: 2 2 1.00 rorw %cl, %di
+# CHECK-NEXT: 5 12 1.00 * * rolw %cl, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * rorw %cl, (%rax)
+# CHECK-NEXT: 2 1 1.00 roll %edi
+# CHECK-NEXT: 2 1 1.00 rorl %edi
+# CHECK-NEXT: 5 12 1.00 * * roll (%rax)
+# CHECK-NEXT: 5 12 1.00 * * rorl (%rax)
+# CHECK-NEXT: 2 1 1.00 roll $7, %edi
+# CHECK-NEXT: 2 1 1.00 rorl $7, %edi
+# CHECK-NEXT: 5 12 1.00 * * roll $7, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * rorl $7, (%rax)
+# CHECK-NEXT: 2 2 1.00 roll %cl, %edi
+# CHECK-NEXT: 2 2 1.00 rorl %cl, %edi
+# CHECK-NEXT: 5 12 1.00 * * roll %cl, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * rorl %cl, (%rax)
+# CHECK-NEXT: 2 1 1.00 rolq %rdi
+# CHECK-NEXT: 2 1 1.00 rorq %rdi
+# CHECK-NEXT: 5 12 1.00 * * rolq (%rax)
+# CHECK-NEXT: 5 12 1.00 * * rorq (%rax)
+# CHECK-NEXT: 2 1 1.00 rolq $7, %rdi
+# CHECK-NEXT: 2 1 1.00 rorq $7, %rdi
+# CHECK-NEXT: 5 12 1.00 * * rolq $7, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * rorq $7, (%rax)
+# CHECK-NEXT: 2 2 1.00 rolq %cl, %rdi
+# CHECK-NEXT: 2 2 1.00 rorq %cl, %rdi
+# CHECK-NEXT: 5 12 1.00 * * rolq %cl, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * rorq %cl, (%rax)
+# CHECK-NEXT: 2 4 1.00 sahf
+# CHECK-NEXT: 1 1 0.50 sarb %dil
+# CHECK-NEXT: 1 1 0.50 shlb %dil
+# CHECK-NEXT: 1 1 0.50 shrb %dil
+# CHECK-NEXT: 4 13 0.50 * * sarb (%rax)
+# CHECK-NEXT: 4 13 0.50 * * shlb (%rax)
+# CHECK-NEXT: 4 13 0.50 * * shrb (%rax)
+# CHECK-NEXT: 1 1 0.50 sarb $7, %dil
+# CHECK-NEXT: 1 1 0.50 shlb $7, %dil
+# CHECK-NEXT: 1 1 0.50 shrb $7, %dil
+# CHECK-NEXT: 4 13 0.50 * * sarb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * shlb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * shrb $7, (%rax)
+# CHECK-NEXT: 2 2 1.00 sarb %cl, %dil
+# CHECK-NEXT: 2 2 1.00 shlb %cl, %dil
+# CHECK-NEXT: 2 2 1.00 shrb %cl, %dil
+# CHECK-NEXT: 5 13 1.00 * * sarb %cl, (%rax)
+# CHECK-NEXT: 5 13 1.00 * * shlb %cl, (%rax)
+# CHECK-NEXT: 5 13 1.00 * * shrb %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 sarw %di
+# CHECK-NEXT: 1 1 0.50 shlw %di
+# CHECK-NEXT: 1 1 0.50 shrw %di
+# CHECK-NEXT: 4 12 0.50 * * sarw (%rax)
+# CHECK-NEXT: 4 12 0.50 * * shlw (%rax)
+# CHECK-NEXT: 4 12 0.50 * * shrw (%rax)
+# CHECK-NEXT: 1 1 0.50 sarw $7, %di
+# CHECK-NEXT: 1 1 0.50 shlw $7, %di
+# CHECK-NEXT: 1 1 0.50 shrw $7, %di
+# CHECK-NEXT: 4 12 0.50 * * sarw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * shlw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * shrw $7, (%rax)
+# CHECK-NEXT: 2 2 1.00 sarw %cl, %di
+# CHECK-NEXT: 2 2 1.00 shlw %cl, %di
+# CHECK-NEXT: 2 2 1.00 shrw %cl, %di
+# CHECK-NEXT: 5 12 1.00 * * sarw %cl, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * shlw %cl, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * shrw %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 sarl %edi
+# CHECK-NEXT: 1 1 0.50 shll %edi
+# CHECK-NEXT: 1 1 0.50 shrl %edi
+# CHECK-NEXT: 4 12 0.50 * * sarl (%rax)
+# CHECK-NEXT: 4 12 0.50 * * shll (%rax)
+# CHECK-NEXT: 4 12 0.50 * * shrl (%rax)
+# CHECK-NEXT: 1 1 0.50 sarl $7, %edi
+# CHECK-NEXT: 1 1 0.50 shll $7, %edi
+# CHECK-NEXT: 1 1 0.50 shrl $7, %edi
+# CHECK-NEXT: 4 12 0.50 * * sarl $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * shll $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * shrl $7, (%rax)
+# CHECK-NEXT: 2 2 1.00 sarl %cl, %edi
+# CHECK-NEXT: 2 2 1.00 shll %cl, %edi
+# CHECK-NEXT: 2 2 1.00 shrl %cl, %edi
+# CHECK-NEXT: 5 12 1.00 * * sarl %cl, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * shll %cl, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * shrl %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 sarq %rdi
+# CHECK-NEXT: 1 1 0.50 shlq %rdi
+# CHECK-NEXT: 1 1 0.50 shrq %rdi
+# CHECK-NEXT: 4 12 0.50 * * sarq (%rax)
+# CHECK-NEXT: 4 12 0.50 * * shlq (%rax)
+# CHECK-NEXT: 4 12 0.50 * * shrq (%rax)
+# CHECK-NEXT: 1 1 0.50 sarq $7, %rdi
+# CHECK-NEXT: 1 1 0.50 shlq $7, %rdi
+# CHECK-NEXT: 1 1 0.50 shrq $7, %rdi
+# CHECK-NEXT: 4 12 0.50 * * sarq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * shlq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * shrq $7, (%rax)
+# CHECK-NEXT: 2 2 1.00 sarq %cl, %rdi
+# CHECK-NEXT: 2 2 1.00 shlq %cl, %rdi
+# CHECK-NEXT: 2 2 1.00 shrq %cl, %rdi
+# CHECK-NEXT: 5 12 1.00 * * sarq %cl, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * shlq %cl, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * shrq %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 sbbb $0, %al
+# CHECK-NEXT: 1 1 0.50 sbbb $0, %dil
+# CHECK-NEXT: 5 13 0.50 * * sbbb $0, (%rax)
+# CHECK-NEXT: 5 13 0.50 * * lock sbbb $0, (%rax)
+# CHECK-NEXT: 1 1 0.50 sbbb $7, %al
+# CHECK-NEXT: 1 1 0.50 sbbb $7, %dil
+# CHECK-NEXT: 5 13 0.50 * * sbbb $7, (%rax)
+# CHECK-NEXT: 5 13 0.50 * * lock sbbb $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 sbbb %sil, %dil
+# CHECK-NEXT: 6 13 0.60 * * sbbb %sil, (%rax)
+# CHECK-NEXT: 6 13 0.60 * * lock sbbb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.50 * sbbb (%rax), %dil
+# CHECK-NEXT: 1 1 0.50 sbbw $0, %ax
+# CHECK-NEXT: 1 1 0.50 sbbw $0, %di
+# CHECK-NEXT: 5 12 0.50 * * sbbw $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbw $0, (%rax)
+# CHECK-NEXT: 1 1 0.50 sbbw $511, %ax
+# CHECK-NEXT: 1 1 0.50 sbbw $511, %di
+# CHECK-NEXT: 5 12 0.50 * * sbbw $511, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbw $511, (%rax)
+# CHECK-NEXT: 1 1 0.50 sbbw $7, %di
+# CHECK-NEXT: 5 12 0.50 * * sbbw $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbw $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 sbbw %si, %di
+# CHECK-NEXT: 6 12 0.60 * * sbbw %si, (%rax)
+# CHECK-NEXT: 6 12 0.60 * * lock sbbw %si, (%rax)
+# CHECK-NEXT: 2 6 0.50 * sbbw (%rax), %di
+# CHECK-NEXT: 1 1 0.50 sbbl $0, %eax
+# CHECK-NEXT: 1 1 0.50 sbbl $0, %edi
+# CHECK-NEXT: 5 12 0.50 * * sbbl $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbl $0, (%rax)
+# CHECK-NEXT: 1 1 0.50 sbbl $665536, %eax
+# CHECK-NEXT: 1 1 0.50 sbbl $665536, %edi
+# CHECK-NEXT: 5 12 0.50 * * sbbl $665536, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.50 sbbl $7, %edi
+# CHECK-NEXT: 5 12 0.50 * * sbbl $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbl $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 sbbl %esi, %edi
+# CHECK-NEXT: 6 12 0.60 * * sbbl %esi, (%rax)
+# CHECK-NEXT: 6 12 0.60 * * lock sbbl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.50 * sbbl (%rax), %edi
+# CHECK-NEXT: 1 1 0.50 sbbq $0, %rax
+# CHECK-NEXT: 1 1 0.50 sbbq $0, %rdi
+# CHECK-NEXT: 5 12 0.50 * * sbbq $0, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbq $0, (%rax)
+# CHECK-NEXT: 1 1 0.50 sbbq $665536, %rax
+# CHECK-NEXT: 1 1 0.50 sbbq $665536, %rdi
+# CHECK-NEXT: 5 12 0.50 * * sbbq $665536, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.50 sbbq $7, %rdi
+# CHECK-NEXT: 5 12 0.50 * * sbbq $7, (%rax)
+# CHECK-NEXT: 5 12 0.50 * * lock sbbq $7, (%rax)
+# CHECK-NEXT: 1 1 0.50 sbbq %rsi, %rdi
+# CHECK-NEXT: 6 12 0.60 * * sbbq %rsi, (%rax)
+# CHECK-NEXT: 6 12 0.60 * * lock sbbq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.50 * sbbq (%rax), %rdi
+# CHECK-NEXT: 4 6 0.60 U scasb %es:(%rdi), %al
+# CHECK-NEXT: 4 6 0.60 U scasw %es:(%rdi), %ax
+# CHECK-NEXT: 4 6 0.60 U scasl %es:(%rdi), %eax
+# CHECK-NEXT: 4 6 0.60 U scasq %es:(%rdi), %rax
+# CHECK-NEXT: 2 2 1.00 seto %al
+# CHECK-NEXT: 4 13 1.00 * seto (%rax)
+# CHECK-NEXT: 2 2 1.00 setno %al
+# CHECK-NEXT: 4 13 1.00 * setno (%rax)
+# CHECK-NEXT: 2 2 1.00 setb %al
+# CHECK-NEXT: 4 13 1.00 * setb (%rax)
+# CHECK-NEXT: 2 2 1.00 setae %al
+# CHECK-NEXT: 4 13 1.00 * setae (%rax)
+# CHECK-NEXT: 2 2 1.00 sete %al
+# CHECK-NEXT: 4 13 1.00 * sete (%rax)
+# CHECK-NEXT: 2 2 1.00 setne %al
+# CHECK-NEXT: 4 13 1.00 * setne (%rax)
+# CHECK-NEXT: 2 2 1.00 seta %al
+# CHECK-NEXT: 4 13 1.00 * seta (%rax)
+# CHECK-NEXT: 2 2 1.00 setbe %al
+# CHECK-NEXT: 4 13 1.00 * setbe (%rax)
+# CHECK-NEXT: 2 2 1.00 sets %al
+# CHECK-NEXT: 4 13 1.00 * sets (%rax)
+# CHECK-NEXT: 2 2 1.00 setns %al
+# CHECK-NEXT: 4 13 1.00 * setns (%rax)
+# CHECK-NEXT: 2 2 1.00 setp %al
+# CHECK-NEXT: 4 13 1.00 * setp (%rax)
+# CHECK-NEXT: 2 2 1.00 setnp %al
+# CHECK-NEXT: 4 13 1.00 * setnp (%rax)
+# CHECK-NEXT: 2 2 1.00 setl %al
+# CHECK-NEXT: 4 13 1.00 * setl (%rax)
+# CHECK-NEXT: 2 2 1.00 setge %al
+# CHECK-NEXT: 4 13 1.00 * setge (%rax)
+# CHECK-NEXT: 2 2 1.00 setg %al
+# CHECK-NEXT: 4 13 1.00 * setg (%rax)
+# CHECK-NEXT: 2 2 1.00 setle %al
+# CHECK-NEXT: 4 13 1.00 * setle (%rax)
+# CHECK-NEXT: 3 5 1.00 shldw %cl, %si, %di
+# CHECK-NEXT: 3 5 1.00 shrdw %cl, %si, %di
+# CHECK-NEXT: 6 12 1.00 * * shldw %cl, %si, (%rax)
+# CHECK-NEXT: 6 12 1.00 * * shrdw %cl, %si, (%rax)
+# CHECK-NEXT: 1 3 1.00 shldw $7, %si, %di
+# CHECK-NEXT: 1 3 1.00 shrdw $7, %si, %di
+# CHECK-NEXT: 5 12 1.00 * * shldw $7, %si, (%rax)
+# CHECK-NEXT: 5 13 1.00 * * shrdw $7, %si, (%rax)
+# CHECK-NEXT: 3 5 1.00 shldl %cl, %esi, %edi
+# CHECK-NEXT: 3 5 1.00 shrdl %cl, %esi, %edi
+# CHECK-NEXT: 6 12 1.00 * * shldl %cl, %esi, (%rax)
+# CHECK-NEXT: 6 12 1.00 * * shrdl %cl, %esi, (%rax)
+# CHECK-NEXT: 1 3 1.00 shldl $7, %esi, %edi
+# CHECK-NEXT: 1 3 1.00 shrdl $7, %esi, %edi
+# CHECK-NEXT: 5 12 1.00 * * shldl $7, %esi, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * shrdl $7, %esi, (%rax)
+# CHECK-NEXT: 3 5 1.00 shldq %cl, %rsi, %rdi
+# CHECK-NEXT: 3 5 1.00 shrdq %cl, %rsi, %rdi
+# CHECK-NEXT: 6 12 1.00 * * shldq %cl, %rsi, (%rax)
+# CHECK-NEXT: 6 12 1.00 * * shrdq %cl, %rsi, (%rax)
+# CHECK-NEXT: 1 3 1.00 shldq $7, %rsi, %rdi
+# CHECK-NEXT: 1 3 1.00 shrdq $7, %rsi, %rdi
+# CHECK-NEXT: 5 12 1.00 * * shldq $7, %rsi, (%rax)
+# CHECK-NEXT: 5 12 1.00 * * shrdq $7, %rsi, (%rax)
+# CHECK-NEXT: 1 1 0.20 U stc
+# CHECK-NEXT: 2 6 0.50 U std
+# CHECK-NEXT: 4 8 0.50 U stosb %al, %es:(%rdi)
+# CHECK-NEXT: 4 7 0.50 U stosw %ax, %es:(%rdi)
+# CHECK-NEXT: 4 7 0.50 U stosl %eax, %es:(%rdi)
+# CHECK-NEXT: 4 7 0.50 U stosq %rax, %es:(%rdi)
+# CHECK-NEXT: 1 1 0.20 subb $7, %al
+# CHECK-NEXT: 1 1 0.20 subb $7, %dil
+# CHECK-NEXT: 4 13 0.50 * * subb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock subb $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 subb %sil, %dil
+# CHECK-NEXT: 4 13 0.50 * * subb %sil, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock subb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * subb (%rax), %dil
+# CHECK-NEXT: 1 1 0.20 subw $511, %ax
+# CHECK-NEXT: 1 1 0.20 subw $511, %di
+# CHECK-NEXT: 4 12 0.50 * * subw $511, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock subw $511, (%rax)
+# CHECK-NEXT: 1 1 0.20 subw $7, %di
+# CHECK-NEXT: 4 12 0.50 * * subw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock subw $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 subw %si, %di
+# CHECK-NEXT: 4 12 0.50 * * subw %si, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock subw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * subw (%rax), %di
+# CHECK-NEXT: 1 1 0.20 subl $665536, %eax
+# CHECK-NEXT: 1 1 0.20 subl $665536, %edi
+# CHECK-NEXT: 4 12 0.50 * * subl $665536, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock subl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 subl $7, %edi
+# CHECK-NEXT: 4 12 0.50 * * subl $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock subl $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 subl %esi, %edi
+# CHECK-NEXT: 4 12 0.50 * * subl %esi, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock subl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * subl (%rax), %edi
+# CHECK-NEXT: 1 1 0.20 subq $665536, %rax
+# CHECK-NEXT: 1 1 0.20 subq $665536, %rdi
+# CHECK-NEXT: 4 12 0.50 * * subq $665536, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock subq $665536, (%rax)
+# CHECK-NEXT: 0 1 0.00 subq $7, %rdi
+# CHECK-NEXT: 4 12 0.50 * * subq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock subq $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 subq %rsi, %rdi
+# CHECK-NEXT: 4 12 0.50 * * subq %rsi, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock subq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * subq (%rax), %rdi
+# CHECK-NEXT: 1 2 0.20 testb $7, %al
+# CHECK-NEXT: 1 2 0.20 testb $7, %dil
+# CHECK-NEXT: 2 7 0.33 * testb $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 testb %sil, %dil
+# CHECK-NEXT: 2 7 0.33 * testb %sil, (%rax)
+# CHECK-NEXT: 1 1 0.20 testw $511, %ax
+# CHECK-NEXT: 1 1 0.20 testw $511, %di
+# CHECK-NEXT: 2 7 0.33 * testw $511, (%rax)
+# CHECK-NEXT: 1 1 0.20 testw $7, %di
+# CHECK-NEXT: 2 7 0.33 * testw $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 testw %si, %di
+# CHECK-NEXT: 2 7 0.33 * testw %si, (%rax)
+# CHECK-NEXT: 1 2 0.20 testl $665536, %eax
+# CHECK-NEXT: 1 2 0.20 testl $665536, %edi
+# CHECK-NEXT: 2 7 0.33 * testl $665536, (%rax)
+# CHECK-NEXT: 1 2 0.20 testl $7, %edi
+# CHECK-NEXT: 2 7 0.33 * testl $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 testl %esi, %edi
+# CHECK-NEXT: 2 7 0.33 * testl %esi, (%rax)
+# CHECK-NEXT: 1 2 0.20 testq $665536, %rax
+# CHECK-NEXT: 1 2 0.20 testq $665536, %rdi
+# CHECK-NEXT: 2 7 0.33 * testq $665536, (%rax)
+# CHECK-NEXT: 1 2 0.20 testq $7, %rdi
+# CHECK-NEXT: 2 7 0.33 * testq $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 testq %rsi, %rdi
+# CHECK-NEXT: 2 7 0.33 * testq %rsi, (%rax)
+# CHECK-NEXT: 1 100 0.25 * U ud2
+# CHECK-NEXT: 144 100 35.50 U wrmsr
+# CHECK-NEXT: 3 2 0.60 xaddb %bl, %cl
+# CHECK-NEXT: 5 13 0.50 * * xaddb %bl, (%rcx)
+# CHECK-NEXT: 5 13 0.50 * * lock xaddb %bl, (%rcx)
+# CHECK-NEXT: 3 2 0.60 xaddw %bx, %cx
+# CHECK-NEXT: 5 12 0.50 * * xaddw %ax, (%rbx)
+# CHECK-NEXT: 5 12 0.50 * * lock xaddw %ax, (%rbx)
+# CHECK-NEXT: 3 2 0.60 xaddl %ebx, %ecx
+# CHECK-NEXT: 5 12 0.50 * * xaddl %eax, (%rbx)
+# CHECK-NEXT: 5 12 0.50 * * lock xaddl %eax, (%rbx)
+# CHECK-NEXT: 3 2 0.60 xaddq %rbx, %rcx
+# CHECK-NEXT: 5 12 0.50 * * xaddq %rax, (%rbx)
+# CHECK-NEXT: 5 12 0.50 * * lock xaddq %rax, (%rbx)
+# CHECK-NEXT: 3 2 0.60 xchgb %bl, %cl
+# CHECK-NEXT: 8 40 1.00 * * xchgb %bl, (%rbx)
+# CHECK-NEXT: 8 40 1.00 * * lock xchgb %bl, (%rbx)
+# CHECK-NEXT: 3 2 0.60 xchgw %bx, %ax
+# CHECK-NEXT: 3 2 0.60 xchgw %bx, %cx
+# CHECK-NEXT: 8 39 1.00 * * xchgw %ax, (%rbx)
+# CHECK-NEXT: 8 39 1.00 * * lock xchgw %ax, (%rbx)
+# CHECK-NEXT: 3 2 0.60 xchgl %ebx, %eax
+# CHECK-NEXT: 3 2 0.60 xchgl %ebx, %ecx
+# CHECK-NEXT: 8 39 1.00 * * xchgl %eax, (%rbx)
+# CHECK-NEXT: 8 39 1.00 * * lock xchgl %eax, (%rbx)
+# CHECK-NEXT: 3 2 0.60 xchgq %rbx, %rax
+# CHECK-NEXT: 3 2 0.60 xchgq %rbx, %rcx
+# CHECK-NEXT: 9 39 1.20 * * xchgq %rax, (%rbx)
+# CHECK-NEXT: 9 39 1.20 * * lock xchgq %rax, (%rbx)
+# CHECK-NEXT: 3 7 0.40 * xlatb
+# CHECK-NEXT: 1 2 0.20 xorb $7, %al
+# CHECK-NEXT: 1 2 0.20 xorb $7, %dil
+# CHECK-NEXT: 4 13 0.50 * * xorb $7, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock xorb $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 xorb %sil, %dil
+# CHECK-NEXT: 4 13 0.50 * * xorb %sil, (%rax)
+# CHECK-NEXT: 4 13 0.50 * * lock xorb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.33 * xorb (%rax), %dil
+# CHECK-NEXT: 1 1 0.20 xorw $511, %ax
+# CHECK-NEXT: 1 1 0.20 xorw $511, %di
+# CHECK-NEXT: 4 12 0.50 * * xorw $511, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock xorw $511, (%rax)
+# CHECK-NEXT: 1 2 0.20 xorw $7, %di
+# CHECK-NEXT: 4 12 0.50 * * xorw $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock xorw $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 xorw %si, %di
+# CHECK-NEXT: 4 12 0.50 * * xorw %si, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock xorw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * xorw (%rax), %di
+# CHECK-NEXT: 1 2 0.20 xorl $665536, %eax
+# CHECK-NEXT: 1 2 0.20 xorl $665536, %edi
+# CHECK-NEXT: 4 12 0.50 * * xorl $665536, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock xorl $665536, (%rax)
+# CHECK-NEXT: 1 2 0.20 xorl $7, %edi
+# CHECK-NEXT: 4 12 0.50 * * xorl $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock xorl $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 xorl %esi, %edi
+# CHECK-NEXT: 4 12 0.50 * * xorl %esi, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock xorl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * xorl (%rax), %edi
+# CHECK-NEXT: 1 2 0.20 xorq $665536, %rax
+# CHECK-NEXT: 1 2 0.20 xorq $665536, %rdi
+# CHECK-NEXT: 4 12 0.50 * * xorq $665536, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock xorq $665536, (%rax)
+# CHECK-NEXT: 1 2 0.20 xorq $7, %rdi
+# CHECK-NEXT: 4 12 0.50 * * xorq $7, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock xorq $7, (%rax)
+# CHECK-NEXT: 1 2 0.20 xorq %rsi, %rdi
+# CHECK-NEXT: 4 12 0.50 * * xorq %rsi, (%rax)
+# CHECK-NEXT: 4 12 0.50 * * lock xorq %rsi, (%rax)
+# CHECK-NEXT: 2 7 0.33 * xorq (%rax), %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 939.92 789.58 213.00 213.00 202.50 597.75 783.42 203.00 203.00 202.50 189.33 213.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcb $0, %al
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcb $0, %dil
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - adcb $0, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock adcb $0, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcb $7, %al
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcb $7, %dil
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - adcb $7, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock adcb $7, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcb %sil, %dil
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - adcb %sil, (%rax)
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - lock adcb %sil, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - adcb (%rax), %dil
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcw $0, %ax
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcw $0, %di
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - adcw $0, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock adcw $0, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcw $511, %ax
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcw $511, %di
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - adcw $511, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock adcw $511, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcw $7, %di
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - adcw $7, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock adcw $7, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcw %si, %di
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - adcw %si, (%rax)
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - lock adcw %si, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - adcw (%rax), %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcl $0, %eax
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcl $0, %edi
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - adcl $0, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock adcl $0, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcl $665536, %eax
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcl $665536, %edi
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - adcl $665536, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock adcl $665536, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcl $7, %edi
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - adcl $7, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock adcl $7, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcl %esi, %edi
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - adcl %esi, (%rax)
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - lock adcl %esi, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - adcl (%rax), %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcq $0, %rax
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcq $0, %rdi
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - adcq $0, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock adcq $0, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcq $665536, %rax
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcq $665536, %rdi
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - adcq $665536, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock adcq $665536, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcq $7, %rdi
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - adcq $7, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock adcq $7, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - adcq %rsi, %rdi
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - adcq %rsi, (%rax)
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - lock adcq %rsi, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - adcq (%rax), %rdi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addb $7, %al
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addb $7, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addb $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addb $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addb %sil, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addb %sil, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addb %sil, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - addb (%rax), %dil
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addw $511, %ax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addw $511, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addw $511, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addw $511, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addw $7, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addw $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addw $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addw %si, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addw %si, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addw %si, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - addw (%rax), %di
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addl $665536, %eax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addl $665536, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addl $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addl $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addl $7, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addl $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addl $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addl %esi, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addl %esi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addl %esi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - addl (%rax), %edi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addq $665536, %rax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addq $665536, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addq $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addq $665536, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - addq $7, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addq $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addq $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addq %rsi, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addq %rsi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addq %rsi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - addq (%rax), %rdi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andb $7, %al
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andb $7, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - andb $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock andb $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andb %sil, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - andb %sil, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock andb %sil, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - andb (%rax), %dil
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andw $511, %ax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andw $511, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - andw $511, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock andw $511, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andw $7, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - andw $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock andw $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andw %si, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - andw %si, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock andw %si, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - andw (%rax), %di
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andl $665536, %eax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andl $665536, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - andl $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock andl $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andl $7, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - andl $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock andl $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andl %esi, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - andl %esi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock andl %esi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - andl (%rax), %edi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andq $665536, %rax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andq $665536, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - andq $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock andq $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andq $7, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - andq $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock andq $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - andq %rsi, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - andq %rsi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock andq %rsi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - andq (%rax), %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - bsfw %si, %di
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - bsrw %si, %di
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - bsfw (%rax), %di
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - bsrw (%rax), %di
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - bsfl %esi, %edi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - bsrl %esi, %edi
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - bsfl (%rax), %edi
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - bsrl (%rax), %edi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - bsfq %rsi, %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - bsrq %rsi, %rdi
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - bsfq (%rax), %rdi
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - bsrq (%rax), %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - bswapl %eax
+# CHECK-NEXT: 0.50 1.00 - - - - 0.50 - - - - - - bswapq %rax
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btw %si, %di
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btcw %si, %di
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btrw %si, %di
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btsw %si, %di
+# CHECK-NEXT: 1.80 2.47 0.33 0.33 - 1.47 1.80 - - - 1.47 0.33 - btw %si, (%rax)
+# CHECK-NEXT: 1.60 2.27 0.33 0.33 0.50 1.27 1.60 0.50 0.50 0.50 1.27 0.33 - btcw %si, (%rax)
+# CHECK-NEXT: 1.60 2.27 0.33 0.33 0.50 1.27 1.60 0.50 0.50 0.50 1.27 0.33 - btrw %si, (%rax)
+# CHECK-NEXT: 1.60 2.27 0.33 0.33 0.50 1.27 1.60 0.50 0.50 0.50 1.27 0.33 - btsw %si, (%rax)
+# CHECK-NEXT: 1.60 2.27 0.33 0.33 0.50 1.27 1.60 0.50 0.50 0.50 1.27 0.33 - lock btcw %si, (%rax)
+# CHECK-NEXT: 1.60 2.27 0.33 0.33 0.50 1.27 1.60 0.50 0.50 0.50 1.27 0.33 - lock btrw %si, (%rax)
+# CHECK-NEXT: 1.60 2.27 0.33 0.33 0.50 1.27 1.60 0.50 0.50 0.50 1.27 0.33 - lock btsw %si, (%rax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btw $7, %di
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btcw $7, %di
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btrw $7, %di
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btsw $7, %di
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - btw $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - btcw $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - btrw $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - btsw $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - lock btcw $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - lock btrw $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - lock btsw $7, (%rax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btl %esi, %edi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btcl %esi, %edi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btrl %esi, %edi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btsl %esi, %edi
+# CHECK-NEXT: 1.80 2.47 0.33 0.33 - 1.47 1.80 - - - 1.47 0.33 - btl %esi, (%rax)
+# CHECK-NEXT: 1.60 2.27 0.33 0.33 0.50 1.27 1.60 0.50 0.50 0.50 1.27 0.33 - btcl %esi, (%rax)
+# CHECK-NEXT: 1.60 2.27 0.33 0.33 0.50 1.27 1.60 0.50 0.50 0.50 1.27 0.33 - btrl %esi, (%rax)
+# CHECK-NEXT: 1.60 2.27 0.33 0.33 0.50 1.27 1.60 0.50 0.50 0.50 1.27 0.33 - btsl %esi, (%rax)
+# CHECK-NEXT: 1.60 2.27 0.33 0.33 0.50 1.27 1.60 0.50 0.50 0.50 1.27 0.33 - lock btcl %esi, (%rax)
+# CHECK-NEXT: 1.60 2.27 0.33 0.33 0.50 1.27 1.60 0.50 0.50 0.50 1.27 0.33 - lock btrl %esi, (%rax)
+# CHECK-NEXT: 1.60 2.27 0.33 0.33 0.50 1.27 1.60 0.50 0.50 0.50 1.27 0.33 - lock btsl %esi, (%rax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btl $7, %edi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btcl $7, %edi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btrl $7, %edi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btsl $7, %edi
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - btl $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - btcl $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - btrl $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - btsl $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - lock btcl $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - lock btrl $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - lock btsl $7, (%rax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btq %rsi, %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btcq %rsi, %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btrq %rsi, %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btsq %rsi, %rdi
+# CHECK-NEXT: 2.00 2.00 0.33 0.33 - 1.00 2.00 - - - 1.00 0.33 - btq %rsi, (%rax)
+# CHECK-NEXT: 1.80 1.80 0.33 0.33 0.50 0.80 1.80 0.50 0.50 0.50 0.80 0.33 - btcq %rsi, (%rax)
+# CHECK-NEXT: 1.80 1.80 0.33 0.33 0.50 0.80 1.80 0.50 0.50 0.50 0.80 0.33 - btrq %rsi, (%rax)
+# CHECK-NEXT: 1.80 1.80 0.33 0.33 0.50 0.80 1.80 0.50 0.50 0.50 0.80 0.33 - btsq %rsi, (%rax)
+# CHECK-NEXT: 1.80 1.80 0.33 0.33 0.50 0.80 1.80 0.50 0.50 0.50 0.80 0.33 - lock btcq %rsi, (%rax)
+# CHECK-NEXT: 1.80 1.80 0.33 0.33 0.50 0.80 1.80 0.50 0.50 0.50 0.80 0.33 - lock btrq %rsi, (%rax)
+# CHECK-NEXT: 1.80 1.80 0.33 0.33 0.50 0.80 1.80 0.50 0.50 0.50 0.80 0.33 - lock btsq %rsi, (%rax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btq $7, %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btcq $7, %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btrq $7, %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - btsq $7, %rdi
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - btq $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - btcq $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - btrq $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - btsq $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - lock btcq $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - lock btrq $7, (%rax)
+# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - lock btsq $7, (%rax)
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - cbtw
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - cwtl
+# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - cltq
+# CHECK-NEXT: 0.70 0.20 - - - 0.20 0.70 - - - 0.20 - - cwtd
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cltd
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cqto
+# CHECK-NEXT: - - - - - - - - - - - - - clc
+# CHECK-NEXT: 0.70 0.20 - - - 0.20 0.70 - - - 0.20 - - cld
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmc
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpb $7, %al
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpb $7, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpb $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpb %sil, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpb %sil, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpb (%rax), %dil
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpw $511, %ax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpw $511, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpw $511, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpw $7, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpw $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpw %si, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpw %si, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpw (%rax), %di
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpl $665536, %eax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpl $665536, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpl $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpl $7, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpl $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpl %esi, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpl %esi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpl (%rax), %edi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpq $665536, %rax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpq $665536, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpq $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpq $7, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpq $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - cmpq %rsi, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpq %rsi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - cmpq (%rax), %rdi
+# CHECK-NEXT: 1.00 1.00 0.67 0.67 - 1.00 1.00 - - - 1.00 0.67 - cmpsb %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1.00 1.00 0.67 0.67 - 1.00 1.00 - - - 1.00 0.67 - cmpsw %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1.00 1.00 0.67 0.67 - 1.00 1.00 - - - 1.00 0.67 - cmpsl %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1.00 1.00 0.67 0.67 - 1.00 1.00 - - - 1.00 0.67 - cmpsq %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1.60 0.60 - - - 0.60 1.60 - - - 0.60 - - cmpxchgb %cl, %bl
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - lock cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 1.60 0.60 - - - 0.60 1.60 - - - 0.60 - - cmpxchgw %cx, %bx
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - lock cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: 1.60 0.60 - - - 0.60 1.60 - - - 0.60 - - cmpxchgl %ecx, %ebx
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - lock cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: 1.60 0.60 - - - 0.60 1.60 - - - 0.60 - - cmpxchgq %rcx, %rbx
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - lock cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: 7.50 6.50 - - 0.50 5.00 5.00 0.50 0.50 0.50 - - - cpuid
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - decb %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - decb (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock decb (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - decw %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - decw (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock decw (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - decl %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - decl (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock decl (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - decq %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - decq (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock decq (%rax)
+# CHECK-NEXT: - 3.00 - - - - - - - - - - - divb %dil
+# CHECK-NEXT: - 3.00 - - - - - - - - - - - divb (%rax)
+# CHECK-NEXT: 0.20 3.20 - - - 0.20 0.20 - - - 0.20 - - divw %si
+# CHECK-NEXT: 0.20 3.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - divw (%rax)
+# CHECK-NEXT: 0.20 3.20 - - - 0.20 0.20 - - - 0.20 - - divl %edx
+# CHECK-NEXT: 0.20 3.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - divl (%rax)
+# CHECK-NEXT: - 3.00 - - - - - - - - - - - divq %rcx
+# CHECK-NEXT: - 3.00 0.33 0.33 - - - - - - - 0.33 - divq (%rax)
+# CHECK-NEXT: 12.50 2.00 4.67 4.67 2.00 9.00 10.50 2.50 2.50 2.00 - 4.67 - enter $7, $4095
+# CHECK-NEXT: - 3.00 - - - - - - - - - - - idivb %dil
+# CHECK-NEXT: - 3.00 - - - - - - - - - - - idivb (%rax)
+# CHECK-NEXT: 0.20 3.20 - - - 0.20 0.20 - - - 0.20 - - idivw %si
+# CHECK-NEXT: 0.20 3.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - idivw (%rax)
+# CHECK-NEXT: 0.20 3.20 - - - 0.20 0.20 - - - 0.20 - - idivl %edx
+# CHECK-NEXT: 0.20 3.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - idivl (%rax)
+# CHECK-NEXT: - 3.00 - - - - - - - - - - - idivq %rcx
+# CHECK-NEXT: - 3.00 0.33 0.33 - - - - - - - 0.33 - idivq (%rax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - imulb %dil
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - imulb (%rax)
+# CHECK-NEXT: 0.90 1.40 - - - 0.40 0.90 - - - 0.40 - - imulw %di
+# CHECK-NEXT: 0.90 1.40 0.33 0.33 - 0.40 0.90 - - - 0.40 0.33 - imulw (%rax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - imulw %si, %di
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - imulw (%rax), %di
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - imulw $511, %si, %di
+# CHECK-NEXT: 0.20 1.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - imulw $511, (%rax), %di
+# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - imulw $7, %si, %di
+# CHECK-NEXT: 0.20 1.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - imulw $7, (%rax), %di
+# CHECK-NEXT: 0.70 1.20 - - - 0.20 0.70 - - - 0.20 - - imull %edi
+# CHECK-NEXT: 0.70 1.20 0.33 0.33 - 0.20 0.70 - - - 0.20 0.33 - imull (%rax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - imull %esi, %edi
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - imull (%rax), %edi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - imull $665536, %esi, %edi
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - imull $665536, (%rax), %edi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - imull $7, %esi, %edi
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - imull $7, (%rax), %edi
+# CHECK-NEXT: - 1.00 - - - 1.00 - - - - - - - imulq %rdi
+# CHECK-NEXT: - 1.00 0.33 0.33 - 1.00 - - - - - 0.33 - imulq (%rax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - imulq %rsi, %rdi
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - imulq (%rax), %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - imulq $665536, %rsi, %rdi
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - imulq $665536, (%rax), %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - imulq $7, %rsi, %rdi
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - imulq $7, (%rax), %rdi
+# CHECK-NEXT: 20.70 20.87 2.67 2.67 - 21.87 13.70 - - - 1.87 2.67 - inb $7, %al
+# CHECK-NEXT: 20.70 20.87 2.33 2.33 - 21.87 13.70 - - - 1.87 2.33 - inb %dx, %al
+# CHECK-NEXT: 21.00 20.67 2.33 2.33 - 22.67 14.00 - - - 1.67 2.33 - inw $7, %ax
+# CHECK-NEXT: 21.30 21.30 2.33 2.33 - 21.80 13.80 - - - 1.80 2.33 - inw %dx, %ax
+# CHECK-NEXT: 22.20 22.87 3.33 3.33 - 21.87 15.20 - - - 1.87 3.33 - inl $7, %eax
+# CHECK-NEXT: 22.80 23.47 3.67 3.67 - 23.47 15.80 - - - 2.47 3.67 - inl %dx, %eax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - incb %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - incb (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock incb (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - incw %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - incw (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock incw (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - incl %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - incl (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock incl (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - incq %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - incq (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock incq (%rax)
+# CHECK-NEXT: 20.20 18.20 2.67 2.67 0.50 20.20 13.20 0.50 0.50 0.50 1.20 2.67 - insb %dx, %es:(%rdi)
+# CHECK-NEXT: 20.97 18.47 3.00 3.00 0.50 20.80 13.63 0.50 0.50 0.50 1.13 3.00 - insw %dx, %es:(%rdi)
+# CHECK-NEXT: 22.17 18.33 3.67 3.67 0.50 22.67 14.83 0.50 0.50 0.50 1.00 3.67 - insl %dx, %es:(%rdi)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - int $7
+# CHECK-NEXT: 9.80 7.47 - - 2.50 8.47 4.80 2.50 2.50 2.50 1.47 - - invlpg (%rax)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - invlpga
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - lahf
+# CHECK-NEXT: 0.40 0.40 0.33 0.33 - 0.40 0.40 - - - 0.40 0.33 - leave
+# CHECK-NEXT: 0.60 0.60 0.33 0.33 - 0.60 0.60 - - - 0.60 0.33 - lodsb (%rsi), %al
+# CHECK-NEXT: 0.60 0.60 0.33 0.33 - 0.60 0.60 - - - 0.60 0.33 - lodsw (%rsi), %ax
+# CHECK-NEXT: 0.40 0.40 0.33 0.33 - 0.40 0.40 - - - 0.40 0.33 - lodsl (%rsi), %eax
+# CHECK-NEXT: 0.40 0.40 0.33 0.33 - 0.40 0.40 - - - 0.40 0.33 - lodsq (%rsi), %rax
+# CHECK-NEXT: 0.80 0.80 0.33 0.33 0.50 0.80 0.80 0.50 0.50 0.50 0.80 0.33 - movsb (%rsi), %es:(%rdi)
+# CHECK-NEXT: 0.80 0.80 0.33 0.33 0.50 0.80 0.80 0.50 0.50 0.50 0.80 0.33 - movsw (%rsi), %es:(%rdi)
+# CHECK-NEXT: 0.80 0.80 0.33 0.33 0.50 0.80 0.80 0.50 0.50 0.50 0.80 0.33 - movsl (%rsi), %es:(%rdi)
+# CHECK-NEXT: 0.80 0.80 0.33 0.33 0.50 0.80 0.80 0.50 0.50 0.50 0.80 0.33 - movsq (%rsi), %es:(%rdi)
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - movsbw %al, %di
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - movzbw %al, %di
+# CHECK-NEXT: - 0.33 0.33 0.33 - 0.33 - - - - 0.33 0.33 - movsbw (%rax), %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - movzbw (%rax), %di
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - movsbl %al, %edi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - movzbl %al, %edi
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movsbl (%rax), %edi
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movzbl (%rax), %edi
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - movsbq %al, %rdi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - movzbq %al, %rdi
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movsbq (%rax), %rdi
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movzbq (%rax), %rdi
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - movswl %ax, %edi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - movzwl %ax, %edi
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movswl (%rax), %edi
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movzwl (%rax), %edi
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - movswq %ax, %rdi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - movzwq %ax, %rdi
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movswq (%rax), %rdi
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movzwq (%rax), %rdi
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - movslq %eax, %rdi
+# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movslq (%rax), %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - mulb %dil
+# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - mulb (%rax)
+# CHECK-NEXT: 0.90 1.40 - - - 0.40 0.90 - - - 0.40 - - mulw %si
+# CHECK-NEXT: 0.90 1.40 0.33 0.33 - 0.40 0.90 - - - 0.40 0.33 - mulw (%rax)
+# CHECK-NEXT: 0.70 1.20 - - - 0.20 0.70 - - - 0.20 - - mull %edx
+# CHECK-NEXT: 0.70 1.20 0.33 0.33 - 0.20 0.70 - - - 0.20 0.33 - mull (%rax)
+# CHECK-NEXT: - 1.00 - - - 1.00 - - - - - - - mulq %rcx
+# CHECK-NEXT: - 1.00 0.33 0.33 - 1.00 - - - - - 0.33 - mulq (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - negb %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - negb (%r8)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock negb (%r8)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - negw %si
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - negw (%r9)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock negw (%r9)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - negl %edx
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - negl (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock negl (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - negq %rcx
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - negq (%r10)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock negq (%r10)
+# CHECK-NEXT: - - - - - - - - - - - - - nop
+# CHECK-NEXT: - - - - - - - - - - - - - nopw %di
+# CHECK-NEXT: - - - - - - - - - - - - - nopw (%rcx)
+# CHECK-NEXT: - - - - - - - - - - - - - nopl %esi
+# CHECK-NEXT: - - - - - - - - - - - - - nopl (%r8)
+# CHECK-NEXT: - - - - - - - - - - - - - nopq %rdx
+# CHECK-NEXT: - - - - - - - - - - - - - nopq (%r9)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - notb %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - notb (%r8)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock notb (%r8)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - notw %si
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - notw (%r9)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock notw (%r9)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - notl %edx
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - notl (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock notl (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - notq %rcx
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - notq (%r10)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock notq (%r10)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orb $7, %al
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orb $7, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - orb $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock orb $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orb %sil, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - orb %sil, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock orb %sil, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - orb (%rax), %dil
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orw $511, %ax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orw $511, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - orw $511, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock orw $511, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orw $7, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - orw $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock orw $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orw %si, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - orw %si, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock orw %si, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - orw (%rax), %di
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orl $665536, %eax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orl $665536, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - orl $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock orl $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orl $7, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - orl $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock orl $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orl %esi, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - orl %esi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock orl %esi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - orl (%rax), %edi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orq $665536, %rax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orq $665536, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - orq $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock orq $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orq $7, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - orq $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock orq $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - orq %rsi, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - orq %rsi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock orq %rsi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - orq (%rax), %rdi
+# CHECK-NEXT: 19.00 16.00 1.67 1.67 0.50 16.50 13.50 0.50 0.50 0.50 1.00 1.67 - outb %al, $7
+# CHECK-NEXT: 19.00 16.00 1.67 1.67 0.50 16.00 14.00 0.50 0.50 0.50 1.00 1.67 - outb %al, %dx
+# CHECK-NEXT: 21.30 15.80 2.33 2.33 0.50 17.30 14.80 0.50 0.50 0.50 0.80 2.33 - outw %ax, $7
+# CHECK-NEXT: 20.70 16.20 2.33 2.33 0.50 17.20 14.70 0.50 0.50 0.50 1.20 2.33 - outw %ax, %dx
+# CHECK-NEXT: 22.30 15.80 3.00 3.00 0.50 19.30 15.80 0.50 0.50 0.50 0.80 3.00 - outl %eax, $7
+# CHECK-NEXT: 21.70 16.20 3.00 3.00 0.50 19.20 15.70 0.50 0.50 0.50 1.20 3.00 - outl %eax, %dx
+# CHECK-NEXT: 20.70 17.20 2.33 2.33 0.50 18.20 13.70 0.50 0.50 0.50 1.20 2.33 - outsb (%rsi), %dx
+# CHECK-NEXT: 21.00 17.50 2.67 2.67 0.50 19.00 14.50 0.50 0.50 0.50 1.00 2.67 - outsw (%rsi), %dx
+# CHECK-NEXT: 22.20 17.20 3.33 3.33 0.50 21.20 15.20 0.50 0.50 0.50 1.20 3.33 - outsl (%rsi), %dx
+# CHECK-NEXT: 0.50 - - - - 1.00 0.50 - - - - - - pause
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rclb %dil
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rcrb %dil
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rclb (%rax)
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rcrb (%rax)
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rclb $7, %dil
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rcrb $7, %dil
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rclb $7, (%rax)
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rcrb $7, (%rax)
+# CHECK-NEXT: 2.90 2.40 - - - 0.40 2.90 - - - 0.40 - - rclb %cl, %dil
+# CHECK-NEXT: 2.60 3.60 - - - 0.60 2.60 - - - 0.60 - - rcrb %cl, %dil
+# CHECK-NEXT: 2.70 2.20 0.33 0.33 0.50 0.20 2.70 0.50 0.50 0.50 0.20 0.33 - rclb %cl, (%rax)
+# CHECK-NEXT: 2.40 3.40 0.33 0.33 0.50 0.40 2.40 0.50 0.50 0.50 0.40 0.33 - rcrb %cl, (%rax)
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rclw %di
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rcrw %di
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rclw (%rax)
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rcrw (%rax)
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rclw $7, %di
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rcrw $7, %di
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rclw $7, (%rax)
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rcrw $7, (%rax)
+# CHECK-NEXT: 1.90 2.40 - - - 0.40 1.90 - - - 0.40 - - rclw %cl, %di
+# CHECK-NEXT: 1.90 2.40 - - - 0.40 1.90 - - - 0.40 - - rcrw %cl, %di
+# CHECK-NEXT: 1.90 2.40 0.33 0.33 0.50 0.40 1.90 0.50 0.50 0.50 0.40 0.33 - rclw %cl, (%rax)
+# CHECK-NEXT: 1.90 2.40 0.33 0.33 0.50 0.40 1.90 0.50 0.50 0.50 0.40 0.33 - rcrw %cl, (%rax)
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rcll %edi
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rcrl %edi
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rcll (%rax)
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rcrl (%rax)
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rcll $7, %edi
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rcrl $7, %edi
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rcll $7, (%rax)
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rcrl $7, (%rax)
+# CHECK-NEXT: 1.90 2.40 - - - 0.40 1.90 - - - 0.40 - - rcll %cl, %edi
+# CHECK-NEXT: 1.90 2.40 - - - 0.40 1.90 - - - 0.40 - - rcrl %cl, %edi
+# CHECK-NEXT: 1.90 2.40 0.33 0.33 0.50 0.40 1.90 0.50 0.50 0.50 0.40 0.33 - rcll %cl, (%rax)
+# CHECK-NEXT: 1.90 2.40 0.33 0.33 0.50 0.40 1.90 0.50 0.50 0.50 0.40 0.33 - rcrl %cl, (%rax)
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rclq %rdi
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rcrq %rdi
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rclq (%rax)
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rcrq (%rax)
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rclq $7, %rdi
+# CHECK-NEXT: 1.20 0.20 - - - 0.20 1.20 - - - 0.20 - - rcrq $7, %rdi
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rclq $7, (%rax)
+# CHECK-NEXT: 1.20 0.20 0.33 0.33 0.50 0.20 1.20 0.50 0.50 0.50 0.20 0.33 - rcrq $7, (%rax)
+# CHECK-NEXT: 1.90 2.40 - - - 0.40 1.90 - - - 0.40 - - rclq %cl, %rdi
+# CHECK-NEXT: 1.90 2.40 - - - 0.40 1.90 - - - 0.40 - - rcrq %cl, %rdi
+# CHECK-NEXT: 1.90 2.40 0.33 0.33 0.50 0.40 1.90 0.50 0.50 0.50 0.40 0.33 - rclq %cl, (%rax)
+# CHECK-NEXT: 1.90 2.40 0.33 0.33 0.50 0.40 1.90 0.50 0.50 0.50 0.40 0.33 - rcrq %cl, (%rax)
+# CHECK-NEXT: 16.33 13.33 - - - 10.67 13.33 - - - 0.33 - - rdmsr
+# CHECK-NEXT: 4.80 3.80 - - - 2.80 4.80 - - - 1.80 - - rdpmc
+# CHECK-NEXT: 4.00 4.00 - - - 2.00 4.00 - - - 1.00 - - rdtsc
+# CHECK-NEXT: 7.50 5.33 - - - 4.00 4.17 - - - - - - rdtscp
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolb %dil
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorb %dil
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolb (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorb (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolb $7, %dil
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorb $7, %dil
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolb $7, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorb $7, (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolb %cl, %dil
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorb %cl, %dil
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolb %cl, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorb %cl, (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolw %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorw %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolw (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorw (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolw $7, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorw $7, %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolw $7, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorw $7, (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolw %cl, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorw %cl, %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolw %cl, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorw %cl, (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - roll %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorl %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - roll (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorl (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - roll $7, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorl $7, %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - roll $7, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorl $7, (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - roll %cl, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorl %cl, %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - roll %cl, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorl %cl, (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolq %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorq %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolq (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorq (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolq $7, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorq $7, %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolq $7, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorq $7, (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolq %cl, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorq %cl, %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolq %cl, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorq %cl, (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - sahf
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sarb %dil
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shlb %dil
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shrb %dil
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - sarb (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shlb (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shrb (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sarb $7, %dil
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shlb $7, %dil
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shrb $7, %dil
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - sarb $7, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shlb $7, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shrb $7, (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - sarb %cl, %dil
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - shlb %cl, %dil
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - shrb %cl, %dil
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - sarb %cl, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - shlb %cl, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - shrb %cl, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sarw %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shlw %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shrw %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - sarw (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shlw (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shrw (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sarw $7, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shlw $7, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shrw $7, %di
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - sarw $7, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shlw $7, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shrw $7, (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - sarw %cl, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - shlw %cl, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - shrw %cl, %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - sarw %cl, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - shlw %cl, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - shrw %cl, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sarl %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shll %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shrl %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - sarl (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shll (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shrl (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sarl $7, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shll $7, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shrl $7, %edi
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - sarl $7, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shll $7, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shrl $7, (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - sarl %cl, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - shll %cl, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - shrl %cl, %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - sarl %cl, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - shll %cl, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - shrl %cl, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sarq %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shlq %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shrq %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - sarq (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shlq (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shrq (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sarq $7, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shlq $7, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - shrq $7, %rdi
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - sarq $7, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shlq $7, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 0.50 - 0.50 0.50 0.50 0.50 - 0.33 - shrq $7, (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - sarq %cl, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - shlq %cl, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - shrq %cl, %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - sarq %cl, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - shlq %cl, (%rax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - shrq %cl, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbb $0, %al
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbb $0, %dil
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - sbbb $0, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock sbbb $0, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbb $7, %al
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbb $7, %dil
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - sbbb $7, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock sbbb $7, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbb %sil, %dil
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - sbbb %sil, (%rax)
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - lock sbbb %sil, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - sbbb (%rax), %dil
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbw $0, %ax
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbw $0, %di
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - sbbw $0, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock sbbw $0, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbw $511, %ax
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbw $511, %di
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - sbbw $511, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock sbbw $511, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbw $7, %di
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - sbbw $7, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock sbbw $7, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbw %si, %di
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - sbbw %si, (%rax)
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - lock sbbw %si, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - sbbw (%rax), %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbl $0, %eax
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbl $0, %edi
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - sbbl $0, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock sbbl $0, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbl $665536, %eax
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbl $665536, %edi
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - sbbl $665536, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock sbbl $665536, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbl $7, %edi
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - sbbl $7, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock sbbl $7, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbl %esi, %edi
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - sbbl %esi, (%rax)
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - lock sbbl %esi, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - sbbl (%rax), %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbq $0, %rax
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbq $0, %rdi
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - sbbq $0, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock sbbq $0, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbq $665536, %rax
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbq $665536, %rdi
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - sbbq $665536, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock sbbq $665536, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbq $7, %rdi
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - sbbq $7, (%rax)
+# CHECK-NEXT: 0.70 0.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - lock sbbq $7, (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sbbq %rsi, %rdi
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - sbbq %rsi, (%rax)
+# CHECK-NEXT: 0.90 0.40 0.33 0.33 0.50 0.40 0.90 0.50 0.50 0.50 0.40 0.33 - lock sbbq %rsi, (%rax)
+# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - sbbq (%rax), %rdi
+# CHECK-NEXT: 0.60 0.60 0.33 0.33 - 0.60 0.60 - - - 0.60 0.33 - scasb %es:(%rdi), %al
+# CHECK-NEXT: 0.60 0.60 0.33 0.33 - 0.60 0.60 - - - 0.60 0.33 - scasw %es:(%rdi), %ax
+# CHECK-NEXT: 0.60 0.60 0.33 0.33 - 0.60 0.60 - - - 0.60 0.33 - scasl %es:(%rdi), %eax
+# CHECK-NEXT: 0.60 0.60 0.33 0.33 - 0.60 0.60 - - - 0.60 0.33 - scasq %es:(%rdi), %rax
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - seto %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - seto (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setno %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setno (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setb %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setb (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setae %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setae (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - sete %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - sete (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setne %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setne (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - seta %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - seta (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setbe %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setbe (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - sets %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - sets (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setns %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setns (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setp %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setp (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setnp %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setnp (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setl %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setl (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setge %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setge (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setg %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setg (%rax)
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setle %al
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setle (%rax)
+# CHECK-NEXT: 0.70 1.20 - - - 0.20 0.70 - - - 0.20 - - shldw %cl, %si, %di
+# CHECK-NEXT: 0.70 1.20 - - - 0.20 0.70 - - - 0.20 - - shrdw %cl, %si, %di
+# CHECK-NEXT: 0.70 1.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - shldw %cl, %si, (%rax)
+# CHECK-NEXT: 0.70 1.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - shrdw %cl, %si, (%rax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - shldw $7, %si, %di
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - shrdw $7, %si, %di
+# CHECK-NEXT: 0.20 1.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - shldw $7, %si, (%rax)
+# CHECK-NEXT: 0.20 1.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - shrdw $7, %si, (%rax)
+# CHECK-NEXT: 0.70 1.20 - - - 0.20 0.70 - - - 0.20 - - shldl %cl, %esi, %edi
+# CHECK-NEXT: 0.70 1.20 - - - 0.20 0.70 - - - 0.20 - - shrdl %cl, %esi, %edi
+# CHECK-NEXT: 0.70 1.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - shldl %cl, %esi, (%rax)
+# CHECK-NEXT: 0.70 1.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - shrdl %cl, %esi, (%rax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - shldl $7, %esi, %edi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - shrdl $7, %esi, %edi
+# CHECK-NEXT: 0.20 1.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - shldl $7, %esi, (%rax)
+# CHECK-NEXT: 0.20 1.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - shrdl $7, %esi, (%rax)
+# CHECK-NEXT: 0.70 1.20 - - - 0.20 0.70 - - - 0.20 - - shldq %cl, %rsi, %rdi
+# CHECK-NEXT: 0.70 1.20 - - - 0.20 0.70 - - - 0.20 - - shrdq %cl, %rsi, %rdi
+# CHECK-NEXT: 0.70 1.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - shldq %cl, %rsi, (%rax)
+# CHECK-NEXT: 0.70 1.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - shrdq %cl, %rsi, (%rax)
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - shldq $7, %rsi, %rdi
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - shrdq $7, %rsi, %rdi
+# CHECK-NEXT: 0.20 1.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - shldq $7, %rsi, (%rax)
+# CHECK-NEXT: 0.20 1.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - shrdq $7, %rsi, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - stc
+# CHECK-NEXT: 0.70 0.20 - - - 0.20 0.70 - - - 0.20 - - std
+# CHECK-NEXT: 0.40 0.40 - - 0.50 0.40 0.40 0.50 0.50 0.50 0.40 - - stosb %al, %es:(%rdi)
+# CHECK-NEXT: 0.40 0.40 - - 0.50 0.40 0.40 0.50 0.50 0.50 0.40 - - stosw %ax, %es:(%rdi)
+# CHECK-NEXT: 0.40 0.40 - - 0.50 0.40 0.40 0.50 0.50 0.50 0.40 - - stosl %eax, %es:(%rdi)
+# CHECK-NEXT: 0.40 0.40 - - 0.50 0.40 0.40 0.50 0.50 0.50 0.40 - - stosq %rax, %es:(%rdi)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subb $7, %al
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subb $7, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subb $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subb $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subb %sil, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subb %sil, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subb %sil, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - subb (%rax), %dil
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subw $511, %ax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subw $511, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subw $511, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subw $511, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subw $7, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subw $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subw $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subw %si, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subw %si, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subw %si, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - subw (%rax), %di
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subl $665536, %eax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subl $665536, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subl $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subl $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subl $7, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subl $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subl $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subl %esi, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subl %esi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subl %esi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - subl (%rax), %edi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subq $665536, %rax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subq $665536, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subq $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subq $665536, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - subq $7, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subq $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subq $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subq %rsi, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subq %rsi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subq %rsi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - subq (%rax), %rdi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testb $7, %al
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testb $7, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - testb $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testb %sil, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - testb %sil, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testw $511, %ax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testw $511, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - testw $511, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testw $7, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - testw $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testw %si, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - testw %si, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testl $665536, %eax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testl $665536, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - testl $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testl $7, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - testl $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testl %esi, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - testl %esi, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testq $665536, %rax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testq $665536, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - testq $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testq $7, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - testq $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - testq %rsi, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - testq %rsi, (%rax)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - ud2
+# CHECK-NEXT: 52.00 31.50 - - 0.50 27.00 31.50 0.50 0.50 0.50 - - - wrmsr
+# CHECK-NEXT: 0.60 0.60 - - - 0.60 0.60 - - - 0.60 - - xaddb %bl, %cl
+# CHECK-NEXT: 0.40 0.40 0.33 0.33 0.50 0.40 0.40 0.50 0.50 0.50 0.40 0.33 - xaddb %bl, (%rcx)
+# CHECK-NEXT: 0.40 0.40 0.33 0.33 0.50 0.40 0.40 0.50 0.50 0.50 0.40 0.33 - lock xaddb %bl, (%rcx)
+# CHECK-NEXT: 0.60 0.60 - - - 0.60 0.60 - - - 0.60 - - xaddw %bx, %cx
+# CHECK-NEXT: 0.40 0.40 0.33 0.33 0.50 0.40 0.40 0.50 0.50 0.50 0.40 0.33 - xaddw %ax, (%rbx)
+# CHECK-NEXT: 0.40 0.40 0.33 0.33 0.50 0.40 0.40 0.50 0.50 0.50 0.40 0.33 - lock xaddw %ax, (%rbx)
+# CHECK-NEXT: 0.60 0.60 - - - 0.60 0.60 - - - 0.60 - - xaddl %ebx, %ecx
+# CHECK-NEXT: 0.40 0.40 0.33 0.33 0.50 0.40 0.40 0.50 0.50 0.50 0.40 0.33 - xaddl %eax, (%rbx)
+# CHECK-NEXT: 0.40 0.40 0.33 0.33 0.50 0.40 0.40 0.50 0.50 0.50 0.40 0.33 - lock xaddl %eax, (%rbx)
+# CHECK-NEXT: 0.60 0.60 - - - 0.60 0.60 - - - 0.60 - - xaddq %rbx, %rcx
+# CHECK-NEXT: 0.40 0.40 0.33 0.33 0.50 0.40 0.40 0.50 0.50 0.50 0.40 0.33 - xaddq %rax, (%rbx)
+# CHECK-NEXT: 0.40 0.40 0.33 0.33 0.50 0.40 0.40 0.50 0.50 0.50 0.40 0.33 - lock xaddq %rax, (%rbx)
+# CHECK-NEXT: 0.60 0.60 - - - 0.60 0.60 - - - 0.60 - - xchgb %bl, %cl
+# CHECK-NEXT: 1.30 0.80 0.33 0.33 0.50 0.80 1.30 0.50 0.50 0.50 0.80 0.33 - xchgb %bl, (%rbx)
+# CHECK-NEXT: 1.30 0.80 0.33 0.33 0.50 0.80 1.30 0.50 0.50 0.50 0.80 0.33 - lock xchgb %bl, (%rbx)
+# CHECK-NEXT: 0.60 0.60 - - - 0.60 0.60 - - - 0.60 - - xchgw %bx, %ax
+# CHECK-NEXT: 0.60 0.60 - - - 0.60 0.60 - - - 0.60 - - xchgw %bx, %cx
+# CHECK-NEXT: 1.30 0.80 0.33 0.33 0.50 0.80 1.30 0.50 0.50 0.50 0.80 0.33 - xchgw %ax, (%rbx)
+# CHECK-NEXT: 1.30 0.80 0.33 0.33 0.50 0.80 1.30 0.50 0.50 0.50 0.80 0.33 - lock xchgw %ax, (%rbx)
+# CHECK-NEXT: 0.60 0.60 - - - 0.60 0.60 - - - 0.60 - - xchgl %ebx, %eax
+# CHECK-NEXT: 0.60 0.60 - - - 0.60 0.60 - - - 0.60 - - xchgl %ebx, %ecx
+# CHECK-NEXT: 1.30 0.80 0.33 0.33 0.50 0.80 1.30 0.50 0.50 0.50 0.80 0.33 - xchgl %eax, (%rbx)
+# CHECK-NEXT: 1.30 0.80 0.33 0.33 0.50 0.80 1.30 0.50 0.50 0.50 0.80 0.33 - lock xchgl %eax, (%rbx)
+# CHECK-NEXT: 0.60 0.60 - - - 0.60 0.60 - - - 0.60 - - xchgq %rbx, %rax
+# CHECK-NEXT: 0.60 0.60 - - - 0.60 0.60 - - - 0.60 - - xchgq %rbx, %rcx
+# CHECK-NEXT: 1.50 1.00 0.33 0.33 0.50 1.00 1.50 0.50 0.50 0.50 1.00 0.33 - xchgq %rax, (%rbx)
+# CHECK-NEXT: 1.50 1.00 0.33 0.33 0.50 1.00 1.50 0.50 0.50 0.50 1.00 0.33 - lock xchgq %rax, (%rbx)
+# CHECK-NEXT: 0.40 0.40 0.33 0.33 - 0.40 0.40 - - - 0.40 0.33 - xlatb
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorb $7, %al
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorb $7, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - xorb $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock xorb $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorb %sil, %dil
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - xorb %sil, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock xorb %sil, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - xorb (%rax), %dil
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorw $511, %ax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorw $511, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - xorw $511, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock xorw $511, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorw $7, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - xorw $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock xorw $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorw %si, %di
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - xorw %si, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock xorw %si, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - xorw (%rax), %di
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorl $665536, %eax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorl $665536, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - xorl $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock xorl $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorl $7, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - xorl $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock xorl $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorl %esi, %edi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - xorl %esi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock xorl %esi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - xorl (%rax), %edi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorq $665536, %rax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorq $665536, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - xorq $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock xorq $665536, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorq $7, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - xorq $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock xorq $7, (%rax)
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - xorq %rsi, %rdi
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - xorq %rsi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock xorq %rsi, (%rax)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - xorq (%rax), %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x87.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x87.s
new file mode 100644
index 0000000000000..5947c582df4b3
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x87.s
@@ -0,0 +1,526 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s
+
+f2xm1
+
+fabs
+
+fadd %st, %st(1)
+fadd %st(2)
+fadds (%ecx)
+faddl (%ecx)
+faddp %st(1)
+faddp %st(2)
+fiadds (%ecx)
+fiaddl (%ecx)
+
+fbld (%ecx)
+fbstp (%eax)
+
+fchs
+
+fnclex
+
+fcmovb %st(1), %st
+fcmovbe %st(1), %st
+fcmove %st(1), %st
+fcmovnb %st(1), %st
+fcmovnbe %st(1), %st
+fcmovne %st(1), %st
+fcmovnu %st(1), %st
+fcmovu %st(1), %st
+
+fcom %st(1)
+fcom %st(3)
+fcoms (%ecx)
+fcoml (%eax)
+fcomp %st(1)
+fcomp %st(3)
+fcomps (%ecx)
+fcompl (%eax)
+fcompp
+
+fcomi %st(3)
+fcompi %st(3)
+
+fcos
+
+fdecstp
+
+fdiv %st, %st(1)
+fdiv %st(2)
+fdivs (%ecx)
+fdivl (%eax)
+fdivp %st(1)
+fdivp %st(2)
+fidivs (%ecx)
+fidivl (%eax)
+
+fdivr %st, %st(1)
+fdivr %st(2)
+fdivrs (%ecx)
+fdivrl (%eax)
+fdivrp %st(1)
+fdivrp %st(2)
+fidivrs (%ecx)
+fidivrl (%eax)
+
+ffree %st(0)
+
+ficoms (%ecx)
+ficoml (%eax)
+ficomps (%ecx)
+ficompl (%eax)
+
+filds (%edx)
+fildl (%ecx)
+fildll (%eax)
+
+fincstp
+
+fninit
+
+fists (%edx)
+fistl (%ecx)
+fistps (%edx)
+fistpl (%ecx)
+fistpll (%eax)
+
+fisttps (%edx)
+fisttpl (%ecx)
+fisttpll (%eax)
+
+fld %st(0)
+flds (%edx)
+fldl (%ecx)
+fldt (%eax)
+
+fldcw (%eax)
+fldenv (%eax)
+
+fld1
+fldl2e
+fldl2t
+fldlg2
+fldln2
+fldpi
+fldz
+
+fmul %st, %st(1)
+fmul %st(2)
+fmuls (%ecx)
+fmull (%eax)
+fmulp %st(1)
+fmulp %st(2)
+fimuls (%ecx)
+fimull (%eax)
+
+fnop
+
+fpatan
+
+fprem
+fprem1
+
+fptan
+
+frndint
+
+frstor (%eax)
+
+fnsave (%eax)
+
+fscale
+
+fsin
+
+fsincos
+
+fsqrt
+
+fst %st(0)
+fsts (%edx)
+fstl (%ecx)
+fstp %st(0)
+fstpl (%edx)
+fstpl (%ecx)
+fstpt (%eax)
+
+fnstcw (%eax)
+fnstenv (%eax)
+fnstsw (%eax)
+
+frstor (%eax)
+fsave (%eax)
+
+fsub %st, %st(1)
+fsub %st(2)
+fsubs (%ecx)
+fsubl (%eax)
+fsubp %st(1)
+fsubp %st(2)
+fisubs (%ecx)
+fisubl (%eax)
+
+fsubr %st, %st(1)
+fsubr %st(2)
+fsubrs (%ecx)
+fsubrl (%eax)
+fsubrp %st(1)
+fsubrp %st(2)
+fisubrs (%ecx)
+fisubrl (%eax)
+
+ftst
+
+fucom %st(1)
+fucom %st(3)
+fucomp %st(1)
+fucomp %st(3)
+fucompp
+
+fucomi %st(3)
+fucompi %st(3)
+
+fwait
+
+fxam
+
+fxch %st(1)
+fxch %st(3)
+
+fxrstor (%eax)
+fxsave (%eax)
+
+fxtract
+
+fyl2x
+fyl2xp1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 U f2xm1
+# CHECK-NEXT: 1 1 1.00 U fabs
+# CHECK-NEXT: 1 3 1.00 U fadd %st, %st(1)
+# CHECK-NEXT: 1 3 1.00 U fadd %st(2), %st
+# CHECK-NEXT: 2 10 1.00 * U fadds (%ecx)
+# CHECK-NEXT: 2 10 1.00 * U faddl (%ecx)
+# CHECK-NEXT: 1 3 1.00 U faddp %st, %st(1)
+# CHECK-NEXT: 1 3 1.00 U faddp %st, %st(2)
+# CHECK-NEXT: 3 13 2.00 * U fiadds (%ecx)
+# CHECK-NEXT: 3 13 2.00 * U fiaddl (%ecx)
+# CHECK-NEXT: 1 100 0.25 * U fbld (%ecx)
+# CHECK-NEXT: 2 1 1.00 * U fbstp (%eax)
+# CHECK-NEXT: 1 1 1.00 U fchs
+# CHECK-NEXT: 4 4 1.00 U fnclex
+# CHECK-NEXT: 1 3 1.00 U fcmovb %st(1), %st
+# CHECK-NEXT: 1 3 1.00 U fcmovbe %st(1), %st
+# CHECK-NEXT: 1 3 1.00 U fcmove %st(1), %st
+# CHECK-NEXT: 1 3 1.00 U fcmovnb %st(1), %st
+# CHECK-NEXT: 1 3 1.00 U fcmovnbe %st(1), %st
+# CHECK-NEXT: 1 3 1.00 U fcmovne %st(1), %st
+# CHECK-NEXT: 1 3 1.00 U fcmovnu %st(1), %st
+# CHECK-NEXT: 1 3 1.00 U fcmovu %st(1), %st
+# CHECK-NEXT: 1 1 1.00 U fcom %st(1)
+# CHECK-NEXT: 1 1 1.00 U fcom %st(3)
+# CHECK-NEXT: 2 8 1.00 * U fcoms (%ecx)
+# CHECK-NEXT: 2 8 1.00 * U fcoml (%eax)
+# CHECK-NEXT: 1 1 1.00 U fcomp %st(1)
+# CHECK-NEXT: 1 1 1.00 U fcomp %st(3)
+# CHECK-NEXT: 2 8 1.00 * U fcomps (%ecx)
+# CHECK-NEXT: 2 8 1.00 * U fcompl (%eax)
+# CHECK-NEXT: 1 100 0.25 U fcompp
+# CHECK-NEXT: 1 1 1.00 U fcomi %st(3), %st
+# CHECK-NEXT: 1 1 1.00 U fcompi %st(3), %st
+# CHECK-NEXT: 1 100 0.25 U fcos
+# CHECK-NEXT: 2 2 1.00 U fdecstp
+# CHECK-NEXT: 1 15 1.00 U fdiv %st, %st(1)
+# CHECK-NEXT: 1 20 1.00 U fdiv %st(2), %st
+# CHECK-NEXT: 2 22 1.00 * U fdivs (%ecx)
+# CHECK-NEXT: 2 22 1.00 * U fdivl (%eax)
+# CHECK-NEXT: 1 15 1.00 U fdivp %st, %st(1)
+# CHECK-NEXT: 1 15 1.00 U fdivp %st, %st(2)
+# CHECK-NEXT: 3 25 1.00 * U fidivs (%ecx)
+# CHECK-NEXT: 3 25 1.00 * U fidivl (%eax)
+# CHECK-NEXT: 1 20 1.00 U fdivr %st, %st(1)
+# CHECK-NEXT: 1 15 1.00 U fdivr %st(2), %st
+# CHECK-NEXT: 2 27 1.00 * U fdivrs (%ecx)
+# CHECK-NEXT: 2 27 1.00 * U fdivrl (%eax)
+# CHECK-NEXT: 1 20 1.00 U fdivrp %st, %st(1)
+# CHECK-NEXT: 1 20 1.00 U fdivrp %st, %st(2)
+# CHECK-NEXT: 3 30 1.00 * U fidivrs (%ecx)
+# CHECK-NEXT: 3 30 1.00 * U fidivrl (%eax)
+# CHECK-NEXT: 1 100 0.25 U ffree %st(0)
+# CHECK-NEXT: 3 11 2.00 * U ficoms (%ecx)
+# CHECK-NEXT: 3 11 2.00 * U ficoml (%eax)
+# CHECK-NEXT: 3 11 2.00 * U ficomps (%ecx)
+# CHECK-NEXT: 3 11 2.00 * U ficompl (%eax)
+# CHECK-NEXT: 2 10 1.00 * U filds (%edx)
+# CHECK-NEXT: 2 10 1.00 * U fildl (%ecx)
+# CHECK-NEXT: 2 10 1.00 * U fildll (%eax)
+# CHECK-NEXT: 1 1 0.50 U fincstp
+# CHECK-NEXT: 15 75 6.00 U fninit
+# CHECK-NEXT: 3 4 1.00 * U fists (%edx)
+# CHECK-NEXT: 3 4 1.00 * U fistl (%ecx)
+# CHECK-NEXT: 3 4 1.00 * U fistps (%edx)
+# CHECK-NEXT: 3 4 1.00 * U fistpl (%ecx)
+# CHECK-NEXT: 3 4 1.00 * U fistpll (%eax)
+# CHECK-NEXT: 3 4 1.00 * U fisttps (%edx)
+# CHECK-NEXT: 3 4 1.00 * U fisttpl (%ecx)
+# CHECK-NEXT: 3 4 1.00 * U fisttpll (%eax)
+# CHECK-NEXT: 1 1 0.25 U fld %st(0)
+# CHECK-NEXT: 1 7 0.50 * U flds (%edx)
+# CHECK-NEXT: 1 7 0.50 * U fldl (%ecx)
+# CHECK-NEXT: 1 7 0.50 * U fldt (%eax)
+# CHECK-NEXT: 3 7 1.00 * U fldcw (%eax)
+# CHECK-NEXT: 64 62 14.00 * U fldenv (%eax)
+# CHECK-NEXT: 2 1 1.00 U fld1
+# CHECK-NEXT: 2 1 1.00 U fldl2e
+# CHECK-NEXT: 2 1 1.00 U fldl2t
+# CHECK-NEXT: 2 1 1.00 U fldlg2
+# CHECK-NEXT: 2 1 1.00 U fldln2
+# CHECK-NEXT: 2 1 1.00 U fldpi
+# CHECK-NEXT: 1 1 0.50 U fldz
+# CHECK-NEXT: 1 4 1.00 U fmul %st, %st(1)
+# CHECK-NEXT: 1 4 1.00 U fmul %st(2), %st
+# CHECK-NEXT: 2 11 1.00 * U fmuls (%ecx)
+# CHECK-NEXT: 2 11 1.00 * U fmull (%eax)
+# CHECK-NEXT: 1 4 1.00 U fmulp %st, %st(1)
+# CHECK-NEXT: 1 4 1.00 U fmulp %st, %st(2)
+# CHECK-NEXT: 3 14 1.00 * U fimuls (%ecx)
+# CHECK-NEXT: 3 14 1.00 * U fimull (%eax)
+# CHECK-NEXT: 1 1 0.50 U fnop
+# CHECK-NEXT: 1 100 0.25 U fpatan
+# CHECK-NEXT: 1 100 0.25 U fprem
+# CHECK-NEXT: 1 100 0.25 U fprem1
+# CHECK-NEXT: 1 100 0.25 U fptan
+# CHECK-NEXT: 1 100 0.25 U frndint
+# CHECK-NEXT: 1 100 0.25 * U frstor (%eax)
+# CHECK-NEXT: 1 100 0.25 * U fnsave (%eax)
+# CHECK-NEXT: 1 100 0.25 U fscale
+# CHECK-NEXT: 1 100 0.25 U fsin
+# CHECK-NEXT: 1 100 0.25 U fsincos
+# CHECK-NEXT: 1 21 7.00 U fsqrt
+# CHECK-NEXT: 1 1 0.25 U fst %st(0)
+# CHECK-NEXT: 1 1 1.00 * U fsts (%edx)
+# CHECK-NEXT: 1 1 1.00 * U fstl (%ecx)
+# CHECK-NEXT: 1 1 0.25 U fstp %st(0)
+# CHECK-NEXT: 2 1 1.00 * U fstpl (%edx)
+# CHECK-NEXT: 2 1 1.00 * U fstpl (%ecx)
+# CHECK-NEXT: 2 1 1.00 * U fstpt (%eax)
+# CHECK-NEXT: 3 2 1.00 * U fnstcw (%eax)
+# CHECK-NEXT: 100 106 19.50 * U fnstenv (%eax)
+# CHECK-NEXT: 3 3 1.00 * U fnstsw (%eax)
+# CHECK-NEXT: 1 100 0.25 * U frstor (%eax)
+# CHECK-NEXT: 2 2 0.50 U wait
+# CHECK-NEXT: 1 100 0.25 * U fnsave (%eax)
+# CHECK-NEXT: 1 3 1.00 U fsub %st, %st(1)
+# CHECK-NEXT: 1 3 1.00 U fsub %st(2), %st
+# CHECK-NEXT: 2 10 1.00 * U fsubs (%ecx)
+# CHECK-NEXT: 2 10 1.00 * U fsubl (%eax)
+# CHECK-NEXT: 1 3 1.00 U fsubp %st, %st(1)
+# CHECK-NEXT: 1 3 1.00 U fsubp %st, %st(2)
+# CHECK-NEXT: 3 13 2.00 * U fisubs (%ecx)
+# CHECK-NEXT: 3 13 2.00 * U fisubl (%eax)
+# CHECK-NEXT: 1 3 1.00 U fsubr %st, %st(1)
+# CHECK-NEXT: 1 3 1.00 U fsubr %st(2), %st
+# CHECK-NEXT: 2 10 1.00 * U fsubrs (%ecx)
+# CHECK-NEXT: 2 10 1.00 * U fsubrl (%eax)
+# CHECK-NEXT: 1 3 1.00 U fsubrp %st, %st(1)
+# CHECK-NEXT: 1 3 1.00 U fsubrp %st, %st(2)
+# CHECK-NEXT: 3 13 2.00 * U fisubrs (%ecx)
+# CHECK-NEXT: 3 13 2.00 * U fisubrl (%eax)
+# CHECK-NEXT: 1 2 1.00 U ftst
+# CHECK-NEXT: 1 1 1.00 U fucom %st(1)
+# CHECK-NEXT: 1 1 1.00 U fucom %st(3)
+# CHECK-NEXT: 1 1 1.00 U fucomp %st(1)
+# CHECK-NEXT: 1 1 1.00 U fucomp %st(3)
+# CHECK-NEXT: 1 2 1.00 U fucompp
+# CHECK-NEXT: 1 1 1.00 U fucomi %st(3), %st
+# CHECK-NEXT: 1 1 1.00 U fucompi %st(3), %st
+# CHECK-NEXT: 2 2 0.50 U wait
+# CHECK-NEXT: 1 2 1.00 U fxam
+# CHECK-NEXT: 15 17 4.00 U fxch %st(1)
+# CHECK-NEXT: 15 17 4.00 U fxch %st(3)
+# CHECK-NEXT: 90 63 16.50 * * U fxrstor (%eax)
+# CHECK-NEXT: 110 100 19.00 * * U fxsave (%eax)
+# CHECK-NEXT: 1 100 0.25 U fxtract
+# CHECK-NEXT: 1 100 0.25 U fyl2x
+# CHECK-NEXT: 1 100 0.25 U fyl2xp1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 131.25 62.75 49.67 49.67 46.00 159.25 74.75 28.00 19.00 19.00 1.00 0.67 7.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - f2xm1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fabs
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fadd %st, %st(1)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fadd %st(2), %st
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - fadds (%ecx)
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - faddl (%ecx)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - faddp %st, %st(1)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - faddp %st, %st(2)
+# CHECK-NEXT: - - 0.50 0.50 - 2.00 - - - - - - - fiadds (%ecx)
+# CHECK-NEXT: - - 0.50 0.50 - 2.00 - - - - - - - fiaddl (%ecx)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fbld (%ecx)
+# CHECK-NEXT: - - 0.33 0.33 1.00 - - 0.33 - - - - - fbstp (%eax)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fchs
+# CHECK-NEXT: 1.00 1.00 - - - 1.00 1.00 - - - - - - fnclex
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcmovb %st(1), %st
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcmovbe %st(1), %st
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcmove %st(1), %st
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcmovnb %st(1), %st
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcmovnbe %st(1), %st
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcmovne %st(1), %st
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcmovnu %st(1), %st
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fcmovu %st(1), %st
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcom %st(1)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcom %st(3)
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - fcoms (%ecx)
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - fcoml (%eax)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcomp %st(1)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcomp %st(3)
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - fcomps (%ecx)
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - fcompl (%eax)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fcompp
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcomi %st(3), %st
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fcompi %st(3), %st
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fcos
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - fdecstp
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fdiv %st, %st(1)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fdiv %st(2), %st
+# CHECK-NEXT: 1.00 - 0.50 0.50 - - - - - - - - - fdivs (%ecx)
+# CHECK-NEXT: 1.00 - 0.50 0.50 - - - - - - - - - fdivl (%eax)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fdivp %st, %st(1)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fdivp %st, %st(2)
+# CHECK-NEXT: 1.00 - 0.50 0.50 - 1.00 - - - - - - - fidivs (%ecx)
+# CHECK-NEXT: 1.00 - 0.50 0.50 - 1.00 - - - - - - - fidivl (%eax)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fdivr %st, %st(1)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fdivr %st(2), %st
+# CHECK-NEXT: 1.00 - 0.50 0.50 - - - - - - - - - fdivrs (%ecx)
+# CHECK-NEXT: 1.00 - 0.50 0.50 - - - - - - - - - fdivrl (%eax)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fdivrp %st, %st(1)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fdivrp %st, %st(2)
+# CHECK-NEXT: 1.00 - 0.50 0.50 - 1.00 - - - - - - - fidivrs (%ecx)
+# CHECK-NEXT: 1.00 - 0.50 0.50 - 1.00 - - - - - - - fidivrl (%eax)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - ffree %st(0)
+# CHECK-NEXT: - - 0.50 0.50 - 2.00 - - - - - - - ficoms (%ecx)
+# CHECK-NEXT: - - 0.50 0.50 - 2.00 - - - - - - - ficoml (%eax)
+# CHECK-NEXT: - - 0.50 0.50 - 2.00 - - - - - - - ficomps (%ecx)
+# CHECK-NEXT: - - 0.50 0.50 - 2.00 - - - - - - - ficompl (%eax)
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - filds (%edx)
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - fildl (%ecx)
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - fildll (%eax)
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - fincstp
+# CHECK-NEXT: 3.00 1.50 - - - 9.00 1.50 - - - - - - fninit
+# CHECK-NEXT: - - 0.33 0.33 1.00 1.00 - 0.33 - - - - - fists (%edx)
+# CHECK-NEXT: - - 0.33 0.33 1.00 1.00 - 0.33 - - - - - fistl (%ecx)
+# CHECK-NEXT: - - 0.33 0.33 1.00 1.00 - 0.33 - - - - - fistps (%edx)
+# CHECK-NEXT: - - 0.33 0.33 1.00 1.00 - 0.33 - - - - - fistpl (%ecx)
+# CHECK-NEXT: - - 0.33 0.33 1.00 1.00 - 0.33 - - - - - fistpll (%eax)
+# CHECK-NEXT: - - 0.33 0.33 1.00 1.00 - 0.33 - - - - - fisttps (%edx)
+# CHECK-NEXT: - - 0.33 0.33 1.00 1.00 - 0.33 - - - - - fisttpl (%ecx)
+# CHECK-NEXT: - - 0.33 0.33 1.00 1.00 - 0.33 - - - - - fisttpll (%eax)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fld %st(0)
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - flds (%edx)
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - fldl (%ecx)
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - fldt (%eax)
+# CHECK-NEXT: 1.50 - 0.50 0.50 - 0.50 - - - - - - - fldcw (%eax)
+# CHECK-NEXT: 19.25 9.75 4.00 4.00 - 12.25 14.75 - - - - - - fldenv (%eax)
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - fld1
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - fldl2e
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - fldl2t
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - fldlg2
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - fldln2
+# CHECK-NEXT: 1.00 - - - - 1.00 - - - - - - - fldpi
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - fldz
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmul %st, %st(1)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmul %st(2), %st
+# CHECK-NEXT: 1.00 - 0.50 0.50 - - - - - - - - - fmuls (%ecx)
+# CHECK-NEXT: 1.00 - 0.50 0.50 - - - - - - - - - fmull (%eax)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmulp %st, %st(1)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmulp %st, %st(2)
+# CHECK-NEXT: 1.00 - 0.50 0.50 - 1.00 - - - - - - - fimuls (%ecx)
+# CHECK-NEXT: 1.00 - 0.50 0.50 - 1.00 - - - - - - - fimull (%eax)
+# CHECK-NEXT: 0.50 - - - - 0.50 - - - - - - - fnop
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fpatan
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fprem
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fprem1
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fptan
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - frndint
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - frstor (%eax)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fnsave (%eax)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fscale
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fsin
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fsincos
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 7.00 fsqrt
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fst %st(0)
+# CHECK-NEXT: - - 0.33 0.33 1.00 - - 0.33 - - - - - fsts (%edx)
+# CHECK-NEXT: - - 0.33 0.33 1.00 - - 0.33 - - - - - fstl (%ecx)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fstp %st(0)
+# CHECK-NEXT: - - 0.33 0.33 1.00 - - 0.33 - - - - - fstpl (%edx)
+# CHECK-NEXT: - - 0.33 0.33 1.00 - - 0.33 - - - - - fstpl (%ecx)
+# CHECK-NEXT: - - 0.33 0.33 1.00 - - 0.33 - - - - - fstpt (%eax)
+# CHECK-NEXT: - - 0.33 0.33 1.00 - 1.00 0.33 - - - - - fnstcw (%eax)
+# CHECK-NEXT: 27.00 8.50 3.67 3.67 11.00 23.50 19.00 3.67 - - - - - fnstenv (%eax)
+# CHECK-NEXT: 1.00 - 0.33 0.33 1.00 - - 0.33 - - - - - fnstsw (%eax)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - frstor (%eax)
+# CHECK-NEXT: 0.50 0.50 - - - 0.50 0.50 - - - - - - wait
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fnsave (%eax)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fsub %st, %st(1)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fsub %st(2), %st
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - fsubs (%ecx)
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - fsubl (%eax)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fsubp %st, %st(1)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fsubp %st, %st(2)
+# CHECK-NEXT: - - 0.50 0.50 - 2.00 - - - - - - - fisubs (%ecx)
+# CHECK-NEXT: - - 0.50 0.50 - 2.00 - - - - - - - fisubl (%eax)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fsubr %st, %st(1)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fsubr %st(2), %st
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - fsubrs (%ecx)
+# CHECK-NEXT: - - 0.50 0.50 - 1.00 - - - - - - - fsubrl (%eax)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fsubrp %st, %st(1)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fsubrp %st, %st(2)
+# CHECK-NEXT: - - 0.50 0.50 - 2.00 - - - - - - - fisubrs (%ecx)
+# CHECK-NEXT: - - 0.50 0.50 - 2.00 - - - - - - - fisubrl (%eax)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - ftst
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fucom %st(1)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fucom %st(3)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fucomp %st(1)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fucomp %st(3)
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fucompp
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fucomi %st(3), %st
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - fucompi %st(3), %st
+# CHECK-NEXT: 0.50 0.50 - - - 0.50 0.50 - - - - - - wait
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fxam
+# CHECK-NEXT: 4.00 2.00 - - - 4.00 5.00 - - - - - - fxch %st(1)
+# CHECK-NEXT: 4.00 2.00 - - - 4.00 5.00 - - - - - - fxch %st(3)
+# CHECK-NEXT: 17.25 12.25 16.50 16.50 - 12.75 14.75 - - - - - - fxrstor (%eax)
+# CHECK-NEXT: 8.00 11.00 0.67 0.67 19.00 6.00 6.00 19.00 19.00 19.00 1.00 0.67 - fxsave (%eax)
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fxtract
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fyl2x
+# CHECK-NEXT: 0.25 0.25 - - - 0.25 0.25 - - - - - - fyl2xp1
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s
new file mode 100644
index 0000000000000..90fea632be66b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s
@@ -0,0 +1,496 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -timeline -register-file-stats -iterations=1 < %s | FileCheck %s
+
+# On SKL, renamer-based zeroing does not work for:
+# - 16 and 8-bit GPRs
+# - MMX
+# - ANDN variants
+
+subl %eax, %eax
+subq %rax, %rax
+xorl %eax, %eax
+xorq %rax, %rax
+
+pcmpgtb %mm2, %mm2
+pcmpgtd %mm2, %mm2
+# pcmpgtq %mm2, %mm2 # invalid operand for instruction
+pcmpgtw %mm2, %mm2
+
+pcmpgtb %xmm2, %xmm2
+pcmpgtd %xmm2, %xmm2
+pcmpgtq %xmm2, %xmm2
+pcmpgtw %xmm2, %xmm2
+
+vpcmpgtb %xmm3, %xmm3, %xmm3
+vpcmpgtd %xmm3, %xmm3, %xmm3
+vpcmpgtq %xmm3, %xmm3, %xmm3
+vpcmpgtw %xmm3, %xmm3, %xmm3
+
+vpcmpgtb %xmm3, %xmm3, %xmm5
+vpcmpgtd %xmm3, %xmm3, %xmm5
+vpcmpgtq %xmm3, %xmm3, %xmm5
+vpcmpgtw %xmm3, %xmm3, %xmm5
+
+vpcmpgtb %ymm3, %ymm3, %ymm3
+vpcmpgtd %ymm3, %ymm3, %ymm3
+vpcmpgtq %ymm3, %ymm3, %ymm3
+vpcmpgtw %ymm3, %ymm3, %ymm3
+
+vpcmpgtb %ymm3, %ymm3, %ymm5
+vpcmpgtd %ymm3, %ymm3, %ymm5
+vpcmpgtq %ymm3, %ymm3, %ymm5
+vpcmpgtw %ymm3, %ymm3, %ymm5
+
+psubb %mm2, %mm2
+psubd %mm2, %mm2
+psubq %mm2, %mm2
+psubw %mm2, %mm2
+psubb %xmm2, %xmm2
+psubd %xmm2, %xmm2
+psubq %xmm2, %xmm2
+psubw %xmm2, %xmm2
+vpsubb %xmm3, %xmm3, %xmm3
+vpsubd %xmm3, %xmm3, %xmm3
+vpsubq %xmm3, %xmm3, %xmm3
+vpsubw %xmm3, %xmm3, %xmm3
+vpsubb %ymm3, %ymm3, %ymm3
+vpsubd %ymm3, %ymm3, %ymm3
+vpsubq %ymm3, %ymm3, %ymm3
+vpsubw %ymm3, %ymm3, %ymm3
+
+vpsubb %xmm3, %xmm3, %xmm5
+vpsubd %xmm3, %xmm3, %xmm5
+vpsubq %xmm3, %xmm3, %xmm5
+vpsubw %xmm3, %xmm3, %xmm5
+vpsubb %ymm3, %ymm3, %ymm5
+vpsubd %ymm3, %ymm3, %ymm5
+vpsubq %ymm3, %ymm3, %ymm5
+vpsubw %ymm3, %ymm3, %ymm5
+
+andnps %xmm0, %xmm0
+andnpd %xmm1, %xmm1
+vandnps %xmm2, %xmm2, %xmm2
+vandnpd %xmm1, %xmm1, %xmm1
+vandnps %ymm2, %ymm2, %ymm2
+vandnpd %ymm1, %ymm1, %ymm1
+pandn %mm2, %mm2
+pandn %xmm2, %xmm2
+vpandn %xmm3, %xmm3, %xmm3
+vpandn %ymm3, %ymm3, %ymm3
+
+vandnps %xmm2, %xmm2, %xmm5
+vandnpd %xmm1, %xmm1, %xmm5
+vpandn %xmm3, %xmm3, %xmm5
+vandnps %ymm2, %ymm2, %ymm5
+vandnpd %ymm1, %ymm1, %ymm5
+vpandn %ymm3, %ymm3, %ymm5
+
+xorps %xmm0, %xmm0
+xorpd %xmm1, %xmm1
+vxorps %xmm2, %xmm2, %xmm2
+vxorpd %xmm1, %xmm1, %xmm1
+vxorps %ymm2, %ymm2, %ymm2
+vxorpd %ymm1, %ymm1, %ymm1
+pxor %mm2, %mm2
+pxor %xmm2, %xmm2
+vpxor %xmm3, %xmm3, %xmm3
+vpxor %ymm3, %ymm3, %ymm3
+
+vxorps %xmm4, %xmm4, %xmm5
+vxorpd %xmm1, %xmm1, %xmm3
+vxorps %ymm4, %ymm4, %ymm5
+vxorpd %ymm1, %ymm1, %ymm3
+vpxor %xmm3, %xmm3, %xmm5
+vpxor %ymm3, %ymm3, %ymm5
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 83
+# CHECK-NEXT: Total Cycles: 34
+# CHECK-NEXT: Total uOps: 83
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 2.44
+# CHECK-NEXT: IPC: 2.44
+# CHECK-NEXT: Block RThroughput: 16.7
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.20 subl %eax, %eax
+# CHECK-NEXT: 1 1 0.20 subq %rax, %rax
+# CHECK-NEXT: 1 2 0.20 xorl %eax, %eax
+# CHECK-NEXT: 1 2 0.20 xorq %rax, %rax
+# CHECK-NEXT: 1 1 1.00 pcmpgtb %mm2, %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpgtd %mm2, %mm2
+# CHECK-NEXT: 1 1 1.00 pcmpgtw %mm2, %mm2
+# CHECK-NEXT: 1 1 0.50 pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: 1 3 1.00 pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.50 pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.50 vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 3 1.00 vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.50 vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.50 vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.50 vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 3 1.00 vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.50 vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.50 vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.50 vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 3 1.00 vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.50 vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.50 vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.50 vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 3 1.00 vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.50 vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.50 psubb %mm2, %mm2
+# CHECK-NEXT: 1 1 0.50 psubd %mm2, %mm2
+# CHECK-NEXT: 1 1 0.50 psubq %mm2, %mm2
+# CHECK-NEXT: 1 1 0.50 psubw %mm2, %mm2
+# CHECK-NEXT: 1 1 0.33 psubb %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.33 psubd %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.33 psubq %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.33 psubw %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.33 vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.33 vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.33 vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.33 vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.33 vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.33 vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.33 vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.33 vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.33 vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.33 vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.33 vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.33 vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.33 vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.33 vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.33 vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.33 andnps %xmm0, %xmm0
+# CHECK-NEXT: 1 1 0.33 andnpd %xmm1, %xmm1
+# CHECK-NEXT: 1 1 0.33 vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.33 vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 1 1 0.33 vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 1 1 0.33 vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 1 1 0.50 pandn %mm2, %mm2
+# CHECK-NEXT: 1 1 0.33 pandn %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.33 vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.33 vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: 1 1 0.33 vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: 1 1 0.33 vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.33 vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: 1 1 0.33 vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: 1 1 0.33 vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.33 xorps %xmm0, %xmm0
+# CHECK-NEXT: 1 1 0.33 xorpd %xmm1, %xmm1
+# CHECK-NEXT: 1 1 0.33 vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.33 vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 1 1 0.33 vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 1 1 0.33 vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 1 1 0.50 pxor %mm2, %mm2
+# CHECK-NEXT: 1 1 0.33 pxor %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.33 vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 1 0.33 vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 1 0.33 vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: 1 1 0.33 vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: 1 1 0.33 vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: 1 1 0.33 vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: 1 1 0.33 vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 1 0.33 vpxor %ymm3, %ymm3, %ymm5
+
+# CHECK: Register File statistics:
+# CHECK-NEXT: Total number of mappings created: 87
+# CHECK-NEXT: Max number of mappings used: 66
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ADLPPort00
+# CHECK-NEXT: [1] - ADLPPort01
+# CHECK-NEXT: [2] - ADLPPort02
+# CHECK-NEXT: [3] - ADLPPort03
+# CHECK-NEXT: [4] - ADLPPort04
+# CHECK-NEXT: [5] - ADLPPort05
+# CHECK-NEXT: [6] - ADLPPort06
+# CHECK-NEXT: [7] - ADLPPort07
+# CHECK-NEXT: [8] - ADLPPort08
+# CHECK-NEXT: [9] - ADLPPort09
+# CHECK-NEXT: [10] - ADLPPort10
+# CHECK-NEXT: [11] - ADLPPort11
+# CHECK-NEXT: [12] - ADLPPortInvalid
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: 27.00 26.00 - - - 27.00 1.00 - - - 2.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - subl %eax, %eax
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - subq %rax, %rax
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - xorl %eax, %eax
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - xorq %rax, %rax
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pcmpgtb %mm2, %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pcmpgtd %mm2, %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pcmpgtw %mm2, %mm2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - psubb %mm2, %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psubd %mm2, %mm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - psubq %mm2, %mm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - psubw %mm2, %mm2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - psubb %xmm2, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - psubd %xmm2, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - psubq %xmm2, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - psubw %xmm2, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - andnps %xmm0, %xmm0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - andnpd %xmm1, %xmm1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pandn %mm2, %mm2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - pandn %xmm2, %xmm2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - xorps %xmm0, %xmm0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - xorpd %xmm1, %xmm1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - pxor %mm2, %mm2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - pxor %xmm2, %xmm2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - vpxor %ymm3, %ymm3, %ymm5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123
+# CHECK-NEXT: Index 0123456789 0123456789
+
+# CHECK: [0,0] DeER . . . . . . . subl %eax, %eax
+# CHECK-NEXT: [0,1] D=eER. . . . . . . subq %rax, %rax
+# CHECK-NEXT: [0,2] D==eeER . . . . . . xorl %eax, %eax
+# CHECK-NEXT: [0,3] D====eeER . . . . . . xorq %rax, %rax
+# CHECK-NEXT: [0,4] DeE-----R . . . . . . pcmpgtb %mm2, %mm2
+# CHECK-NEXT: [0,5] D=eE----R . . . . . . pcmpgtd %mm2, %mm2
+# CHECK-NEXT: [0,6] .D=eE---R . . . . . . pcmpgtw %mm2, %mm2
+# CHECK-NEXT: [0,7] .DeE----R . . . . . . pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: [0,8] .D=eE---R . . . . . . pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: [0,9] .D==eeeER . . . . . . pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: [0,10] .D=====eER. . . . . . pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: [0,11] .D==eE---R. . . . . . vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,12] . D==eE--R. . . . . . vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,13] . D===eeeER . . . . . vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,14] . D======eER . . . . . vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,15] . D=======eER . . . . . vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,16] . D=======eER . . . . . vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,17] . D=======eeeER. . . . . vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,18] . D=======eE-R. . . . . vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,19] . D=======eE-R. . . . . vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,20] . D========eER. . . . . vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,21] . D=========eeeER . . . . vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,22] . D============eER . . . . vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,23] . D=============eER. . . . vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,24] . D============eER. . . . vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,25] . D============eeeER . . . vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,26] . D=============eE-R . . . vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,27] . DeE--------------R . . . psubb %mm2, %mm2
+# CHECK-NEXT: [0,28] . D=eE-------------R . . . psubd %mm2, %mm2
+# CHECK-NEXT: [0,29] . D==eE------------R . . . psubq %mm2, %mm2
+# CHECK-NEXT: [0,30] . D==eE-----------R . . . psubw %mm2, %mm2
+# CHECK-NEXT: [0,31] . D==eE-----------R . . . psubb %xmm2, %xmm2
+# CHECK-NEXT: [0,32] . D===eE----------R . . . psubd %xmm2, %xmm2
+# CHECK-NEXT: [0,33] . D=====eE--------R . . . psubq %xmm2, %xmm2
+# CHECK-NEXT: [0,34] . D======eE-------R . . . psubw %xmm2, %xmm2
+# CHECK-NEXT: [0,35] . D============eE-R . . . vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,36] . .D============eER . . . vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,37] . .D=============eER . . . vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,38] . .D==============eER . . . vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,39] . .D===============eER. . . vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,40] . .D================eER . . vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,41] . .D=================eER . . vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,42] . . D=================eER . . vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,43] . . D==================eER . . vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,44] . . D==================eER . . vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,45] . . D==================eER . . vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,46] . . D===================eER. . vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,47] . . D===================eER. . vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,48] . . D==================eER. . vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,49] . . D===================eER . vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,50] . . D===================eER . vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,51] . . DeE-------------------R . andnps %xmm0, %xmm0
+# CHECK-NEXT: [0,52] . . D===eE----------------R . andnpd %xmm1, %xmm1
+# CHECK-NEXT: [0,53] . . D====eE---------------R . vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: [0,54] . . D===eE---------------R . vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: [0,55] . . D====eE--------------R . vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: [0,56] . . D====eE--------------R . vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [0,57] . . D====eE--------------R . pandn %mm2, %mm2
+# CHECK-NEXT: [0,58] . . D=====eE-------------R . pandn %xmm2, %xmm2
+# CHECK-NEXT: [0,59] . . D==================eER . vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,60] . . D==================eER . vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,61] . . D=====eE-------------R . vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: [0,62] . . D====eE--------------R . vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: [0,63] . . D===================eER. vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,64] . . D=====eE--------------R. vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: [0,65] . . D====eE---------------R. vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: [0,66] . . .D==================eER. vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,67] . . .D=======eE-----------R. xorps %xmm0, %xmm0
+# CHECK-NEXT: [0,68] . . .D======eE------------R. xorpd %xmm1, %xmm1
+# CHECK-NEXT: [0,69] . . .D=======eE-----------R. vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: [0,70] . . .D========eE----------R. vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: [0,71] . . .D========eE----------R. vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: [0,72] . . . D========eE---------R. vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [0,73] . . . D========eE---------R. pxor %mm2, %mm2
+# CHECK-NEXT: [0,74] . . . D=========eE--------R. pxor %xmm2, %xmm2
+# CHECK-NEXT: [0,75] . . . D=================eER. vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,76] . . . D==================eER vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,77] . . . D==========eE--------R vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: [0,78] . . . D=========eE--------R vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: [0,79] . . . D==========eE-------R vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: [0,80] . . . D========eE---------R vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: [0,81] . . . D==========eE-------R vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,82] . . . D===========eE------R vpxor %ymm3, %ymm3, %ymm5
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 subl %eax, %eax
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 subq %rax, %rax
+# CHECK-NEXT: 2. 1 3.0 0.0 0.0 xorl %eax, %eax
+# CHECK-NEXT: 3. 1 5.0 0.0 0.0 xorq %rax, %rax
+# CHECK-NEXT: 4. 1 1.0 1.0 5.0 pcmpgtb %mm2, %mm2
+# CHECK-NEXT: 5. 1 2.0 0.0 4.0 pcmpgtd %mm2, %mm2
+# CHECK-NEXT: 6. 1 2.0 0.0 3.0 pcmpgtw %mm2, %mm2
+# CHECK-NEXT: 7. 1 1.0 1.0 4.0 pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: 8. 1 2.0 0.0 3.0 pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: 9. 1 3.0 0.0 0.0 pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: 10. 1 6.0 0.0 0.0 pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: 11. 1 3.0 3.0 3.0 vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 12. 1 3.0 0.0 2.0 vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 13. 1 4.0 0.0 0.0 vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 14. 1 7.0 0.0 0.0 vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 15. 1 8.0 0.0 0.0 vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 16. 1 8.0 0.0 0.0 vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 17. 1 8.0 0.0 0.0 vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 18. 1 8.0 1.0 1.0 vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 19. 1 8.0 1.0 1.0 vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 20. 1 9.0 0.0 0.0 vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 21. 1 10.0 0.0 0.0 vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 22. 1 13.0 0.0 0.0 vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 23. 1 14.0 0.0 0.0 vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 24. 1 13.0 0.0 0.0 vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 25. 1 13.0 0.0 0.0 vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 26. 1 14.0 1.0 1.0 vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 27. 1 1.0 1.0 14.0 psubb %mm2, %mm2
+# CHECK-NEXT: 28. 1 2.0 0.0 13.0 psubd %mm2, %mm2
+# CHECK-NEXT: 29. 1 3.0 0.0 12.0 psubq %mm2, %mm2
+# CHECK-NEXT: 30. 1 3.0 0.0 11.0 psubw %mm2, %mm2
+# CHECK-NEXT: 31. 1 3.0 0.0 11.0 psubb %xmm2, %xmm2
+# CHECK-NEXT: 32. 1 4.0 0.0 10.0 psubd %xmm2, %xmm2
+# CHECK-NEXT: 33. 1 6.0 1.0 8.0 psubq %xmm2, %xmm2
+# CHECK-NEXT: 34. 1 7.0 0.0 7.0 psubw %xmm2, %xmm2
+# CHECK-NEXT: 35. 1 13.0 1.0 1.0 vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 36. 1 13.0 0.0 0.0 vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 37. 1 14.0 0.0 0.0 vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 38. 1 15.0 0.0 0.0 vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 39. 1 16.0 0.0 0.0 vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 40. 1 17.0 0.0 0.0 vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 41. 1 18.0 0.0 0.0 vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 42. 1 18.0 0.0 0.0 vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 43. 1 19.0 0.0 0.0 vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 44. 1 19.0 0.0 0.0 vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 45. 1 19.0 0.0 0.0 vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 46. 1 20.0 1.0 0.0 vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 47. 1 20.0 1.0 0.0 vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 48. 1 19.0 1.0 0.0 vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 49. 1 20.0 2.0 0.0 vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 50. 1 20.0 2.0 0.0 vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 51. 1 1.0 1.0 19.0 andnps %xmm0, %xmm0
+# CHECK-NEXT: 52. 1 4.0 4.0 16.0 andnpd %xmm1, %xmm1
+# CHECK-NEXT: 53. 1 5.0 0.0 15.0 vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 54. 1 4.0 0.0 15.0 vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 55. 1 5.0 0.0 14.0 vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 56. 1 5.0 0.0 14.0 vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 57. 1 5.0 5.0 14.0 pandn %mm2, %mm2
+# CHECK-NEXT: 58. 1 6.0 0.0 13.0 pandn %xmm2, %xmm2
+# CHECK-NEXT: 59. 1 19.0 2.0 0.0 vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 60. 1 19.0 0.0 0.0 vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 61. 1 6.0 0.0 13.0 vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: 62. 1 5.0 0.0 14.0 vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: 63. 1 20.0 0.0 0.0 vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 64. 1 6.0 0.0 14.0 vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: 65. 1 5.0 0.0 15.0 vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: 66. 1 19.0 0.0 0.0 vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 67. 1 8.0 8.0 11.0 xorps %xmm0, %xmm0
+# CHECK-NEXT: 68. 1 7.0 3.0 12.0 xorpd %xmm1, %xmm1
+# CHECK-NEXT: 69. 1 8.0 3.0 11.0 vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 70. 1 9.0 1.0 10.0 vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 71. 1 9.0 0.0 10.0 vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 72. 1 9.0 0.0 9.0 vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 73. 1 9.0 6.0 9.0 pxor %mm2, %mm2
+# CHECK-NEXT: 74. 1 10.0 1.0 8.0 pxor %xmm2, %xmm2
+# CHECK-NEXT: 75. 1 18.0 0.0 0.0 vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 76. 1 19.0 0.0 0.0 vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 77. 1 11.0 11.0 8.0 vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: 78. 1 10.0 1.0 8.0 vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: 79. 1 11.0 11.0 7.0 vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: 80. 1 9.0 0.0 9.0 vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: 81. 1 11.0 1.0 7.0 vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 82. 1 12.0 2.0 6.0 vpxor %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 9.4 1.0 5.0 <total>
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