[PATCH] D132080: RegisterClassInfo: Fix CSR cache invalidation

[Matthias Braun via Phabricator via llvm-commits]

MatzeB added a comment.

Adding PowerPC and XCore test authors. I update the tests to match the new output, I'm not sure if they still test what they are intended to test. I would recomment rewritinging them into .mir tests that run a single test and do not depend on a particular register allocation if necessary!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132080/new/

https://reviews.llvm.org/D132080