[PATCH] D132000: [RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 17 09:50:37 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG550fab53e1da: [RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1). (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D132000/new/
https://reviews.llvm.org/D132000
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/double-select-fcmp.ll
llvm/test/CodeGen/RISCV/float-select-fcmp.ll
llvm/test/CodeGen/RISCV/half-select-fcmp.ll
Index: llvm/test/CodeGen/RISCV/half-select-fcmp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/half-select-fcmp.ll
+++ llvm/test/CodeGen/RISCV/half-select-fcmp.ll
@@ -258,8 +258,7 @@
; CHECK-LABEL: select_fcmp_uge_negone_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: fle.h a0, fa0, fa1
-; CHECK-NEXT: xori a0, a0, 1
-; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: ret
%1 = fcmp ugt half %a, %b
%2 = select i1 %1, i32 -1, i32 0
@@ -270,9 +269,7 @@
; CHECK-LABEL: select_fcmp_uge_1_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fle.h a0, fa0, fa1
-; CHECK-NEXT: xori a0, a0, 1
-; CHECK-NEXT: li a1, 2
-; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp ugt half %a, %b
%2 = select i1 %1, i32 1, i32 2
Index: llvm/test/CodeGen/RISCV/float-select-fcmp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/float-select-fcmp.ll
+++ llvm/test/CodeGen/RISCV/float-select-fcmp.ll
@@ -258,8 +258,7 @@
; CHECK-LABEL: select_fcmp_uge_negone_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: fle.s a0, fa0, fa1
-; CHECK-NEXT: xori a0, a0, 1
-; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: ret
%1 = fcmp ugt float %a, %b
%2 = select i1 %1, i32 -1, i32 0
@@ -270,9 +269,7 @@
; CHECK-LABEL: select_fcmp_uge_1_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fle.s a0, fa0, fa1
-; CHECK-NEXT: xori a0, a0, 1
-; CHECK-NEXT: li a1, 2
-; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp ugt float %a, %b
%2 = select i1 %1, i32 1, i32 2
Index: llvm/test/CodeGen/RISCV/double-select-fcmp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/double-select-fcmp.ll
+++ llvm/test/CodeGen/RISCV/double-select-fcmp.ll
@@ -258,8 +258,7 @@
; CHECK-LABEL: select_fcmp_uge_negone_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: fle.d a0, fa0, fa1
-; CHECK-NEXT: xori a0, a0, 1
-; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: ret
%1 = fcmp ugt double %a, %b
%2 = select i1 %1, i32 -1, i32 0
@@ -270,9 +269,7 @@
; CHECK-LABEL: select_fcmp_uge_1_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fle.d a0, fa0, fa1
-; CHECK-NEXT: xori a0, a0, 1
-; CHECK-NEXT: li a1, 2
-; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp ugt double %a, %b
%2 = select i1 %1, i32 1, i32 2
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8306,6 +8306,11 @@
CCVal = ISD::getSetCCInverse(CCVal, SetCCOpVT);
NewLHS =
DAG.getSetCC(SDLoc(N1), VT, N1.getOperand(0), N1.getOperand(1), CCVal);
+ } else if (N1.getOpcode() == ISD::XOR && isOneConstant(N1.getOperand(1)) &&
+ N1.getOperand(0).getOpcode() == ISD::SETCC) {
+ // (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
+ // Since setcc returns a bool the xor is equivalent to 1-setcc.
+ NewLHS = N1.getOperand(0);
} else
return SDValue();
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