[llvm] d27c147 - [RISCV] Allow lowerSELECT to fold integer setcc with FP select.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-08-16T21:28:54-07:00
New Revision: d27c147aaa8fea0d3b438ba9e51b497a621ecf1e

URL: https://github.com/llvm/llvm-project/commit/d27c147aaa8fea0d3b438ba9e51b497a621ecf1e
DIFF: https://github.com/llvm/llvm-project/commit/d27c147aaa8fea0d3b438ba9e51b497a621ecf1e.diff

LOG: [RISCV] Allow lowerSELECT to fold integer setcc with FP select.

We'd pick it up in DAG combine later even if we didn't handle it here.
No test changes because we get it in DAG combine anyway.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6a6e4c1119ab..69f305303e0f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3990,13 +3990,12 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
     return DAG.getNode(ISD::VSELECT, DL, VT, CondSplat, TrueV, FalseV);
   }
 
-  // If the result type is XLenVT and CondV is the output of a SETCC node
-  // which also operated on XLenVT inputs, then merge the SETCC node into the
-  // lowered RISCVISD::SELECT_CC to take advantage of the integer
-  // compare+branch instructions. i.e.:
+  // If the CondV is the output of a SETCC node which operates on XLenVT inputs,
+  // then merge the SETCC node into the lowered RISCVISD::SELECT_CC to take
+  // advantage of the integer compare+branch instructions. i.e.:
   // (select (setcc lhs, rhs, cc), truev, falsev)
   // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev)
-  if (VT == XLenVT && CondV.getOpcode() == ISD::SETCC &&
+  if (CondV.getOpcode() == ISD::SETCC &&
       CondV.getOperand(0).getSimpleValueType() == XLenVT) {
     SDValue LHS = CondV.getOperand(0);
     SDValue RHS = CondV.getOperand(1);