[PATCH] D130222: [RISCV] Add scheduling class for vector pseudo segment instructions.

[Monk Chiang via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0af4651c0fc7: [RISCV] Add scheduling class for vector pseudo segment instructions. (authored by monkchiang).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130222/new/

https://reviews.llvm.org/D130222

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

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