[llvm] 2dfa4b6 - Revert "[RISCV] Use setcc's original SDLoc when inverting it in performSUBCombine."
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 16 15:47:09 PDT 2022
Author: Craig Topper
Date: 2022-08-16T15:47:01-07:00
New Revision: 2dfa4b6475f85c9f795647513dbd5f206144c23a
URL: https://github.com/llvm/llvm-project/commit/2dfa4b6475f85c9f795647513dbd5f206144c23a
DIFF: https://github.com/llvm/llvm-project/commit/2dfa4b6475f85c9f795647513dbd5f206144c23a.diff
LOG: Revert "[RISCV] Use setcc's original SDLoc when inverting it in performSUBCombine."
This reverts commit 1380b21ceba7b7b19e960da5df68dcd5cba1b091.
I mixed up N0 and N1 and didn't do what I intended.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 11ee31a033d9..937491f99212 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8298,7 +8298,7 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {
// and may increase the number of constants we need.
if (ImmValMinus1.isSignedIntN(12)) {
CCVal = ISD::getSetCCInverse(CCVal, SetCCOpVT);
- SDValue NewN0 = DAG.getSetCC(SDLoc(N0), VT, N1.getOperand(0),
+ SDValue NewN0 = DAG.getSetCC(SDLoc(N), VT, N1.getOperand(0),
N1.getOperand(1), CCVal);
SDValue NewN1 = DAG.getConstant(ImmValMinus1, SDLoc(N), VT);
return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewN0, NewN1);
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