[PATCH] D131962: [RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:146
 multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1,
-                        bit HWEncodingHigh = 0> {
+                        bit HWEncodingHigh = 0, bit Constant = false> {
   // There is no special encoding for 16 bit subregs, these are not real
----------------
Not used any more


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:227
 defm SGPR_NULL : SIRegLoHi16 <"null", 0>;
 defm SGPR_NULL_HI : SIRegLoHi16 <"", 0>;
+} // isConstant = true
----------------
This wasn't constant before


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:242
 defm SRC_PRIVATE_LIMIT : SIRegLoHi16<"src_private_limit", 238>;
 defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>;
+}
----------------
This wasn't constant before


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Comment at: llvm/lib/Target/Mips/MipsRegisterInfo.td:87
   // General Purpose Registers
-  def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
+  def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]> { let isConstant = true; }
   def AT   : MipsGPRReg< 1, "1">,    DwarfRegNum<[1]>;
----------------
let ... in gets used for SubRegIndices later


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131962/new/

https://reviews.llvm.org/D131962