[PATCH] D131229: [LoongArch] Add codegen support for atomicrmw xchg operation on LA32

[Gong LingQin via Phabricator via llvm-commits]

gonglingqin added inline comments.


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Comment at: llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp:111
+  //   beq scratch, zero, loop
+  BuildMI(LoopMBB, DL, TII->get(LoongArch::DBAR)).addImm(0);
+  BuildMI(LoopMBB, DL, TII->get(LoongArch::LL_W), DestReg)
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xen0n wrote:
> In GCC they apparently used `dbar 0x700` for open-coded atomic CAS templates, that seemed to result from a hardware erratum. If in a future hardware iteration this `dbar` is going to become unnecessary, coding `dbar 0x700` here might be a good idea.
> 
> You may confirm with the CPU designers and the GCC team for this.
Thanks, this issue is being confirmed.


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Comment at: llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll:26
+; LA32-NEXT:    srl.w $a0, $a4, $a0
+; LA32-NEXT:    jirl $zero, $ra, 0
+;
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xen0n wrote:
> Have to rebase...
Thanks for your reminding. I will rebase this patch and D131228.


Repository:
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  https://reviews.llvm.org/D131229/new/

https://reviews.llvm.org/D131229