[PATCH] D131773: [AArch64] Add support for 256-bit non temporal loads
Zain Jaffal via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 16 00:47:40 PDT 2022
zjaffal marked 5 inline comments as done.
zjaffal added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:20391
+ if (LoadNode->isNonTemporal() && MemVT.getSizeInBits() == 256u &&
+ EC.isKnownEven() &&
+ ((MemVT.getScalarSizeInBits() == 8u ||
----------------
dmgreen wrote:
> Why is EC.isKnownEven needed?
I followed the same code that is used to lower `STNP` but I think it is not really necessary here.
I think we can remove it.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D131773/new/
https://reviews.llvm.org/D131773
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