[PATCH] D131343: [RISC-V][HWASAN] Add support for lowering HWASAN intrinsic for RISC-V

[Vitaly Buka via Phabricator via llvm-commits]

vitalybuka accepted this revision.
vitalybuka added a comment.
This revision is now accepted and ready to land.

In D131343#3722882 <https://reviews.llvm.org/D131343#3722882>, @smd wrote:

> In D131343#3719618 <https://reviews.llvm.org/D131343#3719618>, @vitalybuka wrote:
>
>> RISCVAsmPrinter needs a test for changes in this patch.
>
> The requested tests have been added as part of D131344 <https://reviews.llvm.org/D131344>.
> Thanks.

llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll ?
the test essentially validates LowerHWASAN_CHECK_MEMACCESS, and does not relies on the rest of D131344 <https://reviews.llvm.org/D131344>
So the test needs to be moved from D131344 <https://reviews.llvm.org/D131344> into this patch.

With moved test LGTM in general.
But I have no experience with RISCV, so I didn't look into details of emitted code.



================
Comment at: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:120
+
   if (!lowerRISCVMachineInstrToMCInst(MI, TmpInst, *this))
     EmitToStreamer(*OutStreamer, TmpInst);
----------------
This "if" looks to random here?
File structure is very different from AArch64 version, so not sure if this is the best place for the code.



Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131343/new/

https://reviews.llvm.org/D131343