[PATCH] D131729: [RISCV] Move xori creation for scalar setccs to lowering.

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3633
+          SDValue SetCC = DAG.getSetCC(
+              DL, VT, LHS, DAG.getConstant(Imm + 1, DL, OpVT), CCVal);
+          return DAG.getLogicalNOT(DL, SetCC, VT);
----------------
I'm not following something here.  You're increment the rhs of a GT or UGT in the manner I'd expect to apply to a GE or UGE, but also not changing the condition code?

This looks like a dag combine btw, why does this need to be done during lowering at all?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3638
+
+      // Swap the operands.
+      return DAG.getSetCC(DL, VT, RHS, LHS, CCVal);
----------------
Why is swapping the operands correct here?  I don't follow?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8338
+  if (isNullConstant(N0) && N1.getOpcode() == ISD::XOR &&
+      N1.getOperand(0).getOpcode() == ISD::SETCC &&
+      isOneConstant(N1.getOperand(1))) {
----------------
I think the setcc here is only providing the 0 or 1 fact for N1, is there any way we can generalize?  (e.g. known bits?)  If so, we can probably separate and test separately.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131729/new/

https://reviews.llvm.org/D131729