[PATCH] D131093: [LV] Restructure isPredicatedInst and isScalarWithPredication (w/a fix for uniform mem ops)

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Aug 15 09:00:08 PDT 2022


reames added inline comments.


================
Comment at: llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll:585
 ;
 ; TF-SCALABLE-LABEL: @uniform_load_unaligned(
 ; TF-SCALABLE-NEXT:  entry:
----------------
david-arm wrote:
> I tried vectorising these tests with SVE (`opt -loop-vectorize -mattr=+sve -mtriple=aarch64-linux-gnu < ../llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll -S`) and it already works today without this patch. In fact it works both and without tail-folding enabled. Do you know why RISC-V is different to SVE and why this patch is needed to vectorise?
This is just a guess, but... aarch64 and riscv have different sets of legal scatters and gathers.  The widening cost currently bails for illegal scatters we don't *know* we can scalarize.  If aarch64 was picking scatter, but then optimizing to a scalarization, we'd see something like this.  

This doesn't explain why aarch64 is able to handle unaligned uniform loads and riscv isn't though.  I didn't dig into that in detail.

This type of difference isn't particularly surprising though.  This code is delicate and the same result can be reached through multiple event chains.  That doesn't mean we shouldn't fix issues when we find them.  


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https://reviews.llvm.org/D131093



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