[PATCH] D131260: [DAG] select Cond, -1, C --> or (sext Cond), C if Cond is MVT::i1

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll:1212
+; CHECK-PWR8-NEXT:    isel r3, 0, r3, 4*cr1+eq
 ; CHECK-PWR8-NEXT:    blr
   %t1 = fcmp nnan oeq double %b, %a
----------------
RKSimon wrote:
> regression?
I have no idea, but  think so.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D131260/new/

https://reviews.llvm.org/D131260