[llvm] 3a73133 - [DAG] canCreateUndefOrPoison - add freeze(sign_extend_inreg(x,vt)) -> sign_extend_inreg(freeze(x),vt) support

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-08-15T12:18:59+01:00
New Revision: 3a731332178513bb11b50f7a3212845a77023d26

URL: https://github.com/llvm/llvm-project/commit/3a731332178513bb11b50f7a3212845a77023d26
DIFF: https://github.com/llvm/llvm-project/commit/3a731332178513bb11b50f7a3212845a77023d26.diff

LOG: [DAG] canCreateUndefOrPoison - add freeze(sign_extend_inreg(x,vt)) -> sign_extend_inreg(freeze(x),vt) support

Guaranteed not to create undef/poison

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/test/CodeGen/RISCV/iabs.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 36dc3f548d5d..8e9d49100300 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4580,6 +4580,7 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
   case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND:
   case ISD::TRUNCATE:
+  case ISD::SIGN_EXTEND_INREG:
   case ISD::BITCAST:
     return false;
 

diff  --git a/llvm/test/CodeGen/RISCV/iabs.ll b/llvm/test/CodeGen/RISCV/iabs.ll
index 8434f886624c..2fa73bd85c32 100644
--- a/llvm/test/CodeGen/RISCV/iabs.ll
+++ b/llvm/test/CodeGen/RISCV/iabs.ll
@@ -727,9 +727,9 @@ define i64 @zext_abs32(i32 %x) {
 ;
 ; RV64ZBB-LABEL: zext_abs32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    sext.w a0, a0
-; RV64ZBB-NEXT:    negw a1, a0
-; RV64ZBB-NEXT:    max a0, a0, a1
+; RV64ZBB-NEXT:    sext.w a1, a0
+; RV64ZBB-NEXT:    negw a0, a0
+; RV64ZBB-NEXT:    max a0, a1, a0
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: zext_abs32: