[PATCH] D131551: [RISCV] Fold scalable binary integer vector op and vector select op to RVV VL Op.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8326
+    OP_CASE(MUL, 1)
+    OP_CASE(MULHS, 1)
+    OP_CASE(MULHU, 1)
----------------
1 is also not the identify value for MULHS/MULHU. This returns the high half of the product. MULHU(a, 1) produces 0 since the high product is 0. MULHS(a, 1) is a vector filled with the sigh bit of a.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131551/new/

https://reviews.llvm.org/D131551