[PATCH] D131551: [RISCV] Fold scalable binary integer vector op and vector select op to RVV VL Op.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:981
+                         ISD::UREM, ISD::SREM});
+  if (Subtarget.hasVInstructions() && !Subtarget.hasStdExtZbb())
+    setTargetDAGCombine({ISD::UMIN, ISD::UMAX});
----------------
Why !hasStdExtZbb()?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8347
+
+  SDValue VL =
+      DAG.getConstant(RISCV::VLMaxSentinel, SDLoc(N), Subtarget.getXLenVT());
----------------
VLMaxSentinel is not to be used in SelectionDAG anymore. Use `getRegister(RISCV::X0`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131551/new/

https://reviews.llvm.org/D131551