[PATCH] D106675: [X86] Freeze shl(x,1) -> add(x,x) vector fold (PR50468)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 452536.
RKSimon retitled this revision from "[WIP][X86] Freeze shl(x,1) -> add(x,x) vector fold (PR50468)" to "[X86] Freeze shl(x,1) -> add(x,x) vector fold (PR50468)".
RKSimon added a comment.

Move the (shl V, 1) -> (add (freeze V),(freeze V)) fold inside LowerShiftByScalarImmediate so it's only attempted on legal types.

With the recently improved freeze combines this appears to fix most of the regressions we were seeing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106675/new/

https://reviews.llvm.org/D106675

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/combine-mul.ll
  llvm/test/CodeGen/X86/freeze-binary.ll
  llvm/test/CodeGen/X86/oddsubvector.ll
  llvm/test/CodeGen/X86/rotate_vec.ll
  llvm/test/CodeGen/X86/sdiv_fix_sat.ll
  llvm/test/CodeGen/X86/udiv_fix_sat.ll
  llvm/test/CodeGen/X86/vector-fshr-128.ll
  llvm/test/CodeGen/X86/vector-fshr-256.ll
  llvm/test/CodeGen/X86/vector-fshr-512.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
  llvm/test/CodeGen/X86/vector-mulfix-legalize.ll
  llvm/test/CodeGen/X86/vector-shift-shl-128.ll
  llvm/test/CodeGen/X86/vector-shift-shl-256.ll

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