[llvm] f159695 - [AArch64] Fix signed integer overflow in CSINC case
Vitaly Buka via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 13 13:12:19 PDT 2022
Author: Vitaly Buka
Date: 2022-08-13T13:12:09-07:00
New Revision: f1596952f9ff9fcfd5e16c9c8ec4d528e5680e2c
URL: https://github.com/llvm/llvm-project/commit/f1596952f9ff9fcfd5e16c9c8ec4d528e5680e2c
DIFF: https://github.com/llvm/llvm-project/commit/f1596952f9ff9fcfd5e16c9c8ec4d528e5680e2c.diff
LOG: [AArch64] Fix signed integer overflow in CSINC case
https://lab.llvm.org/staging/#/builders/224/builds/2/steps/16/logs/stdio
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D131815
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/arm64-csel.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 771b1b40a8e6..92e64301b631 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8235,8 +8235,11 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
Swap = true;
}
}
- // 64-bit check whether we can use CSINC.
- } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
+ // 64-bit check whether we can use CSINC. To avoid signed integer
+ // overflow the condition ignores wrap around, which is already
+ // handled by CSINV above.
+ } else if (1 ==
+ std::max(TrueVal, FalseVal) - std::min(TrueVal, FalseVal)) {
Opcode = AArch64ISD::CSINC;
if (TrueVal > FalseVal) {
diff --git a/llvm/test/CodeGen/AArch64/arm64-csel.ll b/llvm/test/CodeGen/AArch64/arm64-csel.ll
index 35fcc88d908b..cbb367db38f2 100644
--- a/llvm/test/CodeGen/AArch64/arm64-csel.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-csel.ll
@@ -264,6 +264,34 @@ entry:
ret i64 %.
}
+; Regression test for TrueVal + 1 overflow
+define i64 @foo18_overflow1(i64 %a, i64 %b) nounwind readnone optsize ssp {
+; CHECK-LABEL: foo18_overflow1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: cmp x0, x1
+; CHECK-NEXT: mov x8, #9223372036854775807
+; CHECK-NEXT: csel x0, x8, xzr, gt
+; CHECK-NEXT: ret
+entry:
+ %cmp = icmp sgt i64 %a, %b
+ %. = select i1 %cmp, i64 9223372036854775807, i64 0
+ ret i64 %.
+}
+
+; Regression test for FalseVal + 1 overflow
+define i64 @foo18_overflow2(i64 %a, i64 %b) nounwind readnone optsize ssp {
+; CHECK-LABEL: foo18_overflow2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: cmp x0, x1
+; CHECK-NEXT: mov x8, #9223372036854775807
+; CHECK-NEXT: csel x0, xzr, x8, gt
+; CHECK-NEXT: ret
+entry:
+ %cmp = icmp sgt i64 %a, %b
+ %. = select i1 %cmp, i64 0, i64 9223372036854775807
+ ret i64 %.
+}
+
define i64 @foo19(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: foo19:
; CHECK: // %bb.0: // %entry
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