[llvm] 37db283 - [RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-08-12T22:21:05-07:00
New Revision: 37db283362232eaa0a57d452fee45cf2b147f356

URL: https://github.com/llvm/llvm-project/commit/37db283362232eaa0a57d452fee45cf2b147f356
DIFF: https://github.com/llvm/llvm-project/commit/37db283362232eaa0a57d452fee45cf2b147f356.diff

LOG: [RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.

We were incorrectly checking that it returned an implicaton result,
not that the implication result itself was true.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
index 5b51bca2f3782..5c12d3304557b 100644
--- a/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
@@ -73,7 +73,7 @@ bool RISCVCodeGenPrepare::visitZExtInst(ZExtInst &ZExt) {
   // This often occurs with widened induction variables.
   if (isImpliedByDomCondition(ICmpInst::ICMP_SGE, Src,
                               Constant::getNullValue(Src->getType()), &ZExt,
-                              *DL)) {
+                              *DL).value_or(false)) {
     auto *SExt = new SExtInst(Src, ZExt.getType(), "", &ZExt);
     SExt->takeName(&ZExt);
     SExt->setDebugLoc(ZExt.getDebugLoc());
@@ -139,7 +139,7 @@ bool RISCVCodeGenPrepare::visitAnd(BinaryOperator &BO) {
   // And mask constant.
   if (!isImpliedByDomCondition(ICmpInst::ICMP_SGE, LHSSrc,
                                Constant::getNullValue(LHSSrc->getType()),
-                               LHS, *DL))
+                               LHS, *DL).value_or(false))
     return false;
 
   // Sign extend the constant and replace the And operand.