[PATCH] D131551: [RISCV] Add binary mask pattern for vector integer binary instructions.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added a comment.

In D131551#3713084 <https://reviews.llvm.org/D131551#3713084>, @craig.topper wrote:

> We've been discussing doing this as a post isel peephole or a DAG combine in D130442 <https://reviews.llvm.org/D130442>. That should have much less impact on the size of the generated isel table.
>
> It might not be a good idea to do this fold without checking that the select is the only user of binary op. If it's not the only user you'll duplicate the binary op and there will be a masked and unmasked version. This can increase register pressure and use more execution resources.

Thanks for your advice, I swtich to the DAG combiner. And I do not support fixed vector in this revision as I have not finished its test cases. I will add anothe revision to make it.


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https://reviews.llvm.org/D131551