[llvm] 13c1e7a - [PowerPC] Fix test case changed by "Add XXEVAL TD pattern" [NFC]
Ting Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 11 23:57:20 PDT 2022
Author: Ting Wang
Date: 2022-08-12T02:56:54-04:00
New Revision: 13c1e7a8aadbbe796051cb35ff41acff89d2395c
URL: https://github.com/llvm/llvm-project/commit/13c1e7a8aadbbe796051cb35ff41acff89d2395c
DIFF: https://github.com/llvm/llvm-project/commit/13c1e7a8aadbbe796051cb35ff41acff89d2395c.diff
LOG: [PowerPC] Fix test case changed by "Add XXEVAL TD pattern" [NFC]
Added:
Modified:
llvm/test/CodeGen/PowerPC/vector-reduce-or.ll
llvm/test/CodeGen/PowerPC/vector-reduce-xor.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/vector-reduce-or.ll b/llvm/test/CodeGen/PowerPC/vector-reduce-or.ll
index eb884d6f12d8..30a6fba52fcb 100644
--- a/llvm/test/CodeGen/PowerPC/vector-reduce-or.ll
+++ b/llvm/test/CodeGen/PowerPC/vector-reduce-or.ll
@@ -74,8 +74,8 @@ define dso_local i32 @v4i32(<4 x i32> %a) local_unnamed_addr #0 {
; PWR10LE-NEXT: xxswapd v3, v2
; PWR10LE-NEXT: li r3, 0
; PWR10LE-NEXT: xxlor vs0, v2, v3
-; PWR10LE-NEXT: xxspltw vs1, vs0, 2
-; PWR10LE-NEXT: xxlor v2, vs0, vs1
+; PWR10LE-NEXT: xxspltw vs0, vs0, 2
+; PWR10LE-NEXT: xxeval v2, v2, v3, vs0, 127
; PWR10LE-NEXT: vextuwrx r3, r3, v2
; PWR10LE-NEXT: blr
;
@@ -84,8 +84,8 @@ define dso_local i32 @v4i32(<4 x i32> %a) local_unnamed_addr #0 {
; PWR10BE-NEXT: xxswapd v3, v2
; PWR10BE-NEXT: li r3, 0
; PWR10BE-NEXT: xxlor vs0, v2, v3
-; PWR10BE-NEXT: xxspltw vs1, vs0, 1
-; PWR10BE-NEXT: xxlor v2, vs0, vs1
+; PWR10BE-NEXT: xxspltw vs0, vs0, 1
+; PWR10BE-NEXT: xxeval v2, v2, v3, vs0, 127
; PWR10BE-NEXT: vextuwlx r3, r3, v2
; PWR10BE-NEXT: blr
entry:
@@ -120,10 +120,10 @@ define dso_local i32 @v8i32(<8 x i32> %a) local_unnamed_addr #0 {
; PWR10LE: # %bb.0: # %entry
; PWR10LE-NEXT: xxlor vs0, v2, v3
; PWR10LE-NEXT: li r3, 0
-; PWR10LE-NEXT: xxswapd v2, vs0
-; PWR10LE-NEXT: xxlor vs0, vs0, v2
-; PWR10LE-NEXT: xxspltw vs1, vs0, 2
-; PWR10LE-NEXT: xxlor v2, vs0, vs1
+; PWR10LE-NEXT: xxswapd v4, vs0
+; PWR10LE-NEXT: xxeval vs1, v2, v3, v4, 127
+; PWR10LE-NEXT: xxspltw vs1, vs1, 2
+; PWR10LE-NEXT: xxeval v2, vs0, v4, vs1, 127
; PWR10LE-NEXT: vextuwrx r3, r3, v2
; PWR10LE-NEXT: blr
;
@@ -131,10 +131,10 @@ define dso_local i32 @v8i32(<8 x i32> %a) local_unnamed_addr #0 {
; PWR10BE: # %bb.0: # %entry
; PWR10BE-NEXT: xxlor vs0, v2, v3
; PWR10BE-NEXT: li r3, 0
-; PWR10BE-NEXT: xxswapd v2, vs0
-; PWR10BE-NEXT: xxlor vs0, vs0, v2
-; PWR10BE-NEXT: xxspltw vs1, vs0, 1
-; PWR10BE-NEXT: xxlor v2, vs0, vs1
+; PWR10BE-NEXT: xxswapd v4, vs0
+; PWR10BE-NEXT: xxeval vs1, v2, v3, v4, 127
+; PWR10BE-NEXT: xxspltw vs1, vs1, 1
+; PWR10BE-NEXT: xxeval v2, vs0, v4, vs1, 127
; PWR10BE-NEXT: vextuwlx r3, r3, v2
; PWR10BE-NEXT: blr
entry:
@@ -171,27 +171,27 @@ define dso_local i32 @v16i32(<16 x i32> %a) local_unnamed_addr #0 {
;
; PWR10LE-LABEL: v16i32:
; PWR10LE: # %bb.0: # %entry
-; PWR10LE-NEXT: xxlor vs0, v3, v5
; PWR10LE-NEXT: xxlor vs1, v2, v4
+; PWR10LE-NEXT: xxlor vs0, v3, v5
; PWR10LE-NEXT: li r3, 0
-; PWR10LE-NEXT: xxlor vs0, vs1, vs0
-; PWR10LE-NEXT: xxswapd v2, vs0
-; PWR10LE-NEXT: xxlor vs0, vs0, v2
-; PWR10LE-NEXT: xxspltw vs1, vs0, 2
-; PWR10LE-NEXT: xxlor v2, vs0, vs1
+; PWR10LE-NEXT: xxeval vs2, vs1, v3, v5, 127
+; PWR10LE-NEXT: xxswapd v2, vs2
+; PWR10LE-NEXT: xxeval vs0, vs1, vs0, v2, 127
+; PWR10LE-NEXT: xxspltw vs0, vs0, 2
+; PWR10LE-NEXT: xxeval v2, vs2, v2, vs0, 127
; PWR10LE-NEXT: vextuwrx r3, r3, v2
; PWR10LE-NEXT: blr
;
; PWR10BE-LABEL: v16i32:
; PWR10BE: # %bb.0: # %entry
-; PWR10BE-NEXT: xxlor vs0, v3, v5
; PWR10BE-NEXT: xxlor vs1, v2, v4
+; PWR10BE-NEXT: xxlor vs0, v3, v5
; PWR10BE-NEXT: li r3, 0
-; PWR10BE-NEXT: xxlor vs0, vs1, vs0
-; PWR10BE-NEXT: xxswapd v2, vs0
-; PWR10BE-NEXT: xxlor vs0, vs0, v2
-; PWR10BE-NEXT: xxspltw vs1, vs0, 1
-; PWR10BE-NEXT: xxlor v2, vs0, vs1
+; PWR10BE-NEXT: xxeval vs2, vs1, v3, v5, 127
+; PWR10BE-NEXT: xxswapd v2, vs2
+; PWR10BE-NEXT: xxeval vs0, vs1, vs0, v2, 127
+; PWR10BE-NEXT: xxspltw vs0, vs0, 1
+; PWR10BE-NEXT: xxeval v2, vs2, v2, vs0, 127
; PWR10BE-NEXT: vextuwlx r3, r3, v2
; PWR10BE-NEXT: blr
entry:
@@ -260,16 +260,16 @@ define dso_local i64 @v4i64(<4 x i64> %a) local_unnamed_addr #0 {
; PWR10LE-LABEL: v4i64:
; PWR10LE: # %bb.0: # %entry
; PWR10LE-NEXT: xxlor vs0, v2, v3
-; PWR10LE-NEXT: xxswapd v2, vs0
-; PWR10LE-NEXT: xxlor vs0, vs0, v2
+; PWR10LE-NEXT: xxswapd v4, vs0
+; PWR10LE-NEXT: xxeval vs0, v2, v3, v4, 127
; PWR10LE-NEXT: mfvsrld r3, vs0
; PWR10LE-NEXT: blr
;
; PWR10BE-LABEL: v4i64:
; PWR10BE: # %bb.0: # %entry
; PWR10BE-NEXT: xxlor vs0, v2, v3
-; PWR10BE-NEXT: xxswapd v2, vs0
-; PWR10BE-NEXT: xxlor vs0, vs0, v2
+; PWR10BE-NEXT: xxswapd v4, vs0
+; PWR10BE-NEXT: xxeval vs0, v2, v3, v4, 127
; PWR10BE-NEXT: mffprd r3, f0
; PWR10BE-NEXT: blr
entry:
@@ -300,21 +300,21 @@ define dso_local i64 @v8i64(<8 x i64> %a) local_unnamed_addr #0 {
;
; PWR10LE-LABEL: v8i64:
; PWR10LE: # %bb.0: # %entry
-; PWR10LE-NEXT: xxlor vs0, v3, v5
; PWR10LE-NEXT: xxlor vs1, v2, v4
-; PWR10LE-NEXT: xxlor vs0, vs1, vs0
-; PWR10LE-NEXT: xxswapd v2, vs0
-; PWR10LE-NEXT: xxlor vs0, vs0, v2
+; PWR10LE-NEXT: xxlor vs0, v3, v5
+; PWR10LE-NEXT: xxeval vs2, vs1, v3, v5, 127
+; PWR10LE-NEXT: xxswapd v2, vs2
+; PWR10LE-NEXT: xxeval vs0, vs1, vs0, v2, 127
; PWR10LE-NEXT: mfvsrld r3, vs0
; PWR10LE-NEXT: blr
;
; PWR10BE-LABEL: v8i64:
; PWR10BE: # %bb.0: # %entry
-; PWR10BE-NEXT: xxlor vs0, v3, v5
; PWR10BE-NEXT: xxlor vs1, v2, v4
-; PWR10BE-NEXT: xxlor vs0, vs1, vs0
-; PWR10BE-NEXT: xxswapd v2, vs0
-; PWR10BE-NEXT: xxlor vs0, vs0, v2
+; PWR10BE-NEXT: xxlor vs0, v3, v5
+; PWR10BE-NEXT: xxeval vs2, vs1, v3, v5, 127
+; PWR10BE-NEXT: xxswapd v2, vs2
+; PWR10BE-NEXT: xxeval vs0, vs1, vs0, v2, 127
; PWR10BE-NEXT: mffprd r3, f0
; PWR10BE-NEXT: blr
entry:
@@ -353,29 +353,27 @@ define dso_local i64 @v16i64(<16 x i64> %a) local_unnamed_addr #0 {
;
; PWR10LE-LABEL: v16i64:
; PWR10LE: # %bb.0: # %entry
-; PWR10LE-NEXT: xxlor vs0, v4, v8
; PWR10LE-NEXT: xxlor vs1, v2, v6
-; PWR10LE-NEXT: xxlor vs2, v5, v9
-; PWR10LE-NEXT: xxlor vs3, v3, v7
-; PWR10LE-NEXT: xxlor vs2, vs3, vs2
-; PWR10LE-NEXT: xxlor vs0, vs1, vs0
-; PWR10LE-NEXT: xxlor vs0, vs0, vs2
+; PWR10LE-NEXT: xxlor vs0, v5, v9
+; PWR10LE-NEXT: xxlor vs2, v3, v7
+; PWR10LE-NEXT: xxeval vs1, vs1, v4, v8, 127
+; PWR10LE-NEXT: xxeval vs3, vs2, v5, v9, 127
+; PWR10LE-NEXT: xxeval vs0, vs1, vs2, vs0, 127
; PWR10LE-NEXT: xxswapd v2, vs0
-; PWR10LE-NEXT: xxlor vs0, vs0, v2
+; PWR10LE-NEXT: xxeval vs0, vs1, vs3, v2, 127
; PWR10LE-NEXT: mfvsrld r3, vs0
; PWR10LE-NEXT: blr
;
; PWR10BE-LABEL: v16i64:
; PWR10BE: # %bb.0: # %entry
-; PWR10BE-NEXT: xxlor vs0, v4, v8
; PWR10BE-NEXT: xxlor vs1, v2, v6
-; PWR10BE-NEXT: xxlor vs2, v5, v9
-; PWR10BE-NEXT: xxlor vs3, v3, v7
-; PWR10BE-NEXT: xxlor vs2, vs3, vs2
-; PWR10BE-NEXT: xxlor vs0, vs1, vs0
-; PWR10BE-NEXT: xxlor vs0, vs0, vs2
+; PWR10BE-NEXT: xxlor vs0, v5, v9
+; PWR10BE-NEXT: xxlor vs2, v3, v7
+; PWR10BE-NEXT: xxeval vs1, vs1, v4, v8, 127
+; PWR10BE-NEXT: xxeval vs3, vs2, v5, v9, 127
+; PWR10BE-NEXT: xxeval vs0, vs1, vs2, vs0, 127
; PWR10BE-NEXT: xxswapd v2, vs0
-; PWR10BE-NEXT: xxlor vs0, vs0, v2
+; PWR10BE-NEXT: xxeval vs0, vs1, vs3, v2, 127
; PWR10BE-NEXT: mffprd r3, f0
; PWR10BE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/vector-reduce-xor.ll b/llvm/test/CodeGen/PowerPC/vector-reduce-xor.ll
index 552ca9a69724..6d799601a68d 100644
--- a/llvm/test/CodeGen/PowerPC/vector-reduce-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/vector-reduce-xor.ll
@@ -74,8 +74,8 @@ define dso_local i32 @v4i32(<4 x i32> %a) local_unnamed_addr #0 {
; PWR10LE-NEXT: xxswapd v3, v2
; PWR10LE-NEXT: li r3, 0
; PWR10LE-NEXT: xxlxor vs0, v2, v3
-; PWR10LE-NEXT: xxspltw vs1, vs0, 2
-; PWR10LE-NEXT: xxlxor v2, vs0, vs1
+; PWR10LE-NEXT: xxspltw vs0, vs0, 2
+; PWR10LE-NEXT: xxeval v2, v2, v3, vs0, 105
; PWR10LE-NEXT: vextuwrx r3, r3, v2
; PWR10LE-NEXT: blr
;
@@ -84,8 +84,8 @@ define dso_local i32 @v4i32(<4 x i32> %a) local_unnamed_addr #0 {
; PWR10BE-NEXT: xxswapd v3, v2
; PWR10BE-NEXT: li r3, 0
; PWR10BE-NEXT: xxlxor vs0, v2, v3
-; PWR10BE-NEXT: xxspltw vs1, vs0, 1
-; PWR10BE-NEXT: xxlxor v2, vs0, vs1
+; PWR10BE-NEXT: xxspltw vs0, vs0, 1
+; PWR10BE-NEXT: xxeval v2, v2, v3, vs0, 105
; PWR10BE-NEXT: vextuwlx r3, r3, v2
; PWR10BE-NEXT: blr
entry:
@@ -120,10 +120,10 @@ define dso_local i32 @v8i32(<8 x i32> %a) local_unnamed_addr #0 {
; PWR10LE: # %bb.0: # %entry
; PWR10LE-NEXT: xxlxor vs0, v2, v3
; PWR10LE-NEXT: li r3, 0
-; PWR10LE-NEXT: xxswapd v2, vs0
-; PWR10LE-NEXT: xxlxor vs0, vs0, v2
-; PWR10LE-NEXT: xxspltw vs1, vs0, 2
-; PWR10LE-NEXT: xxlxor v2, vs0, vs1
+; PWR10LE-NEXT: xxswapd v4, vs0
+; PWR10LE-NEXT: xxeval vs1, v2, v3, v4, 105
+; PWR10LE-NEXT: xxspltw vs1, vs1, 2
+; PWR10LE-NEXT: xxeval v2, vs0, v4, vs1, 105
; PWR10LE-NEXT: vextuwrx r3, r3, v2
; PWR10LE-NEXT: blr
;
@@ -131,10 +131,10 @@ define dso_local i32 @v8i32(<8 x i32> %a) local_unnamed_addr #0 {
; PWR10BE: # %bb.0: # %entry
; PWR10BE-NEXT: xxlxor vs0, v2, v3
; PWR10BE-NEXT: li r3, 0
-; PWR10BE-NEXT: xxswapd v2, vs0
-; PWR10BE-NEXT: xxlxor vs0, vs0, v2
-; PWR10BE-NEXT: xxspltw vs1, vs0, 1
-; PWR10BE-NEXT: xxlxor v2, vs0, vs1
+; PWR10BE-NEXT: xxswapd v4, vs0
+; PWR10BE-NEXT: xxeval vs1, v2, v3, v4, 105
+; PWR10BE-NEXT: xxspltw vs1, vs1, 1
+; PWR10BE-NEXT: xxeval v2, vs0, v4, vs1, 105
; PWR10BE-NEXT: vextuwlx r3, r3, v2
; PWR10BE-NEXT: blr
entry:
@@ -171,27 +171,27 @@ define dso_local i32 @v16i32(<16 x i32> %a) local_unnamed_addr #0 {
;
; PWR10LE-LABEL: v16i32:
; PWR10LE: # %bb.0: # %entry
-; PWR10LE-NEXT: xxlxor vs0, v3, v5
; PWR10LE-NEXT: xxlxor vs1, v2, v4
+; PWR10LE-NEXT: xxlxor vs0, v3, v5
; PWR10LE-NEXT: li r3, 0
-; PWR10LE-NEXT: xxlxor vs0, vs1, vs0
-; PWR10LE-NEXT: xxswapd v2, vs0
-; PWR10LE-NEXT: xxlxor vs0, vs0, v2
-; PWR10LE-NEXT: xxspltw vs1, vs0, 2
-; PWR10LE-NEXT: xxlxor v2, vs0, vs1
+; PWR10LE-NEXT: xxeval vs2, vs1, v3, v5, 105
+; PWR10LE-NEXT: xxswapd v2, vs2
+; PWR10LE-NEXT: xxeval vs0, vs1, vs0, v2, 105
+; PWR10LE-NEXT: xxspltw vs0, vs0, 2
+; PWR10LE-NEXT: xxeval v2, vs2, v2, vs0, 105
; PWR10LE-NEXT: vextuwrx r3, r3, v2
; PWR10LE-NEXT: blr
;
; PWR10BE-LABEL: v16i32:
; PWR10BE: # %bb.0: # %entry
-; PWR10BE-NEXT: xxlxor vs0, v3, v5
; PWR10BE-NEXT: xxlxor vs1, v2, v4
+; PWR10BE-NEXT: xxlxor vs0, v3, v5
; PWR10BE-NEXT: li r3, 0
-; PWR10BE-NEXT: xxlxor vs0, vs1, vs0
-; PWR10BE-NEXT: xxswapd v2, vs0
-; PWR10BE-NEXT: xxlxor vs0, vs0, v2
-; PWR10BE-NEXT: xxspltw vs1, vs0, 1
-; PWR10BE-NEXT: xxlxor v2, vs0, vs1
+; PWR10BE-NEXT: xxeval vs2, vs1, v3, v5, 105
+; PWR10BE-NEXT: xxswapd v2, vs2
+; PWR10BE-NEXT: xxeval vs0, vs1, vs0, v2, 105
+; PWR10BE-NEXT: xxspltw vs0, vs0, 1
+; PWR10BE-NEXT: xxeval v2, vs2, v2, vs0, 105
; PWR10BE-NEXT: vextuwlx r3, r3, v2
; PWR10BE-NEXT: blr
entry:
@@ -260,16 +260,16 @@ define dso_local i64 @v4i64(<4 x i64> %a) local_unnamed_addr #0 {
; PWR10LE-LABEL: v4i64:
; PWR10LE: # %bb.0: # %entry
; PWR10LE-NEXT: xxlxor vs0, v2, v3
-; PWR10LE-NEXT: xxswapd v2, vs0
-; PWR10LE-NEXT: xxlxor vs0, vs0, v2
+; PWR10LE-NEXT: xxswapd v4, vs0
+; PWR10LE-NEXT: xxeval vs0, v2, v3, v4, 105
; PWR10LE-NEXT: mfvsrld r3, vs0
; PWR10LE-NEXT: blr
;
; PWR10BE-LABEL: v4i64:
; PWR10BE: # %bb.0: # %entry
; PWR10BE-NEXT: xxlxor vs0, v2, v3
-; PWR10BE-NEXT: xxswapd v2, vs0
-; PWR10BE-NEXT: xxlxor vs0, vs0, v2
+; PWR10BE-NEXT: xxswapd v4, vs0
+; PWR10BE-NEXT: xxeval vs0, v2, v3, v4, 105
; PWR10BE-NEXT: mffprd r3, f0
; PWR10BE-NEXT: blr
entry:
@@ -300,21 +300,21 @@ define dso_local i64 @v8i64(<8 x i64> %a) local_unnamed_addr #0 {
;
; PWR10LE-LABEL: v8i64:
; PWR10LE: # %bb.0: # %entry
-; PWR10LE-NEXT: xxlxor vs0, v3, v5
; PWR10LE-NEXT: xxlxor vs1, v2, v4
-; PWR10LE-NEXT: xxlxor vs0, vs1, vs0
-; PWR10LE-NEXT: xxswapd v2, vs0
-; PWR10LE-NEXT: xxlxor vs0, vs0, v2
+; PWR10LE-NEXT: xxlxor vs0, v3, v5
+; PWR10LE-NEXT: xxeval vs2, vs1, v3, v5, 105
+; PWR10LE-NEXT: xxswapd v2, vs2
+; PWR10LE-NEXT: xxeval vs0, vs1, vs0, v2, 105
; PWR10LE-NEXT: mfvsrld r3, vs0
; PWR10LE-NEXT: blr
;
; PWR10BE-LABEL: v8i64:
; PWR10BE: # %bb.0: # %entry
-; PWR10BE-NEXT: xxlxor vs0, v3, v5
; PWR10BE-NEXT: xxlxor vs1, v2, v4
-; PWR10BE-NEXT: xxlxor vs0, vs1, vs0
-; PWR10BE-NEXT: xxswapd v2, vs0
-; PWR10BE-NEXT: xxlxor vs0, vs0, v2
+; PWR10BE-NEXT: xxlxor vs0, v3, v5
+; PWR10BE-NEXT: xxeval vs2, vs1, v3, v5, 105
+; PWR10BE-NEXT: xxswapd v2, vs2
+; PWR10BE-NEXT: xxeval vs0, vs1, vs0, v2, 105
; PWR10BE-NEXT: mffprd r3, f0
; PWR10BE-NEXT: blr
entry:
@@ -353,29 +353,27 @@ define dso_local i64 @v16i64(<16 x i64> %a) local_unnamed_addr #0 {
;
; PWR10LE-LABEL: v16i64:
; PWR10LE: # %bb.0: # %entry
-; PWR10LE-NEXT: xxlxor vs0, v4, v8
; PWR10LE-NEXT: xxlxor vs1, v2, v6
-; PWR10LE-NEXT: xxlxor vs2, v5, v9
-; PWR10LE-NEXT: xxlxor vs3, v3, v7
-; PWR10LE-NEXT: xxlxor vs2, vs3, vs2
-; PWR10LE-NEXT: xxlxor vs0, vs1, vs0
-; PWR10LE-NEXT: xxlxor vs0, vs0, vs2
+; PWR10LE-NEXT: xxlxor vs0, v5, v9
+; PWR10LE-NEXT: xxlxor vs2, v3, v7
+; PWR10LE-NEXT: xxeval vs1, vs1, v4, v8, 105
+; PWR10LE-NEXT: xxeval vs3, vs2, v5, v9, 105
+; PWR10LE-NEXT: xxeval vs0, vs1, vs2, vs0, 105
; PWR10LE-NEXT: xxswapd v2, vs0
-; PWR10LE-NEXT: xxlxor vs0, vs0, v2
+; PWR10LE-NEXT: xxeval vs0, vs1, vs3, v2, 105
; PWR10LE-NEXT: mfvsrld r3, vs0
; PWR10LE-NEXT: blr
;
; PWR10BE-LABEL: v16i64:
; PWR10BE: # %bb.0: # %entry
-; PWR10BE-NEXT: xxlxor vs0, v4, v8
; PWR10BE-NEXT: xxlxor vs1, v2, v6
-; PWR10BE-NEXT: xxlxor vs2, v5, v9
-; PWR10BE-NEXT: xxlxor vs3, v3, v7
-; PWR10BE-NEXT: xxlxor vs2, vs3, vs2
-; PWR10BE-NEXT: xxlxor vs0, vs1, vs0
-; PWR10BE-NEXT: xxlxor vs0, vs0, vs2
+; PWR10BE-NEXT: xxlxor vs0, v5, v9
+; PWR10BE-NEXT: xxlxor vs2, v3, v7
+; PWR10BE-NEXT: xxeval vs1, vs1, v4, v8, 105
+; PWR10BE-NEXT: xxeval vs3, vs2, v5, v9, 105
+; PWR10BE-NEXT: xxeval vs0, vs1, vs2, vs0, 105
; PWR10BE-NEXT: xxswapd v2, vs0
-; PWR10BE-NEXT: xxlxor vs0, vs0, v2
+; PWR10BE-NEXT: xxeval vs0, vs1, vs3, v2, 105
; PWR10BE-NEXT: mffprd r3, f0
; PWR10BE-NEXT: blr
entry:
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