[llvm] e493944 - [RISCV] Use SLTIU X, -1 for (setne X, -1).
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 11 15:36:31 PDT 2022
Author: Craig Topper
Date: 2022-08-11T15:36:04-07:00
New Revision: e493944f5fa40181ada7d897af39fef932325169
URL: https://github.com/llvm/llvm-project/commit/e493944f5fa40181ada7d897af39fef932325169
DIFF: https://github.com/llvm/llvm-project/commit/e493944f5fa40181ada7d897af39fef932325169.diff
LOG: [RISCV] Use SLTIU X, -1 for (setne X, -1).
Since -1 is the maximum unsigned value, all values less than it
are not equal to it.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/fpclamptosat.ll
llvm/test/CodeGen/RISCV/i32-icmp.ll
llvm/test/CodeGen/RISCV/i64-icmp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 6b0d790f913d..fdbad27ba951 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1271,6 +1271,7 @@ def : Pat<(setne GPR:$rs1, simm12_plus1:$imm12),
(SLTU X0, (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>;
def : Pat<(setne GPR:$rs1, -2048),
(SLTU X0, (XORI GPR:$rs1, -2048))>;
+def : Pat<(setne GPR:$rs1, -1), (SLTIU GPR:$rs1, -1)>;
def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>;
def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;
diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat.ll b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
index ee4ecbcc2d69..56c7a36a5599 100644
--- a/llvm/test/CodeGen/RISCV/fpclamptosat.ll
+++ b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
@@ -118,8 +118,7 @@ define i32 @utest_f64i32(double %x) {
; RV32IF-NEXT: beqz a1, .LBB1_3
; RV32IF-NEXT: j .LBB1_4
; RV32IF-NEXT: .LBB1_2:
-; RV32IF-NEXT: addi a1, a0, 1
-; RV32IF-NEXT: snez a1, a1
+; RV32IF-NEXT: sltiu a1, a0, -1
; RV32IF-NEXT: bnez a1, .LBB1_4
; RV32IF-NEXT: .LBB1_3: # %entry
; RV32IF-NEXT: li a0, -1
@@ -186,8 +185,7 @@ define i32 @ustest_f64i32(double %x) {
; RV32IF-NEXT: beqz a2, .LBB2_3
; RV32IF-NEXT: j .LBB2_4
; RV32IF-NEXT: .LBB2_2:
-; RV32IF-NEXT: addi a2, a0, 1
-; RV32IF-NEXT: snez a2, a2
+; RV32IF-NEXT: sltiu a2, a0, -1
; RV32IF-NEXT: bnez a2, .LBB2_4
; RV32IF-NEXT: .LBB2_3: # %entry
; RV32IF-NEXT: li a1, 0
@@ -452,8 +450,7 @@ define i32 @utesth_f16i32(half %x) {
; RV32-NEXT: beqz a1, .LBB7_3
; RV32-NEXT: j .LBB7_4
; RV32-NEXT: .LBB7_2:
-; RV32-NEXT: addi a1, a0, 1
-; RV32-NEXT: snez a1, a1
+; RV32-NEXT: sltiu a1, a0, -1
; RV32-NEXT: bnez a1, .LBB7_4
; RV32-NEXT: .LBB7_3: # %entry
; RV32-NEXT: li a0, -1
@@ -504,8 +501,7 @@ define i32 @ustest_f16i32(half %x) {
; RV32-NEXT: beqz a2, .LBB8_3
; RV32-NEXT: j .LBB8_4
; RV32-NEXT: .LBB8_2:
-; RV32-NEXT: addi a2, a0, 1
-; RV32-NEXT: snez a2, a2
+; RV32-NEXT: sltiu a2, a0, -1
; RV32-NEXT: bnez a2, .LBB8_4
; RV32-NEXT: .LBB8_3: # %entry
; RV32-NEXT: li a1, 0
@@ -1110,8 +1106,7 @@ define i64 @stest_f64i64(double %x) {
; RV32IF-NEXT: bnez a6, .LBB18_3
; RV32IF-NEXT: j .LBB18_4
; RV32IF-NEXT: .LBB18_2:
-; RV32IF-NEXT: addi a6, a0, 1
-; RV32IF-NEXT: snez a7, a6
+; RV32IF-NEXT: sltiu a7, a0, -1
; RV32IF-NEXT: or a6, a3, a2
; RV32IF-NEXT: beqz a6, .LBB18_4
; RV32IF-NEXT: .LBB18_3: # %entry
@@ -1206,8 +1201,7 @@ define i64 @stest_f64i64(double %x) {
; RV32IFD-NEXT: bnez a6, .LBB18_3
; RV32IFD-NEXT: j .LBB18_4
; RV32IFD-NEXT: .LBB18_2:
-; RV32IFD-NEXT: addi a6, a0, 1
-; RV32IFD-NEXT: snez a7, a6
+; RV32IFD-NEXT: sltiu a7, a0, -1
; RV32IFD-NEXT: or a6, a3, a2
; RV32IFD-NEXT: beqz a6, .LBB18_4
; RV32IFD-NEXT: .LBB18_3: # %entry
@@ -1542,8 +1536,7 @@ define i64 @stest_f32i64(float %x) {
; RV32-NEXT: bnez a6, .LBB21_3
; RV32-NEXT: j .LBB21_4
; RV32-NEXT: .LBB21_2:
-; RV32-NEXT: addi a6, a0, 1
-; RV32-NEXT: snez a7, a6
+; RV32-NEXT: sltiu a7, a0, -1
; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: beqz a6, .LBB21_4
; RV32-NEXT: .LBB21_3: # %entry
@@ -1779,8 +1772,7 @@ define i64 @stest_f16i64(half %x) {
; RV32-NEXT: bnez a6, .LBB24_3
; RV32-NEXT: j .LBB24_4
; RV32-NEXT: .LBB24_2:
-; RV32-NEXT: addi a6, a0, 1
-; RV32-NEXT: snez a7, a6
+; RV32-NEXT: sltiu a7, a0, -1
; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: beqz a6, .LBB24_4
; RV32-NEXT: .LBB24_3: # %entry
diff --git a/llvm/test/CodeGen/RISCV/i32-icmp.ll b/llvm/test/CodeGen/RISCV/i32-icmp.ll
index 3120f3a9b511..dc9c545ae1c0 100644
--- a/llvm/test/CodeGen/RISCV/i32-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/i32-icmp.ll
@@ -158,6 +158,16 @@ define i32 @icmp_nez(i32 %a) nounwind {
ret i32 %2
}
+define i32 @icmp_ne_neg_1(i32 %a) nounwind {
+; RV32I-LABEL: icmp_ne_neg_1:
+; RV32I: # %bb.0:
+; RV32I-NEXT: sltiu a0, a0, -1
+; RV32I-NEXT: ret
+ %1 = icmp ne i32 %a, -1
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
define i32 @icmp_ugt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ugt:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/i64-icmp.ll b/llvm/test/CodeGen/RISCV/i64-icmp.ll
index b819d1f45d67..452737994601 100644
--- a/llvm/test/CodeGen/RISCV/i64-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/i64-icmp.ll
@@ -158,6 +158,16 @@ define i64 @icmp_nez(i64 %a) nounwind {
ret i64 %2
}
+define i64 @icmp_ne_neg_1(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ne_neg_1:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltiu a0, a0, -1
+; RV64I-NEXT: ret
+ %1 = icmp ne i64 %a, -1
+ %2 = zext i1 %1 to i64
+ ret i64 %2
+}
+
define i64 @icmp_ugt(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_ugt:
; RV64I: # %bb.0:
@@ -744,10 +754,10 @@ define i64 @icmp_ne_zext_inreg_umin(i64 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 30141
; RV64I-NEXT: addiw a1, a1, -747
-; RV64I-NEXT: bltu a0, a1, .LBB66_2
+; RV64I-NEXT: bltu a0, a1, .LBB67_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: .LBB66_2:
+; RV64I-NEXT: .LBB67_2:
; RV64I-NEXT: addi a0, a0, -123
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
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