[PATCH] D131729: [RISCV] Move xori creation for scalar setccs to lowering.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rv32zbt.ll:656
-; RV32ZBT-NEXT:    xori a3, a3, 1
-; RV32ZBT-NEXT:    cmov a2, t0, a3, a2
-; RV32ZBT-NEXT:    cmov a0, a2, a0, a6
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The two xoris were the true and false values of the first cmov. The later two cmovs use the first cmov as a condition. We are now able to pull the xoris through the first cmov and fold it into the condition of the other two by swapping their true and false values.


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Comment at: llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll:510
 ; RV64M-NEXT:    sltiu a2, a2, 293
+; RV64M-NEXT:    addiw a1, a1, -1
 ; RV64M-NEXT:    addiw a2, a2, -1
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This appears to be a scheduling change only


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Comment at: llvm/test/CodeGen/RISCV/xaluo.ll:788
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    li a2, -2
+; RV32-NEXT:    sub a3, a2, a0
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This is a special case related to the constant value -2. Originally we had setugt x, -2, which was converted to seteq x, -1 since that's the the only value unsigned greater than -2. We now convert it to the setult -2, x and the DAG combine misses the seteq opportunity since the constant is on the left hand side. This allows use to use the -2 for both the sub and the sltu.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131729/new/

https://reviews.llvm.org/D131729