[PATCH] D131617: [RISCV] Re-enable JIT support

[Jonas Hahnfeld via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG940733d6a0a9: [RISCV] Re-enable JIT support (authored by Hahnfeld).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131617/new/

https://reviews.llvm.org/D131617

Files:
  llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp


Index: llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
+++ llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
@@ -21,8 +21,8 @@
 }
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetInfo() {
-  RegisterTarget<Triple::riscv32> X(getTheRISCV32Target(), "riscv32",
-                                    "32-bit RISC-V", "RISCV");
-  RegisterTarget<Triple::riscv64> Y(getTheRISCV64Target(), "riscv64",
-                                    "64-bit RISC-V", "RISCV");
+  RegisterTarget<Triple::riscv32, /*HasJIT=*/true> X(
+      getTheRISCV32Target(), "riscv32", "32-bit RISC-V", "RISCV");
+  RegisterTarget<Triple::riscv64, /*HasJIT=*/true> Y(
+      getTheRISCV64Target(), "riscv64", "64-bit RISC-V", "RISCV");
 }


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