[PATCH] D131093: [LV] Restructure isPredicatedInst and isScalarWithPredication (w/a fix for uniform mem ops)

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:1438
 
-  /// Returns true if \p I is an instruction that will be scalarized with
-  /// predication when vectorizing \p I with vectorization factor \p VF. Such
-  /// instructions include conditional stores and instructions that may divide
-  /// by zero.
+  /// Returns true if \p I is an instrcution which requires predication and
+  /// for which our chosen predication strategy is scalarization (i.e. we
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nit: I think it should be 'instruction'


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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll:585
 ;
 ; TF-SCALABLE-LABEL: @uniform_load_unaligned(
 ; TF-SCALABLE-NEXT:  entry:
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I tried vectorising these tests with SVE (`opt -loop-vectorize -mattr=+sve -mtriple=aarch64-linux-gnu < ../llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll -S`) and it already works today without this patch. In fact it works both and without tail-folding enabled. Do you know why RISC-V is different to SVE and why this patch is needed to vectorise?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D131093/new/

https://reviews.llvm.org/D131093