[PATCH] D131512: [LoongArch] Add insn aliases `jr` and `ret`
Lu Weining via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 10 19:03:14 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGed078c48f0d7: [LoongArch] Add insn aliases `jr` and `ret` (authored by WANG Xuerui <git at xen0n.name>, committed by SixWeining).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D131512/new/
https://reviews.llvm.org/D131512
Files:
llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
llvm/test/CodeGen/LoongArch/analyze-branch.ll
llvm/test/CodeGen/LoongArch/bitreverse.ll
llvm/test/CodeGen/LoongArch/bstrins_d.ll
llvm/test/CodeGen/LoongArch/bstrins_w.ll
llvm/test/CodeGen/LoongArch/bstrpick_d.ll
llvm/test/CodeGen/LoongArch/bstrpick_w.ll
llvm/test/CodeGen/LoongArch/bswap-bitreverse.ll
llvm/test/CodeGen/LoongArch/bswap.ll
llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll
llvm/test/CodeGen/LoongArch/double-imm.ll
llvm/test/CodeGen/LoongArch/float-imm.ll
llvm/test/CodeGen/LoongArch/frame.ll
llvm/test/CodeGen/LoongArch/imm.ll
llvm/test/CodeGen/LoongArch/ir-instruction/add.ll
llvm/test/CodeGen/LoongArch/ir-instruction/and.ll
llvm/test/CodeGen/LoongArch/ir-instruction/ashr.ll
llvm/test/CodeGen/LoongArch/ir-instruction/br.ll
llvm/test/CodeGen/LoongArch/ir-instruction/call.ll
llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll
llvm/test/CodeGen/LoongArch/ir-instruction/fadd.ll
llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-dbl.ll
llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-flt.ll
llvm/test/CodeGen/LoongArch/ir-instruction/fdiv.ll
llvm/test/CodeGen/LoongArch/ir-instruction/fence.ll
llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
llvm/test/CodeGen/LoongArch/ir-instruction/fmul.ll
llvm/test/CodeGen/LoongArch/ir-instruction/fneg.ll
llvm/test/CodeGen/LoongArch/ir-instruction/fsub.ll
llvm/test/CodeGen/LoongArch/ir-instruction/icmp.ll
llvm/test/CodeGen/LoongArch/ir-instruction/indirectbr.ll
llvm/test/CodeGen/LoongArch/ir-instruction/load-store-atomic.ll
llvm/test/CodeGen/LoongArch/ir-instruction/load-store.ll
llvm/test/CodeGen/LoongArch/ir-instruction/lshr.ll
llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll
llvm/test/CodeGen/LoongArch/ir-instruction/or.ll
llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
llvm/test/CodeGen/LoongArch/ir-instruction/select-bare-dbl.ll
llvm/test/CodeGen/LoongArch/ir-instruction/select-bare-flt.ll
llvm/test/CodeGen/LoongArch/ir-instruction/select-bare-int.ll
llvm/test/CodeGen/LoongArch/ir-instruction/select-fpcc-dbl.ll
llvm/test/CodeGen/LoongArch/ir-instruction/select-fpcc-flt.ll
llvm/test/CodeGen/LoongArch/ir-instruction/select-fpcc-int.ll
llvm/test/CodeGen/LoongArch/ir-instruction/select-icc-dbl.ll
llvm/test/CodeGen/LoongArch/ir-instruction/select-icc-flt.ll
llvm/test/CodeGen/LoongArch/ir-instruction/select-icc-int.ll
llvm/test/CodeGen/LoongArch/ir-instruction/sext-zext-trunc.ll
llvm/test/CodeGen/LoongArch/ir-instruction/shl.ll
llvm/test/CodeGen/LoongArch/ir-instruction/sub.ll
llvm/test/CodeGen/LoongArch/ir-instruction/xor.ll
llvm/test/CodeGen/LoongArch/not.ll
llvm/test/CodeGen/LoongArch/rotl-rotr.ll
llvm/test/CodeGen/LoongArch/shift-masked-shamt.ll
llvm/test/CodeGen/LoongArch/vararg.ll
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_function_name.ll.expected
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_generated_funcs.ll.generated.expected
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_generated_funcs.ll.nogenerated.expected
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