[PATCH] D131587: [CodeGen] Deduplicate restore blocks in branch relaxation

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For multiple far branches to the same destination, there are chances that some restore blocks could be shared if they clobber the same registers and share the same restore sequence.

This patch stores all restore blocks for a destination in RestoreBlocks in the destination's BasicBlockInfo, allowing the target to call `DeduplicateRestoreBB()` to find a previously inserted restore block identical to RestoreBB and insert an unconditional branch to it, then `BranchRelaxation::fixupUnconditionalBranch()` can erase RestoreBB from the function.

Suppose `jump .dest` is out of range so need a register to jump indirectly in the following code.

  .label_0:
          foo     1
          jump    .dest
  .label_1:
          foo     2
          jump    .dest
  .label_2:
          bar
          bar
          bar
          bar
  .dest:
          baz

Without this patch, it will be relaxed to:

  .label_0:
          foo     1
          store   reg1, (sp)
          mov     reg1, .restore_1
          jump    reg1
  .label_1:
          foo     2
          store   reg1, (sp)
          mov     reg1, .restore_2
          jump    reg1
  .label_2:
          bar
          bar
          bar
          bar
  .restore_1:
          load    reg1, (sp)
          jump    .dest
  .restore_2:
          load    reg1, (sp)
  .dest:
          baz

With this patch, restore blocks can be deduplicated, thus generating the following code:

          foo
          store   reg1, (sp)
          mov     reg1, .restore_1
          jump    reg1
  .label_1:
          foo
          store   reg1, (sp)
          mov     reg1, .restore_1
          jump    reg1
  .label_2:
          bar
          bar
          bar
          bar
  .restore_1:
          load    reg1, (sp)
  .dest:
          baz


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131587

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/BranchRelaxation.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AVR/AVRInstrInfo.cpp
  llvm/lib/Target/AVR/AVRInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll

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