[PATCH] D131340: [RISC-V][HWASAN] Add intrinsics required for HWASAN support for RISC-V

[Alexey Baturo via Phabricator via llvm-commits]

smd added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:149
 
+def GPRNoX1X6X7X28X29X30X31 : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, X1, X6, X7, X28, X29, X30, X31)> {
+  let RegInfos = XLenRI;
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jrtc27 wrote:
> smd wrote:
> > craig.topper wrote:
> > > I think this line probably exceeds 80 characters
> > Fixed, thanks
> Why is this set of registers what it is? This is not a helpful name. It looks like this is in fact the set of GPRs minus RA and all temporary registers other than t0. The AArch64 equivalent has:
> 
> ```
> // Register set that excludes registers that are reserved for procedure calls.
> // This is used for pseudo-instructions that are actually implemented using a
> // procedure call.
> ```
Thanks for catching this, you're right, there's no need to introduce a new register class like this and GPRJALR should be used instead. 


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https://reviews.llvm.org/D131340