[PATCH] D131568: [RISCV] Set HasJIT to True when register target

[luxufan via Phabricator via llvm-commits]

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Since Orc JIT has been supported on riscv32 and riscv64, Variable
`HasJIT` should be True; Otherwise lli would report error: Target has
no JIT support.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131568

Files:
  llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp


Index: llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
+++ llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
@@ -21,8 +21,8 @@
 }
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetInfo() {
-  RegisterTarget<Triple::riscv32> X(getTheRISCV32Target(), "riscv32",
-                                    "32-bit RISC-V", "RISCV");
-  RegisterTarget<Triple::riscv64> Y(getTheRISCV64Target(), "riscv64",
-                                    "64-bit RISC-V", "RISCV");
+  RegisterTarget<Triple::riscv32, /*HasJIT=*/true> X(
+      getTheRISCV32Target(), "riscv32", "32-bit RISC-V", "RISCV");
+  RegisterTarget<Triple::riscv64, /*HasJIT=*/true> Y(
+      getTheRISCV64Target(), "riscv64", "64-bit RISC-V", "RISCV");
 }


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