[PATCH] D131503: [DAGCombine] Combine signext_inreg of extract-extend

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:13170
+      SDValue SignExtExtendee =
+          DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), InnerExtVT, Extendee);
+      return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), VT, SignExtExtendee,
----------------
RKSimon wrote:
> Does this need an operation legality check for ISD::SIGN_EXTEND ? `(!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, InnerExtVT))`?
The combine only replaces an extant any-extend with an equivalent sign-extend. Is it an unreasonable assumption that if a target supports an any-extend it won't support the equivalent sign or zero extend? I can add the condition if you think this is suspect.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131503/new/

https://reviews.llvm.org/D131503