[PATCH] D131508: [WIP][RISCV] Enable fixed length vectorization

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D131508#3711122 <https://reviews.llvm.org/D131508#3711122>, @barannikov88 wrote:

> In D131508#3711061 <https://reviews.llvm.org/D131508#3711061>, @reames wrote:
>
>> @barannikov88 - I don't see how your last comment connects to this review.  If you want to ask a question on your hardware, please email me and we can chat briefly.
>
> Sorry for intervening. I wanted to bring to your attention that if you map fixed vectors to scalable registers, you will need a way to know the effective size of the register when a need for a spill arises.
> I don't know if the ISA allows you to extract the number of elements from the internal part of the vector register, but you can always spill 128 bits (the min VLEN), wasting some stack space if the effective size is smaller.
> That is just of more importance for our target, so I was wondering how are you going to solve this spilling issue, if at all.

On RISCV, the current implementation of fixed length vectors uses however many bits of the vector register are required.  When spilling a vector register, we currently spill the full register, and make no attempt at tracking which sub-lanes are live.  We could in theory spill less if sub-lanes of the register are dead, but a) this is unlikely to be a significant stack savings, and b) the spill instructions easiest to use work on full vector registers.


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https://reviews.llvm.org/D131508