[llvm] ea323a4 - [X86][ARM] Update tests for bitwise logic trees of shifts; NFC

[Filipp Zhinkin via llvm-commits]

Author: Filipp Zhinkin
Date: 2022-08-09T20:57:14+03:00
New Revision: ea323a4bd5147ef8e8a6e4f144444e1e07664ec5

URL: https://github.com/llvm/llvm-project/commit/ea323a4bd5147ef8e8a6e4f144444e1e07664ec5
DIFF: https://github.com/llvm/llvm-project/commit/ea323a4bd5147ef8e8a6e4f144444e1e07664ec5.diff

LOG: [X86][ARM] Update tests for bitwise logic trees of shifts; NFC

Baseline tests for D131189.

Added: 
    

Modified: 
    llvm/test/CodeGen/ARM/shift-combine.ll
    llvm/test/CodeGen/X86/shift-combine.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/ARM/shift-combine.ll b/llvm/test/CodeGen/ARM/shift-combine.ll
index d0bd44ec8e8ba..3529947339b00 100644
--- a/llvm/test/CodeGen/ARM/shift-combine.ll
+++ b/llvm/test/CodeGen/ARM/shift-combine.ll
@@ -1044,7 +1044,7 @@ define i32 @xor_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {
   %a.shifted = lshr i32 %a, 16
   %c.shifted = lshr i32 %c, 16
   %xor.ab = xor i32 %a.shifted, %b
-  %xor.cd = xor i32 %c.shifted, %d
+  %xor.cd = xor i32 %d, %c.shifted
   %r = xor i32 %xor.ab, %xor.cd
   ret i32 %r
 }
@@ -1088,7 +1088,7 @@ define i32 @and_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {
 ; CHECK-V6M-NEXT:    bx lr
   %a.shifted = ashr i32 %a, 16
   %c.shifted = ashr i32 %c, 16
-  %and.ab = and i32 %a.shifted, %b
+  %and.ab = and i32 %b, %a.shifted
   %and.cd = and i32 %c.shifted, %d
   %r = and i32 %and.ab, %and.cd
   ret i32 %r
@@ -1143,8 +1143,8 @@ define i32 @logic_tree_with_shifts_var_i32(i32 %a, i32 %b, i32 %c, i32 %d, i32 %
 ; CHECK-V6M-NEXT:    pop {r4, pc}
   %a.shifted = shl i32 %a, %s
   %c.shifted = shl i32 %c, %s
-  %or.ab = or i32 %a.shifted, %b
-  %or.cd = or i32 %c.shifted, %d
+  %or.ab = or i32 %b, %a.shifted
+  %or.cd = or i32 %d, %c.shifted
   %r = or i32 %or.ab, %or.cd
   ret i32 %r
 }

diff  --git a/llvm/test/CodeGen/X86/shift-combine.ll b/llvm/test/CodeGen/X86/shift-combine.ll
index 5bfaa2f3f6c48..82b1afd4c93d7 100644
--- a/llvm/test/CodeGen/X86/shift-combine.ll
+++ b/llvm/test/CodeGen/X86/shift-combine.ll
@@ -558,7 +558,7 @@ define i32 @xor_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {
   %a.shifted = lshr i32 %a, 16
   %c.shifted = lshr i32 %c, 16
   %xor.ab = xor i32 %a.shifted, %b
-  %xor.cd = xor i32 %c.shifted, %d
+  %xor.cd = xor i32 %d, %c.shifted
   %r = xor i32 %xor.ab, %xor.cd
   ret i32 %r
 }
@@ -579,12 +579,12 @@ define i32 @and_tree_with_shifts_i32(i32 %a, i32 %b, i32 %c, i32 %d) {
 ; X64-NEXT:    sarl $16, %edi
 ; X64-NEXT:    sarl $16, %eax
 ; X64-NEXT:    andl %ecx, %eax
-; X64-NEXT:    andl %esi, %eax
 ; X64-NEXT:    andl %edi, %eax
+; X64-NEXT:    andl %esi, %eax
 ; X64-NEXT:    retq
   %a.shifted = ashr i32 %a, 16
   %c.shifted = ashr i32 %c, 16
-  %and.ab = and i32 %a.shifted, %b
+  %and.ab = and i32 %b, %a.shifted
   %and.cd = and i32 %c.shifted, %d
   %r = and i32 %and.ab, %and.cd
   ret i32 %r
@@ -610,13 +610,13 @@ define i32 @logic_tree_with_shifts_var_i32(i32 %a, i32 %b, i32 %c, i32 %d, i32 %
 ; X64-NEXT:    shll %cl, %edi
 ; X64-NEXT:    shll %cl, %edx
 ; X64-NEXT:    orl %edx, %eax
-; X64-NEXT:    orl %esi, %eax
 ; X64-NEXT:    orl %edi, %eax
+; X64-NEXT:    orl %esi, %eax
 ; X64-NEXT:    retq
   %a.shifted = shl i32 %a, %s
   %c.shifted = shl i32 %c, %s
-  %or.ab = or i32 %a.shifted, %b
-  %or.cd = or i32 %c.shifted, %d
+  %or.ab = or i32 %b, %a.shifted
+  %or.cd = or i32 %d, %c.shifted
   %r = or i32 %or.ab, %or.cd
   ret i32 %r
 }