[llvm] 8800b11 - [RISCV] Pin a test to scalar lowering to preserve test intent [nfc]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-08-09T10:12:18-07:00
New Revision: 8800b1103a4f5ac5e5a21c96a39cd382aa1ceccd

URL: https://github.com/llvm/llvm-project/commit/8800b1103a4f5ac5e5a21c96a39cd382aa1ceccd
DIFF: https://github.com/llvm/llvm-project/commit/8800b1103a4f5ac5e5a21c96a39cd382aa1ceccd.diff

LOG: [RISCV] Pin a test to scalar lowering to preserve test intent [nfc]

In an upcoming change to enable fixed length vector lowering via vector registers, the codepath exercised would change.  Pin this to the old lowering.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll b/llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
index f38ec08e4bd71..0139d8009a2e9 100644
--- a/llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
+++ b/llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
-; RUN:     | FileCheck %s --check-prefix=RV32
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
-; RUN:     | FileCheck %s --check-prefix=RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
+; RUN:     -riscv-v-vector-bits-min=0 < %s | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
+; RUN:     -riscv-v-vector-bits-min=0 < %s | FileCheck %s --check-prefix=RV64
 
 ; This test would lead one of the DAGCombiner's visitVSELECT optimizations to
 ; call getSetCCResultType, from which we'd return an invalid MVT (<3 x i1>)