[PATCH] D131508: [WIP][RISCV] Enable fixed length vectorization

[Philip Reames via Phabricator via llvm-commits]

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This is a WIP at the moment, not yet ready for review.

This change enables the use of RISCV's variable length vector registers for fixed length vectors in the IR, and implicitly enables various IR transforms which generate fixed length vectors if legal (e.g. LoopVectorize and SLPVectorize).  Specifically, this enables fixed length vectors which are known to be inbounds of the underlying variable hardware size.

For context, remember that the +V extension provides a minimum VLEN of 128.  The embedded variants provide lower minimums.  The analogy here is essentially vectorizing for SSE on a machine which may or may not include AVX2/AVX615.  We won't get full utilization by default, but we will get some benefit.  And of course, with an explicit mcpu we can vectorize to the exact target hardware.

The LV impact is mostly related to vectorizer robustness.  In cases we haven't yet fully implemented scalable vectorization support, we can fall back to fixed length vectorization.  Note that there a bunch of cases we haven't yet implemented, so in practice this is a fairly major shift towards auto-vectorizing more often.

On the SLP side, ... (haven't looked closely, thus WIP)


https://reviews.llvm.org/D131508

Files:
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/test/Analysis/CostModel/RISCV/active_lane_mask.ll
  llvm/test/CodeGen/RISCV/fold-vector-cmp.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
  llvm/test/Transforms/LoopVectorize/RISCV/illegal-type.ll
  llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
  llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll
  llvm/test/Transforms/LoopVectorize/RISCV/scalable-divrem.ll

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