[PATCH] D130141: [RISCV] Add MC support of RISCV Zca Extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/MC/RISCV/rv32c-only-valid.s:20
 # CHECK-ASM: encoding: [0xfd,0x2f]
 # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions)
 # CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set
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jrtc27 wrote:
> This needs ` or 'Zca' ...` adding otherwise you're not checking what you think you are. Are there cases of this in other files too?
I've added {{$}} to the end of all of these lines in https://reviews.llvm.org/D131436 so we'll require all extensions to be listed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130141/new/

https://reviews.llvm.org/D130141